1 /*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <common/bl_common.h>
10 #include <common/desc_image_load.h>
11
12 #include "ls_16550.h"
13 #include "plat_ls.h"
14 #include "ls_def.h"
15
16 /* Data structure which holds the extents of the trusted SRAM for BL2 */
17 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
18
19 /*******************************************************************************
20 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
21 * in x0. This memory layout is sitting at the base of the free trusted SRAM.
22 * Copy it to a safe location before its reclaimed by later BL2 functionality.
23 ******************************************************************************/
ls_bl2_early_platform_setup(meminfo_t * mem_layout)24 void ls_bl2_early_platform_setup(meminfo_t *mem_layout)
25 {
26 static console_t console;
27
28 /* Initialize the console to provide early debug support */
29 console_ls_16550_register(LS_TF_UART_BASE, LS_TF_UART_CLOCK,
30 LS_TF_UART_BAUDRATE, &console);
31
32 /* Setup the BL2 memory layout */
33 bl2_tzram_layout = *mem_layout;
34
35 /* Initialise the IO layer and register platform IO devices */
36 plat_ls_io_setup();
37 }
38
39 /*******************************************************************************
40 * Perform the very early platform specific architectural setup here. At the
41 * moment this is only initializes the mmu in a quick and dirty way.
42 ******************************************************************************/
ls_bl2_plat_arch_setup(void)43 void ls_bl2_plat_arch_setup(void)
44 {
45 ls_setup_page_tables(bl2_tzram_layout.total_base,
46 bl2_tzram_layout.total_size,
47 BL_CODE_BASE,
48 BL_CODE_END,
49 BL_RO_DATA_BASE,
50 BL_RO_DATA_END
51 #if USE_COHERENT_MEM
52 , BL_COHERENT_RAM_BASE,
53 BL_COHERENT_RAM_END
54 #endif
55 );
56
57 #ifdef __aarch64__
58 enable_mmu_el1(0);
59 #else
60 enable_mmu_svc_mon(0);
61 #endif
62 }
63
bl2_plat_arch_setup(void)64 void bl2_plat_arch_setup(void)
65 {
66 ls_bl2_plat_arch_setup();
67 }
68
ls_bl2_handle_post_image_load(unsigned int image_id)69 int ls_bl2_handle_post_image_load(unsigned int image_id)
70 {
71 int err = 0;
72 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
73
74 assert(bl_mem_params);
75
76 switch (image_id) {
77 #ifdef __aarch64__
78 case BL32_IMAGE_ID:
79 bl_mem_params->ep_info.spsr = ls_get_spsr_for_bl32_entry();
80 break;
81 #endif
82
83 case BL33_IMAGE_ID:
84 /* BL33 expects to receive the primary CPU MPID (through r0) */
85 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
86 bl_mem_params->ep_info.spsr = ls_get_spsr_for_bl33_entry();
87 break;
88 }
89
90 return err;
91 }
92
93 /*******************************************************************************
94 * This function can be used by the platforms to update/use image
95 * information for given `image_id`.
96 ******************************************************************************/
bl2_plat_handle_post_image_load(unsigned int image_id)97 int bl2_plat_handle_post_image_load(unsigned int image_id)
98 {
99 return ls_bl2_handle_post_image_load(image_id);
100 }
101