1 /* 2 * Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <lib/utils_def.h> 11 #include <lib/xlat_tables/xlat_tables_defs.h> 12 #include <plat/arm/board/common/v2m_def.h> 13 #include <plat/arm/common/arm_spm_def.h> 14 #include <plat/arm/common/smccc_def.h> 15 #include <plat/common/common_def.h> 16 17 /* PL011 UART related constants */ 18 #ifdef V2M_IOFPGA_UART0_CLK_IN_HZ 19 #undef V2M_IOFPGA_UART0_CLK_IN_HZ 20 #endif 21 22 #ifdef V2M_IOFPGA_UART1_CLK_IN_HZ 23 #undef V2M_IOFPGA_UART1_CLK_IN_HZ 24 #endif 25 26 #define V2M_IOFPGA_UART0_CLK_IN_HZ 32000000 27 #define V2M_IOFPGA_UART1_CLK_IN_HZ 32000000 28 29 /* Core/Cluster/Thread counts for Corstone700 */ 30 #define CORSTONE700_CLUSTER_COUNT U(1) 31 #define CORSTONE700_MAX_CPUS_PER_CLUSTER U(4) 32 #define CORSTONE700_MAX_PE_PER_CPU U(1) 33 34 #define PLAT_ARM_CLUSTER_COUNT CORSTONE700_CLUSTER_COUNT 35 36 #define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ 37 CORSTONE700_MAX_CPUS_PER_CLUSTER * \ 38 CORSTONE700_MAX_PE_PER_CPU) 39 40 41 /* UART related constants */ 42 #define PLAT_ARM_BOOT_UART_BASE 0x1a510000 43 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 44 #define PLAT_ARM_RUN_UART_BASE 0x1a520000 45 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 46 #define ARM_CONSOLE_BAUDRATE 115200 47 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 48 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 49 50 /* Memory related constants */ 51 #define ARM_DRAM1_BASE UL(0x80000000) 52 #define ARM_DRAM1_SIZE UL(0x80000000) 53 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 54 ARM_DRAM1_SIZE - 1) 55 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 56 #define ARM_NS_DRAM1_SIZE ARM_DRAM1_SIZE 57 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 58 ARM_NS_DRAM1_SIZE - 1) 59 #define ARM_TRUSTED_SRAM_BASE UL(0x02000000) 60 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 61 #define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ 62 #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */ 63 64 /* The remaining Trusted SRAM is used to load the BL images */ 65 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 66 ARM_SHARED_RAM_SIZE) 67 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 68 ARM_SHARED_RAM_SIZE) 69 70 #define ARM_NS_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE + UL(0x00100000) 71 #define ARM_NS_SHARED_RAM_SIZE 0x00300000 72 73 /* 74 * SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM (excluding 75 * the page reserved for fw_configs) to BL32 76 */ 77 #define BL32_BASE (ARM_BL_RAM_BASE + PAGE_SIZE) 78 #define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 79 80 /* 81 * Some data must be aligned on the biggest cache line size in the platform. 82 * This is known only to the platform as it might have a combination of 83 * integrated and external caches. 84 */ 85 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 86 #define ARM_CACHE_WRITEBACK_SHIFT 6 87 88 /* 89 * To enable FW_CONFIG to be loaded by BL1, define the corresponding base 90 * and limit. Leave enough space for BL2 meminfo. 91 */ 92 #define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) 93 #define ARM_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE / 2U)) 94 95 /* 96 * Boot parameters passed from BL2 to BL31/BL32 are stored here 97 */ 98 #define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT) 99 #define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \ 100 + (PAGE_SIZE / 2U)) 101 102 /* 103 * Define limit of firmware configuration memory: 104 * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory 105 */ 106 #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2)) 107 108 /* 109 * The max number of regions like RO(code), coherent and data required by 110 * different BL stages which need to be mapped in the MMU. 111 */ 112 #define ARM_BL_REGIONS 3 113 #define PLAT_ARM_MMAP_ENTRIES 8 114 #define MAX_XLAT_TABLES 5 115 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 116 ARM_BL_REGIONS) 117 118 /* GIC related constants */ 119 #define PLAT_ARM_GICD_BASE 0x1C010000 120 #define PLAT_ARM_GICC_BASE 0x1C02F000 121 122 /* MHUv2 Secure Channel receiver and sender */ 123 #define PLAT_SDK700_MHU0_SEND 0x1B800000 124 #define PLAT_SDK700_MHU0_RECV 0x1B810000 125 126 /* Timer/watchdog related constants */ 127 #define ARM_SYS_CNTCTL_BASE UL(0x1a200000) 128 #define ARM_SYS_CNTREAD_BASE UL(0x1a210000) 129 #define ARM_SYS_TIMCTL_BASE UL(0x1a220000) 130 131 #ifdef TARGET_PLATFORM_FVP 132 #define SYS_COUNTER_FREQ_IN_TICKS UL(50000000) /* 50MHz */ 133 #else 134 #define SYS_COUNTER_FREQ_IN_TICKS UL(32000000) /* 32MHz */ 135 #endif 136 137 #define CORSTONE700_IRQ_TZ_WDOG 32 138 #define CORSTONE700_IRQ_SEC_SYS_TIMER 34 139 140 #define PLAT_MAX_PWR_LVL 2 141 /* 142 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 143 * power levels have a 1:1 mapping with the MPIDR affinity levels. 144 */ 145 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 146 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 147 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 148 149 /* 150 * Macros for local power states in ARM platforms encoded by State-ID field 151 * within the power-state parameter. 152 */ 153 /* Local power state for power domains in Run state. */ 154 #define ARM_LOCAL_STATE_RUN U(0) 155 /* Local power state for retention. Valid only for CPU power domains */ 156 #define ARM_LOCAL_STATE_RET U(1) 157 /* Local power state for OFF/power-down. Valid for CPU and cluster 158 * power domains 159 */ 160 #define ARM_LOCAL_STATE_OFF U(2) 161 162 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 163 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 164 165 #define PLAT_ARM_NS_IMAGE_BASE (ARM_NS_SHARED_RAM_BASE) 166 167 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 168 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 169 170 /* 171 * This macro defines the deepest retention state possible. A higher state 172 * ID will represent an invalid or a power down state. 173 */ 174 #define PLAT_MAX_RET_STATE 1 175 176 /* 177 * This macro defines the deepest power down states possible. Any state ID 178 * higher than this is invalid. 179 */ 180 #define PLAT_MAX_OFF_STATE 2 181 182 #define PLATFORM_STACK_SIZE UL(0x440) 183 184 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 185 ARM_SHARED_RAM_BASE, \ 186 ARM_SHARED_RAM_SIZE, \ 187 MT_MEMORY | MT_RW | MT_SECURE) 188 189 #define ARM_MAP_NS_SHARED_RAM MAP_REGION_FLAT( \ 190 ARM_NS_SHARED_RAM_BASE, \ 191 ARM_NS_SHARED_RAM_SIZE, \ 192 MT_MEMORY | MT_RW | MT_NS) 193 194 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 195 ARM_NS_DRAM1_BASE, \ 196 ARM_NS_DRAM1_SIZE, \ 197 MT_MEMORY | MT_RW | MT_NS) 198 199 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 200 BL_CODE_BASE, \ 201 BL_CODE_END \ 202 - BL_CODE_BASE, \ 203 MT_CODE | MT_SECURE), \ 204 MAP_REGION_FLAT( \ 205 BL_RO_DATA_BASE, \ 206 BL_RO_DATA_END \ 207 - BL_RO_DATA_BASE, \ 208 MT_RO_DATA | MT_SECURE) 209 #if USE_COHERENT_MEM 210 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 211 BL_COHERENT_RAM_BASE, \ 212 BL_COHERENT_RAM_END \ 213 - BL_COHERENT_RAM_BASE, \ 214 MT_DEVICE | MT_RW | MT_SECURE) 215 #endif 216 217 /* 218 * Map the region for device tree configuration with read and write permissions 219 */ 220 #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \ 221 (ARM_FW_CONFIGS_LIMIT \ 222 - ARM_BL_RAM_BASE), \ 223 MT_MEMORY | MT_RW | MT_SECURE) 224 225 #define CORSTONE700_DEVICE_BASE (0x1A000000) 226 #define CORSTONE700_DEVICE_SIZE (0x26000000) 227 #define CORSTONE700_MAP_DEVICE MAP_REGION_FLAT( \ 228 CORSTONE700_DEVICE_BASE,\ 229 CORSTONE700_DEVICE_SIZE,\ 230 MT_DEVICE | MT_RW | MT_SECURE) 231 232 #define ARM_IRQ_SEC_PHY_TIMER 29 233 234 #define ARM_IRQ_SEC_SGI_0 8 235 #define ARM_IRQ_SEC_SGI_1 9 236 #define ARM_IRQ_SEC_SGI_2 10 237 #define ARM_IRQ_SEC_SGI_3 11 238 #define ARM_IRQ_SEC_SGI_4 12 239 #define ARM_IRQ_SEC_SGI_5 13 240 #define ARM_IRQ_SEC_SGI_6 14 241 #define ARM_IRQ_SEC_SGI_7 15 242 243 /* 244 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 245 * terminology. On a GICv2 system or mode, the lists will be merged and treated 246 * as Group 0 interrupts. 247 */ 248 #define ARM_G1S_IRQ_PROPS(grp) \ 249 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ 250 (grp), GIC_INTR_CFG_LEVEL), \ 251 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ 252 (grp), GIC_INTR_CFG_EDGE), \ 253 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ 254 (grp), GIC_INTR_CFG_EDGE), \ 255 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ 256 (grp), GIC_INTR_CFG_EDGE), \ 257 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ 258 (grp), GIC_INTR_CFG_EDGE), \ 259 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ 260 (grp), GIC_INTR_CFG_EDGE), \ 261 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ 262 (grp), GIC_INTR_CFG_EDGE) 263 264 #define ARM_G0_IRQ_PROPS(grp) \ 265 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 266 GIC_INTR_CFG_EDGE) 267 268 /* 269 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 270 * terminology. On a GICv2 system or mode, the lists will be merged and treated 271 * as Group 0 interrupts. 272 */ 273 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 274 ARM_G1S_IRQ_PROPS(grp), \ 275 INTR_PROP_DESC(CORSTONE700_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \ 276 (grp), GIC_INTR_CFG_LEVEL), \ 277 INTR_PROP_DESC(CORSTONE700_IRQ_SEC_SYS_TIMER, \ 278 GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL) 279 280 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 281 282 #endif /* PLATFORM_DEF_H */ 283