1 /* 2 * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SGI_SOC_CSS_DEF_V2_H 8 #define SGI_SOC_CSS_DEF_V2_H 9 10 #include <lib/utils_def.h> 11 #include <plat/common/common_def.h> 12 13 /* 14 * Definitions common to all ARM CSS SoCs 15 */ 16 17 /* Following covers ARM CSS SoC Peripherals */ 18 19 #define SOC_SYSTEM_PERIPH_BASE UL(0x0C000000) 20 #define SOC_SYSTEM_PERIPH_SIZE UL(0x02000000) 21 22 #define SOC_PLATFORM_PERIPH_BASE UL(0x0E000000) 23 #define SOC_PLATFORM_PERIPH_SIZE UL(0x02000000) 24 25 #define SOC_CSS_PCIE_CONTROL_BASE UL(0x0ef20000) 26 27 /* PL011 UART related constants */ 28 #define SOC_CSS_UART1_BASE UL(0x0ef80000) 29 #define SOC_CSS_UART0_BASE UL(0x0ef70000) 30 31 /* Memory controller */ 32 #define SOC_MEMCNTRL_BASE UL(0x10000000) 33 #define SOC_MEMCNTRL_SIZE UL(0x10000000) 34 35 #define SOC_CSS_UART0_CLK_IN_HZ UL(7372800) 36 #define SOC_CSS_UART1_CLK_IN_HZ UL(7372800) 37 38 /* SoC NIC-400 Global Programmers View (GPV) */ 39 #define SOC_CSS_NIC400_BASE UL(0x0ED00000) 40 41 #define SOC_CSS_NIC400_USB_EHCI U(0) 42 #define SOC_CSS_NIC400_TLX_MASTER U(1) 43 #define SOC_CSS_NIC400_USB_OHCI U(2) 44 #define SOC_CSS_NIC400_PL354_SMC U(3) 45 /* 46 * The apb4_bridge controls access to: 47 * - the PCIe configuration registers 48 * - the MMU units for USB, HDLCD and DMA 49 */ 50 #define SOC_CSS_NIC400_APB4_BRIDGE U(4) 51 52 /* Non-volatile counters */ 53 #define SOC_TRUSTED_NVCTR_BASE UL(0x0EE70000) 54 #define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0000) 55 #define TFW_NVCTR_SIZE U(4) 56 #define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0004) 57 #define NTFW_CTR_SIZE U(4) 58 59 /* Keys */ 60 #define SOC_KEYS_BASE UL(0x0EE80000) 61 #define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000) 62 #define TZ_PUB_KEY_HASH_SIZE U(32) 63 #define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020) 64 #define HU_KEY_SIZE U(16) 65 #define END_KEY_BASE (SOC_KEYS_BASE + 0x0044) 66 #define END_KEY_SIZE U(32) 67 68 #define SOC_PLATFORM_PERIPH_MAP_DEVICE MAP_REGION_FLAT( \ 69 SOC_PLATFORM_PERIPH_BASE, \ 70 SOC_PLATFORM_PERIPH_SIZE, \ 71 MT_DEVICE | MT_RW | MT_SECURE) 72 73 #if SPM_MM 74 /* 75 * Memory map definition for the platform peripheral memory region that is 76 * accessible from S-EL0 (with secure user mode access). 77 */ 78 #define SOC_PLATFORM_PERIPH_MAP_DEVICE_USER \ 79 MAP_REGION_FLAT( \ 80 SOC_PLATFORM_PERIPH_BASE, \ 81 SOC_PLATFORM_PERIPH_SIZE, \ 82 MT_DEVICE | MT_RW | MT_SECURE | MT_USER) 83 #endif 84 85 #define SOC_SYSTEM_PERIPH_MAP_DEVICE MAP_REGION_FLAT( \ 86 SOC_SYSTEM_PERIPH_BASE, \ 87 SOC_SYSTEM_PERIPH_SIZE, \ 88 MT_DEVICE | MT_RW | MT_SECURE) 89 90 #define SOC_MEMCNTRL_MAP_DEVICE MAP_REGION_FLAT( \ 91 SOC_MEMCNTRL_BASE, \ 92 SOC_MEMCNTRL_SIZE, \ 93 MT_DEVICE | MT_RW | MT_SECURE) 94 95 /* 96 * The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs. 97 */ 98 #define SOC_CSS_NIC400_BOOTSEC_BRIDGE U(5) 99 #define SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1 UL(1 << 12) 100 101 /* 102 * Required platform porting definitions common to all ARM CSS SoCs 103 */ 104 /* 2MB used for SCP DDR retraining */ 105 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x00200000) 106 107 /* V2M motherboard system registers & offsets */ 108 #define V2M_SYSREGS_BASE UL(0x0C010000) 109 #define V2M_SYS_LED U(0x8) 110 111 /* 112 * V2M sysled bit definitions. The values written to this 113 * register are defined in arch.h & runtime_svc.h. Only 114 * used by the primary cpu to diagnose any cold boot issues. 115 * 116 * SYS_LED[0] - Security state (S=0/NS=1) 117 * SYS_LED[2:1] - Exception Level (EL3-EL0) 118 * SYS_LED[7:3] - Exception Class (Sync/Async & origin) 119 * 120 */ 121 #define V2M_SYS_LED_SS_SHIFT U(0) 122 #define V2M_SYS_LED_EL_SHIFT U(1) 123 #define V2M_SYS_LED_EC_SHIFT U(3) 124 125 #define V2M_SYS_LED_SS_MASK U(0x01) 126 #define V2M_SYS_LED_EL_MASK U(0x03) 127 #define V2M_SYS_LED_EC_MASK U(0x1f) 128 129 /* NOR Flash */ 130 #define V2M_FLASH0_BASE UL(0x08000000) 131 #define V2M_FLASH0_SIZE UL(0x04000000) 132 #define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */ 133 134 /* 135 * The flash can be mapped either as read-only or read-write. 136 * 137 * If it is read-write then it should also be mapped as device memory because 138 * NOR flash programming involves sending a fixed, ordered sequence of commands. 139 * 140 * If it is read-only then it should also be mapped as: 141 * - Normal memory, because reading from NOR flash is transparent, it is like 142 * reading from RAM. 143 * - Non-executable by default. If some parts of the flash need to be executable 144 * then platform code is responsible for re-mapping the appropriate portion 145 * of it as executable. 146 */ 147 #define V2M_MAP_FLASH0_RW MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 148 V2M_FLASH0_SIZE, \ 149 MT_DEVICE | MT_RW | MT_SECURE) 150 151 #define V2M_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 152 V2M_FLASH0_SIZE, \ 153 MT_RO_DATA | MT_SECURE) 154 155 #define SGI_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 156 V2M_FLASH0_SIZE, \ 157 MT_DEVICE | MT_RO | MT_SECURE) 158 159 /* Platform ID address */ 160 #define BOARD_CSS_PLAT_ID_REG_ADDR UL(0x0EFE00E0) 161 162 /* Platform ID related accessors */ 163 #define BOARD_CSS_PLAT_ID_REG_ID_MASK U(0x0F) 164 #define BOARD_CSS_PLAT_ID_REG_ID_SHIFT U(0x00) 165 #define BOARD_CSS_PLAT_ID_REG_VERSION_MASK U(0xF00) 166 #define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT U(0x08) 167 #define BOARD_CSS_PLAT_TYPE_RTL U(0x00) 168 #define BOARD_CSS_PLAT_TYPE_FPGA U(0x01) 169 #define BOARD_CSS_PLAT_TYPE_EMULATOR U(0x02) 170 #define BOARD_CSS_PLAT_TYPE_FVP U(0x03) 171 172 #ifndef __ASSEMBLER__ 173 174 #include <lib/mmio.h> 175 176 #define BOARD_CSS_GET_PLAT_TYPE(addr) \ 177 ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \ 178 >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT) 179 180 #endif /* __ASSEMBLER__ */ 181 182 183 #define MAX_IO_DEVICES U(3) 184 #define MAX_IO_HANDLES U(4) 185 186 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 187 #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 188 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 189 190 #if ARM_GPT_SUPPORT 191 /* 192 * Offset of the FIP in the GPT image. BL1 component uses this option 193 * as it does not load the partition table to get the FIP base 194 * address. At sector 34 by default (i.e. after reserved sectors 0-33) 195 * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 196 */ 197 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 198 #endif /* ARM_GPT_SUPPORT */ 199 200 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 201 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 202 203 /* UART related constants */ 204 #define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE 205 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ 206 207 #define PLAT_ARM_RUN_UART_BASE SOC_CSS_UART1_BASE 208 #define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ 209 210 #define PLAT_ARM_SP_MIN_RUN_UART_BASE SOC_CSS_UART1_BASE 211 #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ 212 213 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 214 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 215 216 #endif /* SGI_SOC_CSS_DEF_V2_H */ 217