1 /*
2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <assert.h>
9 #include <cortex_a57.h>
10 #include <arch_helpers.h>
11 #include <common/debug.h>
12 #include <drivers/delay_timer.h>
13 #include <lib/mmio.h>
14 #include <lib/psci/psci.h>
15 #include <plat/common/platform.h>
16
17 #include <bpmp.h>
18 #include <flowctrl.h>
19 #include <lib/utils.h>
20 #include <memctrl.h>
21 #include <pmc.h>
22 #include <platform_def.h>
23 #include <security_engine.h>
24 #include <tegra_def.h>
25 #include <tegra_private.h>
26 #include <tegra_platform.h>
27
28 /*
29 * Register used to clear CPU reset signals. Each CPU has two reset
30 * signals: CPU reset (3:0) and Core reset (19:16).
31 */
32 #define CPU_CMPLX_RESET_CLR 0x454
33 #define CPU_CORE_RESET_MASK 0x10001
34
35 /* Clock and Reset controller registers for system clock's settings */
36 #define SCLK_RATE 0x30
37 #define SCLK_BURST_POLICY 0x28
38 #define SCLK_BURST_POLICY_DEFAULT 0x10000000
39
40 static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER];
41 static bool tegra_bpmp_available = true;
42
tegra_soc_validate_power_state(unsigned int power_state,psci_power_state_t * req_state)43 int32_t tegra_soc_validate_power_state(unsigned int power_state,
44 psci_power_state_t *req_state)
45 {
46 int state_id = psci_get_pstate_id(power_state);
47 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
48
49 /* Sanity check the requested state id */
50 switch (state_id) {
51 case PSTATE_ID_CORE_POWERDN:
52 /*
53 * Core powerdown request only for afflvl 0
54 */
55 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff;
56
57 break;
58
59 case PSTATE_ID_CLUSTER_IDLE:
60
61 /*
62 * Cluster idle request for afflvl 0
63 */
64 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PSTATE_ID_CORE_POWERDN;
65 req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id;
66 break;
67
68 case PSTATE_ID_SOC_POWERDN:
69
70 /*
71 * sc7entry-fw must be present in the system when the bpmp
72 * firmware is not present, for a successful System Suspend
73 * entry.
74 */
75 if (!tegra_bpmp_init() && !plat_params->sc7entry_fw_base)
76 return PSCI_E_NOT_SUPPORTED;
77
78 /*
79 * System powerdown request only for afflvl 2
80 */
81 for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
82 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
83
84 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] =
85 PLAT_SYS_SUSPEND_STATE_ID;
86
87 break;
88
89 default:
90 ERROR("%s: unsupported state id (%d)\n", __func__, state_id);
91 return PSCI_E_INVALID_PARAMS;
92 }
93
94 return PSCI_E_SUCCESS;
95 }
96
97 /*******************************************************************************
98 * Platform handler to calculate the proper target power level at the
99 * specified affinity level.
100 ******************************************************************************/
tegra_soc_get_target_pwr_state(unsigned int lvl,const plat_local_state_t * states,unsigned int ncpu)101 plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
102 const plat_local_state_t *states,
103 unsigned int ncpu)
104 {
105 plat_local_state_t target = PSCI_LOCAL_STATE_RUN;
106 int cpu = plat_my_core_pos();
107 int core_pos = read_mpidr() & MPIDR_CPU_MASK;
108 uint32_t bpmp_reply, data[3], val;
109 int ret;
110
111 /* get the power state at this level */
112 if (lvl == MPIDR_AFFLVL1)
113 target = *(states + core_pos);
114 if (lvl == MPIDR_AFFLVL2)
115 target = *(states + cpu);
116
117 if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_IDLE)) {
118
119 /* initialize the bpmp interface */
120 ret = tegra_bpmp_init();
121 if (ret != 0U) {
122
123 /*
124 * flag to indicate that BPMP firmware is not
125 * available and the CPU has to handle entry/exit
126 * for all power states
127 */
128 tegra_bpmp_available = false;
129
130 /* Cluster idle not allowed */
131 target = PSCI_LOCAL_STATE_RUN;
132
133 /*******************************************
134 * BPMP is not present, so handle CC6 entry
135 * from the CPU
136 ******************************************/
137
138 /* check if cluster idle state has been enabled */
139 val = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL);
140 if (val == ENABLE_CLOSED_LOOP) {
141 /*
142 * Acquire the cluster idle lock to stop
143 * other CPUs from powering up.
144 */
145 tegra_fc_ccplex_pgexit_lock();
146
147 /* Cluster idle only from the last standing CPU */
148 if (tegra_pmc_is_last_on_cpu() && tegra_fc_is_ccx_allowed()) {
149 /* Cluster idle allowed */
150 target = PSTATE_ID_CLUSTER_IDLE;
151 } else {
152 /* release cluster idle lock */
153 tegra_fc_ccplex_pgexit_unlock();
154 }
155 }
156 } else {
157
158 /* Cluster power-down */
159 data[0] = (uint32_t)cpu;
160 data[1] = TEGRA_PM_CC6;
161 data[2] = TEGRA_PM_SC1;
162 ret = tegra_bpmp_send_receive_atomic(MRQ_DO_IDLE,
163 (void *)&data, (int)sizeof(data),
164 (void *)&bpmp_reply,
165 (int)sizeof(bpmp_reply));
166
167 /* check if cluster power down is allowed */
168 if ((ret != 0L) || (bpmp_reply != BPMP_CCx_ALLOWED)) {
169
170 /* Cluster power down not allowed */
171 target = PSCI_LOCAL_STATE_RUN;
172 }
173 }
174
175 } else if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) &&
176 (target == PSTATE_ID_SOC_POWERDN)) {
177
178 /* System Suspend */
179 target = PSTATE_ID_SOC_POWERDN;
180
181 } else {
182 ; /* do nothing */
183 }
184
185 return target;
186 }
187
tegra_soc_cpu_standby(plat_local_state_t cpu_state)188 int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state)
189 {
190 (void)cpu_state;
191 return PSCI_E_SUCCESS;
192 }
193
tegra_soc_pwr_domain_suspend(const psci_power_state_t * target_state)194 int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
195 {
196 u_register_t mpidr = read_mpidr();
197 const plat_local_state_t *pwr_domain_state =
198 target_state->pwr_domain_state;
199 unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2];
200 unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1];
201 unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0];
202 uint32_t cfg;
203 int ret = PSCI_E_SUCCESS;
204 uint32_t val;
205
206 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
207
208 assert((stateid_afflvl0 == PLAT_MAX_OFF_STATE) ||
209 (stateid_afflvl0 == PSTATE_ID_SOC_POWERDN));
210 assert((stateid_afflvl1 == PLAT_MAX_OFF_STATE) ||
211 (stateid_afflvl1 == PSTATE_ID_SOC_POWERDN));
212
213 /* Suspend se/se2 and pka1 for T210 B01 and se for T210 */
214 if (tegra_se_suspend() != 0) {
215 ret = PSCI_E_INTERN_FAIL;
216 }
217
218 } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_IDLE) {
219
220 assert(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN);
221
222 if (!tegra_bpmp_available) {
223
224 /*
225 * When disabled, DFLL loses its state. Enable
226 * open loop state for the DFLL as we dont want
227 * garbage values being written to the pmic
228 * when we enter cluster idle state.
229 */
230 mmio_write_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL,
231 ENABLE_OPEN_LOOP);
232
233 /* Find if the platform uses OVR2/MAX77621 PMIC */
234 cfg = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_OUTPUT_CFG);
235 if (cfg & DFLL_OUTPUT_CFG_CLK_EN_BIT) {
236 /* OVR2 */
237
238 /* PWM tristate */
239 val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM);
240 val |= PINMUX_PWM_TRISTATE;
241 mmio_write_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM, val);
242
243 /*
244 * SCRATCH201[1] is being used to identify CPU
245 * PMIC in warmboot code.
246 * 0 : OVR2
247 * 1 : MAX77621
248 */
249 tegra_pmc_write_32(PMC_SCRATCH201, 0x0);
250 } else {
251 /* MAX77621 */
252 tegra_pmc_write_32(PMC_SCRATCH201, 0x2);
253 }
254 }
255
256 /* Prepare for cluster idle */
257 tegra_fc_cluster_idle(mpidr);
258
259 } else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) {
260
261 /* Prepare for cpu powerdn */
262 tegra_fc_cpu_powerdn(mpidr);
263
264 } else {
265 ERROR("%s: Unknown state id (%d, %d, %d)\n", __func__,
266 stateid_afflvl2, stateid_afflvl1, stateid_afflvl0);
267 ret = PSCI_E_NOT_SUPPORTED;
268 }
269
270 return ret;
271 }
272
tegra_reset_all_dma_masters(void)273 static void tegra_reset_all_dma_masters(void)
274 {
275 uint32_t val, mask;
276
277 /*
278 * Reset all possible DMA masters in the system.
279 */
280 val = GPU_RESET_BIT;
281 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET, val);
282
283 val = NVENC_RESET_BIT | TSECB_RESET_BIT | APE_RESET_BIT |
284 NVJPG_RESET_BIT | NVDEC_RESET_BIT;
285 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_Y, val);
286
287 val = HOST1X_RESET_BIT | ISP_RESET_BIT | USBD_RESET_BIT |
288 VI_RESET_BIT | SDMMC4_RESET_BIT | SDMMC1_RESET_BIT |
289 SDMMC2_RESET_BIT;
290 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_L, val);
291
292 val = USB2_RESET_BIT | APBDMA_RESET_BIT | AHBDMA_RESET_BIT;
293 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_H, val);
294
295 val = XUSB_DEV_RESET_BIT | XUSB_HOST_RESET_BIT | TSEC_RESET_BIT |
296 PCIE_RESET_BIT | SDMMC3_RESET_BIT;
297 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_U, val);
298
299 val = SE_RESET_BIT | HDA_RESET_BIT | SATA_RESET_BIT;
300 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_V, val);
301
302 /*
303 * If any of the DMA masters are still alive, assume
304 * that the system has been compromised and reboot.
305 */
306 val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET);
307 mask = GPU_RESET_BIT;
308 if ((val & mask) != mask)
309 tegra_pmc_system_reset();
310
311 mask = NVENC_RESET_BIT | TSECB_RESET_BIT | APE_RESET_BIT |
312 NVJPG_RESET_BIT | NVDEC_RESET_BIT;
313 val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_Y);
314 if ((val & mask) != mask)
315 tegra_pmc_system_reset();
316
317 mask = HOST1X_RESET_BIT | ISP_RESET_BIT | USBD_RESET_BIT |
318 VI_RESET_BIT | SDMMC4_RESET_BIT | SDMMC1_RESET_BIT |
319 SDMMC2_RESET_BIT;
320 val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_L);
321 if ((val & mask) != mask)
322 tegra_pmc_system_reset();
323
324 mask = USB2_RESET_BIT | APBDMA_RESET_BIT | AHBDMA_RESET_BIT;
325 val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_H);
326 if ((val & mask) != mask)
327 tegra_pmc_system_reset();
328
329 mask = XUSB_DEV_RESET_BIT | XUSB_HOST_RESET_BIT | TSEC_RESET_BIT |
330 PCIE_RESET_BIT | SDMMC3_RESET_BIT;
331 val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_U);
332 if ((val & mask) != mask)
333 tegra_pmc_system_reset();
334
335 val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_V);
336 mask = SE_RESET_BIT | HDA_RESET_BIT | SATA_RESET_BIT;
337 if ((val & mask) != mask)
338 tegra_pmc_system_reset();
339 }
340
tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t * target_state)341 int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
342 {
343 u_register_t mpidr = read_mpidr();
344 const plat_local_state_t *pwr_domain_state =
345 target_state->pwr_domain_state;
346 unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL];
347 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
348 uint32_t val;
349
350 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
351
352 if (tegra_chipid_is_t210_b01()) {
353 /* Save tzram contents */
354 tegra_se_save_tzram();
355 }
356
357 /* de-init the interface */
358 tegra_bpmp_suspend();
359
360 /*
361 * The CPU needs to load the System suspend entry firmware
362 * if nothing is running on the BPMP.
363 */
364 if (!tegra_bpmp_available) {
365
366 /*
367 * BPMP firmware is not running on the co-processor, so
368 * we need to explicitly load the firmware to enable
369 * entry/exit to/from System Suspend and set the BPMP
370 * on its way.
371 */
372
373 /* Power off BPMP before we proceed */
374 tegra_fc_bpmp_off();
375
376 /* bond out IRAM banks B, C and D */
377 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_BOND_OUT_U,
378 IRAM_B_LOCK_BIT | IRAM_C_LOCK_BIT |
379 IRAM_D_LOCK_BIT);
380
381 /* bond out APB/AHB DMAs */
382 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_BOND_OUT_H,
383 APB_DMA_LOCK_BIT | AHB_DMA_LOCK_BIT);
384
385 /* Power off BPMP before we proceed */
386 tegra_fc_bpmp_off();
387
388 /*
389 * Reset all the hardware blocks that can act as DMA
390 * masters on the bus.
391 */
392 tegra_reset_all_dma_masters();
393
394 /*
395 * Mark PMC as accessible to the non-secure world
396 * to allow the COP to execute System Suspend
397 * sequence
398 */
399 val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
400 val &= ~PMC_SECURITY_EN_BIT;
401 mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
402
403 /* clean up IRAM of any cruft */
404 zeromem((void *)(uintptr_t)TEGRA_IRAM_BASE,
405 TEGRA_IRAM_A_SIZE);
406
407 /* Copy the firmware to BPMP's internal RAM */
408 (void)memcpy((void *)(uintptr_t)TEGRA_IRAM_BASE,
409 (const void *)(plat_params->sc7entry_fw_base + SC7ENTRY_FW_HEADER_SIZE_BYTES),
410 plat_params->sc7entry_fw_size - SC7ENTRY_FW_HEADER_SIZE_BYTES);
411
412 /* Power on the BPMP and execute from IRAM base */
413 tegra_fc_bpmp_on(TEGRA_IRAM_BASE);
414
415 /* Wait until BPMP powers up */
416 do {
417 val = mmio_read_32(TEGRA_RES_SEMA_BASE + STA_OFFSET);
418 } while (val != SIGN_OF_LIFE);
419 }
420
421 /* enter system suspend */
422 tegra_fc_soc_powerdn(mpidr);
423 }
424
425 return PSCI_E_SUCCESS;
426 }
427
tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t * target_state)428 int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state)
429 {
430 return PSCI_E_NOT_SUPPORTED;
431 }
432
tegra_soc_pwr_domain_on_finish(const psci_power_state_t * target_state)433 int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
434 {
435 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
436 uint32_t cfg;
437 uint32_t val, entrypoint = 0;
438 uint64_t offset;
439
440 /* platform parameter passed by the previous bootloader */
441 if (plat_params->l2_ecc_parity_prot_dis != 1) {
442 /* Enable ECC Parity Protection for Cortex-A57 CPUs */
443 val = read_l2ctlr_el1();
444 val |= (uint64_t)CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT;
445 write_l2ctlr_el1(val);
446 }
447
448 /*
449 * Check if we are exiting from SOC_POWERDN.
450 */
451 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
452 PLAT_SYS_SUSPEND_STATE_ID) {
453
454 /*
455 * Security engine resume
456 */
457 if (tegra_chipid_is_t210_b01()) {
458 tegra_se_resume();
459 }
460
461 /*
462 * Lock scratch registers which hold the CPU vectors
463 */
464 tegra_pmc_lock_cpu_vectors();
465
466 /*
467 * Enable WRAP to INCR burst type conversions for
468 * incoming requests on the AXI slave ports.
469 */
470 val = mmio_read_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG);
471 val &= ~ENABLE_UNSUP_TX_ERRORS;
472 val |= ENABLE_WRAP_TO_INCR_BURSTS;
473 mmio_write_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG, val);
474
475 /*
476 * Restore Boot and Power Management Processor (BPMP) reset
477 * address and reset it, if it is supported by the platform.
478 */
479 if (!tegra_bpmp_available) {
480 tegra_fc_bpmp_off();
481 } else {
482 entrypoint = tegra_pmc_read_32(PMC_SCRATCH39);
483 tegra_fc_bpmp_on(entrypoint);
484
485 /* initialise the interface */
486 tegra_bpmp_resume();
487 }
488
489 if (plat_params->sc7entry_fw_base != 0U) {
490 /* sc7entry-fw is part of TZDRAM area */
491 offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base;
492 tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base,
493 plat_params->tzdram_size + offset);
494 }
495
496 if (!tegra_chipid_is_t210_b01()) {
497 /* restrict PMC access to secure world */
498 val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
499 val |= PMC_SECURITY_EN_BIT;
500 mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
501 }
502 }
503
504 /*
505 * Check if we are exiting cluster idle state
506 */
507 if (target_state->pwr_domain_state[MPIDR_AFFLVL1] ==
508 PSTATE_ID_CLUSTER_IDLE) {
509
510 if (!tegra_bpmp_available) {
511
512 /* PWM un-tristate */
513 cfg = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_OUTPUT_CFG);
514 if (cfg & DFLL_OUTPUT_CFG_CLK_EN_BIT) {
515 val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM);
516 val &= ~PINMUX_PWM_TRISTATE;
517 mmio_write_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM, val);
518
519 /* make sure the setting took effect */
520 val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM);
521 assert((val & PINMUX_PWM_TRISTATE) == 0U);
522 }
523
524 /*
525 * Restore operation mode for the DFLL ring
526 * oscillator
527 */
528 mmio_write_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL,
529 ENABLE_CLOSED_LOOP);
530
531 /* release cluster idle lock */
532 tegra_fc_ccplex_pgexit_unlock();
533 }
534 }
535
536 /*
537 * Mark this CPU as ON in the cpu_powergate_mask[],
538 * so that we use Flow Controller for all subsequent
539 * power ups.
540 */
541 cpu_powergate_mask[plat_my_core_pos()] = 1;
542
543 /*
544 * T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's
545 * used for power management and boot purposes. Inform the BPMP that
546 * we have completed the cluster power up.
547 */
548 tegra_fc_lock_active_cluster();
549
550 /*
551 * Resume PMC hardware block for Tegra210 platforms
552 */
553 if (!tegra_chipid_is_t210_b01()) {
554 tegra_pmc_resume();
555 }
556
557 return PSCI_E_SUCCESS;
558 }
559
tegra_soc_pwr_domain_on(u_register_t mpidr)560 int tegra_soc_pwr_domain_on(u_register_t mpidr)
561 {
562 int cpu = mpidr & MPIDR_CPU_MASK;
563 uint32_t mask = CPU_CORE_RESET_MASK << cpu;
564
565 /* Deassert CPU reset signals */
566 mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask);
567
568 /* Turn on CPU using flow controller or PMC */
569 if (cpu_powergate_mask[cpu] == 0) {
570 tegra_pmc_cpu_on(cpu);
571 } else {
572 tegra_fc_cpu_on(cpu);
573 }
574
575 return PSCI_E_SUCCESS;
576 }
577
tegra_soc_pwr_domain_off(const psci_power_state_t * target_state)578 int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
579 {
580 tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK);
581 return PSCI_E_SUCCESS;
582 }
583
tegra_soc_prepare_system_reset(void)584 int tegra_soc_prepare_system_reset(void)
585 {
586 /*
587 * Set System Clock (SCLK) to POR default so that the clock source
588 * for the PMC APB clock would not be changed due to system reset.
589 */
590 mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY,
591 SCLK_BURST_POLICY_DEFAULT);
592 mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0);
593
594 /* Wait 1 ms to make sure clock source/device logic is stabilized. */
595 mdelay(1);
596
597 /*
598 * Program the PMC in order to restart the system.
599 */
600 tegra_pmc_system_reset();
601
602 return PSCI_E_SUCCESS;
603 }
604
tegra_soc_prepare_system_off(void)605 __dead2 void tegra_soc_prepare_system_off(void)
606 {
607 ERROR("Tegra System Off: operation not handled.\n");
608 panic();
609 }
610