1 /*
2  * Copyright 2018-2020 NXP
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 #ifndef PLAT_COMMON_H
9 #define PLAT_COMMON_H
10 
11 #include <stdbool.h>
12 
13 #include <lib/el3_runtime/cpu_data.h>
14 #include <platform_def.h>
15 
16 #ifdef IMAGE_BL31
17 
18 #define BL31_END (uintptr_t)(&__BL31_END__)
19 
20 /*******************************************************************************
21  * This structure represents the superset of information that can be passed to
22  * BL31 e.g. while passing control to it from BL2. The BL32 parameters will be
23  * populated only if BL2 detects its presence. A pointer to a structure of this
24  * type should be passed in X0 to BL31's cold boot entrypoint.
25  *
26  * Use of this structure and the X0 parameter is not mandatory: the BL31
27  * platform code can use other mechanisms to provide the necessary information
28  * about BL32 and BL33 to the common and SPD code.
29  *
30  * BL31 image information is mandatory if this structure is used. If either of
31  * the optional BL32 and BL33 image information is not provided, this is
32  * indicated by the respective image_info pointers being zero.
33  ******************************************************************************/
34 typedef struct bl31_params {
35 	param_header_t h;
36 	image_info_t *bl31_image_info;
37 	entry_point_info_t *bl32_ep_info;
38 	image_info_t *bl32_image_info;
39 	entry_point_info_t *bl33_ep_info;
40 	image_info_t *bl33_image_info;
41 } bl31_params_t;
42 
43 /* BL3 utility functions */
44 void ls_bl31_early_platform_setup(void *from_bl2,
45 				void *plat_params_from_bl2);
46 /* LS Helper functions	*/
47 unsigned int plat_my_core_mask(void);
48 unsigned int plat_core_mask(u_register_t mpidr);
49 unsigned int plat_core_pos(u_register_t mpidr);
50 //unsigned int plat_my_core_pos(void);
51 
52 /* BL31 Data API(s) */
53 void _init_global_data(void);
54 void _initialize_psci(void);
55 uint32_t _getCoreState(u_register_t core_mask);
56 void _setCoreState(u_register_t core_mask, u_register_t core_state);
57 
58 /* SoC defined structure and API(s) */
59 void soc_runtime_setup(void);
60 void soc_init(void);
61 void soc_platform_setup(void);
62 void soc_early_platform_setup2(void);
63 #endif /* IMAGE_BL31 */
64 
65 #ifdef IMAGE_BL2
66 void soc_early_init(void);
67 void soc_mem_access(void);
68 void soc_preload_setup(void);
69 void soc_bl2_prepare_exit(void);
70 
71 /* IO storage utility functions */
72 int plat_io_setup(void);
73 int open_backend(const uintptr_t spec);
74 
75 void ls_bl2_plat_arch_setup(void);
76 void ls_bl2_el3_plat_arch_setup(void);
77 
78 enum boot_device {
79 	BOOT_DEVICE_IFC_NOR,
80 	BOOT_DEVICE_IFC_NAND,
81 	BOOT_DEVICE_QSPI,
82 	BOOT_DEVICE_EMMC,
83 	BOOT_DEVICE_SDHC2_EMMC,
84 	BOOT_DEVICE_FLEXSPI_NOR,
85 	BOOT_DEVICE_FLEXSPI_NAND,
86 	BOOT_DEVICE_NONE
87 };
88 
89 enum boot_device get_boot_dev(void);
90 
91 /* DDR Related functions */
92 #if DDR_INIT
93 #ifdef NXP_WARM_BOOT
94 long long init_ddr(uint32_t wrm_bt_flg);
95 #else
96 long long init_ddr(void);
97 #endif
98 #endif
99 
100 /* Board specific weak functions */
101 bool board_enable_povdd(void);
102 bool board_disable_povdd(void);
103 
104 void mmap_add_ddr_region_dynamically(void);
105 #endif /* IMAGE_BL2 */
106 
107 typedef struct {
108 	uint64_t addr;
109 	uint64_t size;
110 } region_info_t;
111 
112 typedef struct {
113 	uint64_t num_dram_regions;
114 	uint64_t total_dram_size;
115 	region_info_t region[NUM_DRAM_REGIONS];
116 } dram_regions_info_t;
117 
118 dram_regions_info_t *get_dram_regions_info(void);
119 
120 void ls_setup_page_tables(uintptr_t total_base,
121 			size_t total_size,
122 			uintptr_t code_start,
123 			uintptr_t code_limit,
124 			uintptr_t rodata_start,
125 			uintptr_t rodata_limit
126 #if USE_COHERENT_MEM
127 			, uintptr_t coh_start,
128 			uintptr_t coh_limit
129 #endif
130 );
131 
132 
133 /* Structure to define SoC personality */
134 struct soc_type {
135 	char name[10];
136 	uint32_t personality;
137 	uint32_t num_clusters;
138 	uint32_t cores_per_cluster;
139 };
140 
141 #define SOC_ENTRY(n, v, ncl, nc) {	\
142 		.name = #n,		\
143 		.personality = SVR_##v,	\
144 		.num_clusters = (ncl),	\
145 		.cores_per_cluster = (nc)}
146 
147 #endif /* PLAT_COMMON_H */
148