1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <lib/utils_def.h> 13 #include <plat/common/common_def.h> 14 15 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 16 #define QEMU_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 17 18 #define PLATFORM_STACK_SIZE 0x1000 19 20 #if ARM_ARCH_MAJOR == 7 21 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 22 #define PLATFORM_CLUSTER_COUNT U(1) 23 #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 24 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 25 #else 26 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 27 /* 28 * Define the number of cores per cluster used in calculating core position. 29 * The cluster number is shifted by this value and added to the core ID, 30 * so its value represents log2(cores/cluster). 31 * Default is 2**(2) = 4 cores per cluster. 32 */ 33 #define PLATFORM_CPU_PER_CLUSTER_SHIFT U(2) 34 35 #define PLATFORM_CLUSTER_COUNT U(2) 36 #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 37 #define PLATFORM_CLUSTER1_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 38 #endif 39 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ 40 PLATFORM_CLUSTER1_CORE_COUNT) 41 42 #define QEMU_PRIMARY_CPU U(0) 43 44 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ 45 PLATFORM_CORE_COUNT) 46 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 47 48 #define PLAT_MAX_RET_STATE U(1) 49 #define PLAT_MAX_OFF_STATE U(2) 50 51 /* Local power state for power domains in Run state. */ 52 #define PLAT_LOCAL_STATE_RUN U(0) 53 /* Local power state for retention. Valid only for CPU power domains */ 54 #define PLAT_LOCAL_STATE_RET U(1) 55 /* 56 * Local power state for OFF/power-down. Valid for CPU and cluster power 57 * domains. 58 */ 59 #define PLAT_LOCAL_STATE_OFF 2 60 61 /* 62 * Macros used to parse state information from State-ID if it is using the 63 * recommended encoding for State-ID. 64 */ 65 #define PLAT_LOCAL_PSTATE_WIDTH 4 66 #define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1) 67 68 /* 69 * Some data must be aligned on the biggest cache line size in the platform. 70 * This is known only to the platform as it might have a combination of 71 * integrated and external caches. 72 */ 73 #define CACHE_WRITEBACK_SHIFT 6 74 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 75 76 /* 77 * Partition memory into secure ROM, non-secure DRAM, secure "SRAM", 78 * and secure DRAM. 79 */ 80 #define SEC_ROM_BASE 0x00000000 81 #define SEC_ROM_SIZE 0x00020000 82 83 #define NS_DRAM0_BASE 0x40000000 84 #define NS_DRAM0_SIZE 0x3de00000 85 86 #define SEC_SRAM_BASE 0x0e000000 87 #define SEC_SRAM_SIZE 0x00060000 88 89 #define SEC_DRAM_BASE 0x0e100000 90 #define SEC_DRAM_SIZE 0x00f00000 91 92 #define SECURE_GPIO_BASE 0x090b0000 93 #define SECURE_GPIO_SIZE 0x00001000 94 #define SECURE_GPIO_POWEROFF 0 95 #define SECURE_GPIO_RESET 1 96 97 /* Load pageable part of OP-TEE 2MB above secure DRAM base */ 98 #define QEMU_OPTEE_PAGEABLE_LOAD_BASE (SEC_DRAM_BASE + 0x00200000) 99 #define QEMU_OPTEE_PAGEABLE_LOAD_SIZE 0x00400000 100 101 /* 102 * ARM-TF lives in SRAM, partition it here 103 */ 104 105 #define SHARED_RAM_BASE SEC_SRAM_BASE 106 #define SHARED_RAM_SIZE 0x00001000 107 108 #define PLAT_QEMU_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE 109 #define PLAT_QEMU_TRUSTED_MAILBOX_SIZE (8 + PLAT_QEMU_HOLD_SIZE) 110 #define PLAT_QEMU_HOLD_BASE (PLAT_QEMU_TRUSTED_MAILBOX_BASE + 8) 111 #define PLAT_QEMU_HOLD_SIZE (PLATFORM_CORE_COUNT * \ 112 PLAT_QEMU_HOLD_ENTRY_SIZE) 113 #define PLAT_QEMU_HOLD_ENTRY_SHIFT 3 114 #define PLAT_QEMU_HOLD_ENTRY_SIZE (1 << PLAT_QEMU_HOLD_ENTRY_SHIFT) 115 #define PLAT_QEMU_HOLD_STATE_WAIT 0 116 #define PLAT_QEMU_HOLD_STATE_GO 1 117 118 #define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE) 119 #define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) 120 121 /* 122 * BL1 specific defines. 123 * 124 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 125 * addresses. 126 * Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using 127 * the current BL1 RW debug size plus a little space for growth. 128 */ 129 #define BL1_RO_BASE SEC_ROM_BASE 130 #define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE) 131 #define BL1_RW_BASE (BL1_RW_LIMIT - 0x12000) 132 #define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE) 133 134 /* 135 * BL2 specific defines. 136 * 137 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 138 * size plus a little space for growth. 139 */ 140 #define BL2_BASE (BL31_BASE - 0x25000) 141 #define BL2_LIMIT BL31_BASE 142 143 /* 144 * BL3-1 specific defines. 145 * 146 * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the 147 * current BL3-1 debug size plus a little space for growth. 148 */ 149 #define BL31_BASE (BL31_LIMIT - 0x20000) 150 #define BL31_LIMIT (BL_RAM_BASE + BL_RAM_SIZE) 151 #define BL31_PROGBITS_LIMIT BL1_RW_BASE 152 153 154 /* 155 * BL3-2 specific defines. 156 * 157 * BL3-2 can execute from Secure SRAM, or Secure DRAM. 158 */ 159 #define BL32_SRAM_BASE BL_RAM_BASE 160 #define BL32_SRAM_LIMIT BL31_BASE 161 #define BL32_DRAM_BASE SEC_DRAM_BASE 162 #define BL32_DRAM_LIMIT (SEC_DRAM_BASE + SEC_DRAM_SIZE) 163 164 #define SEC_SRAM_ID 0 165 #define SEC_DRAM_ID 1 166 167 #if BL32_RAM_LOCATION_ID == SEC_SRAM_ID 168 # define BL32_MEM_BASE BL_RAM_BASE 169 # define BL32_MEM_SIZE BL_RAM_SIZE 170 # define BL32_BASE BL32_SRAM_BASE 171 # define BL32_LIMIT BL32_SRAM_LIMIT 172 #elif BL32_RAM_LOCATION_ID == SEC_DRAM_ID 173 # define BL32_MEM_BASE SEC_DRAM_BASE 174 # define BL32_MEM_SIZE SEC_DRAM_SIZE 175 # define BL32_BASE BL32_DRAM_BASE 176 # define BL32_LIMIT BL32_DRAM_LIMIT 177 #else 178 # error "Unsupported BL32_RAM_LOCATION_ID value" 179 #endif 180 181 #define NS_IMAGE_OFFSET (NS_DRAM0_BASE + 0x20000000) 182 #define NS_IMAGE_MAX_SIZE (NS_DRAM0_SIZE - 0x20000000) 183 184 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 185 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 186 #define MAX_MMAP_REGIONS 11 187 #define MAX_XLAT_TABLES 6 188 #define MAX_IO_DEVICES 4 189 #define MAX_IO_HANDLES 4 190 191 /* 192 * PL011 related constants 193 */ 194 #define UART0_BASE 0x09000000 195 #define UART1_BASE 0x09040000 196 #define UART0_CLK_IN_HZ 1 197 #define UART1_CLK_IN_HZ 1 198 199 #define PLAT_QEMU_BOOT_UART_BASE UART0_BASE 200 #define PLAT_QEMU_BOOT_UART_CLK_IN_HZ UART0_CLK_IN_HZ 201 202 #define PLAT_QEMU_CRASH_UART_BASE UART1_BASE 203 #define PLAT_QEMU_CRASH_UART_CLK_IN_HZ UART1_CLK_IN_HZ 204 205 #define PLAT_QEMU_CONSOLE_BAUDRATE 115200 206 207 #define QEMU_FLASH0_BASE 0x00000000 208 #define QEMU_FLASH0_SIZE 0x04000000 209 #define QEMU_FLASH1_BASE 0x04000000 210 #define QEMU_FLASH1_SIZE 0x04000000 211 212 #define PLAT_QEMU_FIP_BASE 0x00040000 213 #define PLAT_QEMU_FIP_MAX_SIZE 0x00400000 214 215 #define DEVICE0_BASE 0x08000000 216 #define DEVICE0_SIZE 0x01000000 217 #define DEVICE1_BASE 0x09000000 218 #define DEVICE1_SIZE 0x00c00000 219 220 /* 221 * GIC related constants 222 */ 223 224 #define GICD_BASE 0x8000000 225 #define GICC_BASE 0x8010000 226 #define GICR_BASE 0x80A0000 227 228 229 #define QEMU_IRQ_SEC_SGI_0 8 230 #define QEMU_IRQ_SEC_SGI_1 9 231 #define QEMU_IRQ_SEC_SGI_2 10 232 #define QEMU_IRQ_SEC_SGI_3 11 233 #define QEMU_IRQ_SEC_SGI_4 12 234 #define QEMU_IRQ_SEC_SGI_5 13 235 #define QEMU_IRQ_SEC_SGI_6 14 236 #define QEMU_IRQ_SEC_SGI_7 15 237 238 /****************************************************************************** 239 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 240 * interrupts. 241 *****************************************************************************/ 242 #define PLATFORM_G1S_PROPS(grp) \ 243 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \ 244 grp, GIC_INTR_CFG_EDGE), \ 245 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ 246 grp, GIC_INTR_CFG_EDGE), \ 247 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ 248 grp, GIC_INTR_CFG_EDGE), \ 249 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ 250 grp, GIC_INTR_CFG_EDGE), \ 251 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ 252 grp, GIC_INTR_CFG_EDGE), \ 253 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ 254 grp, GIC_INTR_CFG_EDGE), \ 255 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ 256 grp, GIC_INTR_CFG_EDGE), \ 257 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ 258 grp, GIC_INTR_CFG_EDGE) 259 260 #define PLATFORM_G0_PROPS(grp) 261 262 /* 263 * DT related constants 264 */ 265 #define PLAT_QEMU_DT_BASE NS_DRAM0_BASE 266 #define PLAT_QEMU_DT_MAX_SIZE 0x100000 267 268 /* 269 * System counter 270 */ 271 #define SYS_COUNTER_FREQ_IN_TICKS ((1000 * 1000 * 1000) / 16) 272 273 #endif /* PLATFORM_DEF_H */ 274