1 /*
2 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <common/debug.h>
10 #include <drivers/arm/cci.h>
11 #include <drivers/arm/ccn.h>
12 #include <drivers/arm/gicv2.h>
13 #include <drivers/arm/sp804_delay_timer.h>
14 #include <drivers/generic_delay_timer.h>
15 #include <lib/mmio.h>
16 #include <lib/smccc.h>
17 #include <lib/xlat_tables/xlat_tables_compat.h>
18 #include <platform_def.h>
19 #include <services/arm_arch_svc.h>
20 #if SPM_MM
21 #include <services/spm_mm_partition.h>
22 #endif
23
24 #include <plat/arm/common/arm_config.h>
25 #include <plat/arm/common/plat_arm.h>
26 #include <plat/common/platform.h>
27
28 #include "fvp_private.h"
29
30 /* Defines for GIC Driver build time selection */
31 #define FVP_GICV2 1
32 #define FVP_GICV3 2
33
34 /*******************************************************************************
35 * arm_config holds the characteristics of the differences between the three FVP
36 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot
37 * at each boot stage by the primary before enabling the MMU (to allow
38 * interconnect configuration) & used thereafter. Each BL will have its own copy
39 * to allow independent operation.
40 ******************************************************************************/
41 arm_config_t arm_config;
42
43 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
44 DEVICE0_SIZE, \
45 MT_DEVICE | MT_RW | MT_SECURE)
46
47 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
48 DEVICE1_SIZE, \
49 MT_DEVICE | MT_RW | MT_SECURE)
50
51 #if FVP_GICR_REGION_PROTECTION
52 #define MAP_GICD_MEM MAP_REGION_FLAT(BASE_GICD_BASE, \
53 BASE_GICD_SIZE, \
54 MT_DEVICE | MT_RW | MT_SECURE)
55
56 /* Map all core's redistributor memory as read-only. After boots up,
57 * per-core map its redistributor memory as read-write */
58 #define MAP_GICR_MEM MAP_REGION_FLAT(BASE_GICR_BASE, \
59 (BASE_GICR_SIZE * PLATFORM_CORE_COUNT),\
60 MT_DEVICE | MT_RO | MT_SECURE)
61 #endif /* FVP_GICR_REGION_PROTECTION */
62
63 /*
64 * Need to be mapped with write permissions in order to set a new non-volatile
65 * counter value.
66 */
67 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \
68 DEVICE2_SIZE, \
69 MT_DEVICE | MT_RW | MT_SECURE)
70
71 /*
72 * Table of memory regions for various BL stages to map using the MMU.
73 * This doesn't include Trusted SRAM as setup_page_tables() already takes care
74 * of mapping it.
75 *
76 * The flash needs to be mapped as writable in order to erase the FIP's Table of
77 * Contents in case of unrecoverable error (see plat_error_handler()).
78 */
79 #ifdef IMAGE_BL1
80 const mmap_region_t plat_arm_mmap[] = {
81 ARM_MAP_SHARED_RAM,
82 V2M_MAP_FLASH0_RW,
83 V2M_MAP_IOFPGA,
84 MAP_DEVICE0,
85 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
86 MAP_DEVICE1,
87 #endif
88 #if TRUSTED_BOARD_BOOT
89 /* To access the Root of Trust Public Key registers. */
90 MAP_DEVICE2,
91 /* Map DRAM to authenticate NS_BL2U image. */
92 ARM_MAP_NS_DRAM1,
93 #endif
94 {0}
95 };
96 #endif
97 #ifdef IMAGE_BL2
98 const mmap_region_t plat_arm_mmap[] = {
99 ARM_MAP_SHARED_RAM,
100 V2M_MAP_FLASH0_RW,
101 V2M_MAP_IOFPGA,
102 MAP_DEVICE0,
103 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
104 MAP_DEVICE1,
105 #endif
106 ARM_MAP_NS_DRAM1,
107 #ifdef __aarch64__
108 ARM_MAP_DRAM2,
109 #endif
110 #if defined(SPD_spmd)
111 ARM_MAP_TRUSTED_DRAM,
112 #endif
113 #ifdef SPD_tspd
114 ARM_MAP_TSP_SEC_MEM,
115 #endif
116 #if TRUSTED_BOARD_BOOT
117 /* To access the Root of Trust Public Key registers. */
118 MAP_DEVICE2,
119 #if !BL2_AT_EL3
120 ARM_MAP_BL1_RW,
121 #endif
122 #endif /* TRUSTED_BOARD_BOOT */
123 #if SPM_MM
124 ARM_SP_IMAGE_MMAP,
125 #endif
126 #if ARM_BL31_IN_DRAM
127 ARM_MAP_BL31_SEC_DRAM,
128 #endif
129 #ifdef SPD_opteed
130 ARM_MAP_OPTEE_CORE_MEM,
131 ARM_OPTEE_PAGEABLE_LOAD_MEM,
132 #endif
133 {0}
134 };
135 #endif
136 #ifdef IMAGE_BL2U
137 const mmap_region_t plat_arm_mmap[] = {
138 MAP_DEVICE0,
139 V2M_MAP_IOFPGA,
140 {0}
141 };
142 #endif
143 #ifdef IMAGE_BL31
144 const mmap_region_t plat_arm_mmap[] = {
145 ARM_MAP_SHARED_RAM,
146 #if USE_DEBUGFS
147 /* Required by devfip, can be removed if devfip is not used */
148 V2M_MAP_FLASH0_RW,
149 #endif /* USE_DEBUGFS */
150 ARM_MAP_EL3_TZC_DRAM,
151 V2M_MAP_IOFPGA,
152 MAP_DEVICE0,
153 #if FVP_GICR_REGION_PROTECTION
154 MAP_GICD_MEM,
155 MAP_GICR_MEM,
156 #else
157 MAP_DEVICE1,
158 #endif /* FVP_GICR_REGION_PROTECTION */
159 ARM_V2M_MAP_MEM_PROTECT,
160 #if SPM_MM
161 ARM_SPM_BUF_EL3_MMAP,
162 #endif
163 /* Required by fconf APIs to read HW_CONFIG dtb loaded into DRAM */
164 ARM_DTB_DRAM_NS,
165 {0}
166 };
167
168 #if defined(IMAGE_BL31) && SPM_MM
169 const mmap_region_t plat_arm_secure_partition_mmap[] = {
170 V2M_MAP_IOFPGA_EL0, /* for the UART */
171 MAP_REGION_FLAT(DEVICE0_BASE, \
172 DEVICE0_SIZE, \
173 MT_DEVICE | MT_RO | MT_SECURE | MT_USER),
174 ARM_SP_IMAGE_MMAP,
175 ARM_SP_IMAGE_NS_BUF_MMAP,
176 ARM_SP_IMAGE_RW_MMAP,
177 ARM_SPM_BUF_EL0_MMAP,
178 {0}
179 };
180 #endif
181 #endif
182 #ifdef IMAGE_BL32
183 const mmap_region_t plat_arm_mmap[] = {
184 #ifndef __aarch64__
185 ARM_MAP_SHARED_RAM,
186 ARM_V2M_MAP_MEM_PROTECT,
187 #endif
188 V2M_MAP_IOFPGA,
189 MAP_DEVICE0,
190 MAP_DEVICE1,
191 /* Required by fconf APIs to read HW_CONFIG dtb loaded into DRAM */
192 ARM_DTB_DRAM_NS,
193 {0}
194 };
195 #endif
196
197 ARM_CASSERT_MMAP
198
199 #if FVP_INTERCONNECT_DRIVER != FVP_CCN
200 static const int fvp_cci400_map[] = {
201 PLAT_FVP_CCI400_CLUS0_SL_PORT,
202 PLAT_FVP_CCI400_CLUS1_SL_PORT,
203 };
204
205 static const int fvp_cci5xx_map[] = {
206 PLAT_FVP_CCI5XX_CLUS0_SL_PORT,
207 PLAT_FVP_CCI5XX_CLUS1_SL_PORT,
208 };
209
get_interconnect_master(void)210 static unsigned int get_interconnect_master(void)
211 {
212 unsigned int master;
213 u_register_t mpidr;
214
215 mpidr = read_mpidr_el1();
216 master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ?
217 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr);
218
219 assert(master < FVP_CLUSTER_COUNT);
220 return master;
221 }
222 #endif
223
224 #if defined(IMAGE_BL31) && SPM_MM
225 /*
226 * Boot information passed to a secure partition during initialisation. Linear
227 * indices in MP information will be filled at runtime.
228 */
229 static spm_mm_mp_info_t sp_mp_info[] = {
230 [0] = {0x80000000, 0},
231 [1] = {0x80000001, 0},
232 [2] = {0x80000002, 0},
233 [3] = {0x80000003, 0},
234 [4] = {0x80000100, 0},
235 [5] = {0x80000101, 0},
236 [6] = {0x80000102, 0},
237 [7] = {0x80000103, 0},
238 };
239
240 const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
241 .h.type = PARAM_SP_IMAGE_BOOT_INFO,
242 .h.version = VERSION_1,
243 .h.size = sizeof(spm_mm_boot_info_t),
244 .h.attr = 0,
245 .sp_mem_base = ARM_SP_IMAGE_BASE,
246 .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
247 .sp_image_base = ARM_SP_IMAGE_BASE,
248 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
249 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
250 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
251 .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
252 .sp_image_size = ARM_SP_IMAGE_SIZE,
253 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
254 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
255 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
256 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
257 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
258 .num_cpus = PLATFORM_CORE_COUNT,
259 .mp_info = &sp_mp_info[0],
260 };
261
plat_get_secure_partition_mmap(void * cookie)262 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
263 {
264 return plat_arm_secure_partition_mmap;
265 }
266
plat_get_secure_partition_boot_info(void * cookie)267 const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
268 void *cookie)
269 {
270 return &plat_arm_secure_partition_boot_info;
271 }
272 #endif
273
274 /*******************************************************************************
275 * A single boot loader stack is expected to work on both the Foundation FVP
276 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The
277 * SYS_ID register provides a mechanism for detecting the differences between
278 * these platforms. This information is stored in a per-BL array to allow the
279 * code to take the correct path.Per BL platform configuration.
280 ******************************************************************************/
fvp_config_setup(void)281 void __init fvp_config_setup(void)
282 {
283 unsigned int rev, hbi, bld, arch, sys_id;
284
285 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
286 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK;
287 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK;
288 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK;
289 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK;
290
291 if (arch != ARCH_MODEL) {
292 ERROR("This firmware is for FVP models\n");
293 panic();
294 }
295
296 /*
297 * The build field in the SYS_ID tells which variant of the GIC
298 * memory is implemented by the model.
299 */
300 switch (bld) {
301 case BLD_GIC_VE_MMAP:
302 ERROR("Legacy Versatile Express memory map for GIC peripheral"
303 " is not supported\n");
304 panic();
305 break;
306 case BLD_GIC_A53A57_MMAP:
307 break;
308 default:
309 ERROR("Unsupported board build %x\n", bld);
310 panic();
311 }
312
313 /*
314 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010
315 * for the Foundation FVP.
316 */
317 switch (hbi) {
318 case HBI_FOUNDATION_FVP:
319 arm_config.flags = 0;
320
321 /*
322 * Check for supported revisions of Foundation FVP
323 * Allow future revisions to run but emit warning diagnostic
324 */
325 switch (rev) {
326 case REV_FOUNDATION_FVP_V2_0:
327 case REV_FOUNDATION_FVP_V2_1:
328 case REV_FOUNDATION_FVP_v9_1:
329 case REV_FOUNDATION_FVP_v9_6:
330 break;
331 default:
332 WARN("Unrecognized Foundation FVP revision %x\n", rev);
333 break;
334 }
335 break;
336 case HBI_BASE_FVP:
337 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC);
338
339 /*
340 * Check for supported revisions
341 * Allow future revisions to run but emit warning diagnostic
342 */
343 switch (rev) {
344 case REV_BASE_FVP_V0:
345 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400;
346 break;
347 case REV_BASE_FVP_REVC:
348 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 |
349 ARM_CONFIG_FVP_HAS_CCI5XX);
350 break;
351 default:
352 WARN("Unrecognized Base FVP revision %x\n", rev);
353 break;
354 }
355 break;
356 default:
357 ERROR("Unsupported board HBI number 0x%x\n", hbi);
358 panic();
359 }
360
361 /*
362 * We assume that the presence of MT bit, and therefore shifted
363 * affinities, is uniform across the platform: either all CPUs, or no
364 * CPUs implement it.
365 */
366 if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U)
367 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF;
368 }
369
370
fvp_interconnect_init(void)371 void __init fvp_interconnect_init(void)
372 {
373 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
374 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) {
375 ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported");
376 panic();
377 }
378
379 plat_arm_interconnect_init();
380 #else
381 uintptr_t cci_base = 0U;
382 const int *cci_map = NULL;
383 unsigned int map_size = 0U;
384
385 /* Initialize the right interconnect */
386 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) {
387 cci_base = PLAT_FVP_CCI5XX_BASE;
388 cci_map = fvp_cci5xx_map;
389 map_size = ARRAY_SIZE(fvp_cci5xx_map);
390 } else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) {
391 cci_base = PLAT_FVP_CCI400_BASE;
392 cci_map = fvp_cci400_map;
393 map_size = ARRAY_SIZE(fvp_cci400_map);
394 } else {
395 return;
396 }
397
398 assert(cci_base != 0U);
399 assert(cci_map != NULL);
400 cci_init(cci_base, cci_map, map_size);
401 #endif
402 }
403
fvp_interconnect_enable(void)404 void fvp_interconnect_enable(void)
405 {
406 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
407 plat_arm_interconnect_enter_coherency();
408 #else
409 unsigned int master;
410
411 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
412 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) {
413 master = get_interconnect_master();
414 cci_enable_snoop_dvm_reqs(master);
415 }
416 #endif
417 }
418
fvp_interconnect_disable(void)419 void fvp_interconnect_disable(void)
420 {
421 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
422 plat_arm_interconnect_exit_coherency();
423 #else
424 unsigned int master;
425
426 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
427 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) {
428 master = get_interconnect_master();
429 cci_disable_snoop_dvm_reqs(master);
430 }
431 #endif
432 }
433
434 #if TRUSTED_BOARD_BOOT
plat_get_mbedtls_heap(void ** heap_addr,size_t * heap_size)435 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
436 {
437 assert(heap_addr != NULL);
438 assert(heap_size != NULL);
439
440 return arm_get_mbedtls_heap(heap_addr, heap_size);
441 }
442 #endif
443
fvp_timer_init(void)444 void fvp_timer_init(void)
445 {
446 #if USE_SP804_TIMER
447 /* Enable the clock override for SP804 timer 0, which means that no
448 * clock dividers are applied and the raw (35MHz) clock will be used.
449 */
450 mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV);
451
452 /* Initialize delay timer driver using SP804 dual timer 0 */
453 sp804_timer_init(V2M_SP804_TIMER0_BASE,
454 SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV);
455 #else
456 generic_delay_timer_init();
457
458 /* Enable System level generic timer */
459 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
460 CNTCR_FCREQ(0U) | CNTCR_EN);
461 #endif /* USE_SP804_TIMER */
462 }
463
464 /*****************************************************************************
465 * plat_is_smccc_feature_available() - This function checks whether SMCCC
466 * feature is availabile for platform.
467 * @fid: SMCCC function id
468 *
469 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and
470 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise.
471 *****************************************************************************/
plat_is_smccc_feature_available(u_register_t fid)472 int32_t plat_is_smccc_feature_available(u_register_t fid)
473 {
474 switch (fid) {
475 case SMCCC_ARCH_SOC_ID:
476 return SMC_ARCH_CALL_SUCCESS;
477 default:
478 return SMC_ARCH_CALL_NOT_SUPPORTED;
479 }
480 }
481
482 /* Get SOC version */
plat_get_soc_version(void)483 int32_t plat_get_soc_version(void)
484 {
485 return (int32_t)
486 ((ARM_SOC_IDENTIFICATION_CODE << ARM_SOC_IDENTIFICATION_SHIFT)
487 | (ARM_SOC_CONTINUATION_CODE << ARM_SOC_CONTINUATION_SHIFT)
488 | FVP_SOC_ID);
489 }
490
491 /* Get SOC revision */
plat_get_soc_revision(void)492 int32_t plat_get_soc_revision(void)
493 {
494 unsigned int sys_id;
495
496 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
497 return (int32_t)((sys_id >> V2M_SYS_ID_REV_SHIFT) &
498 V2M_SYS_ID_REV_MASK);
499 }
500