1 /*
2 * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2019-2021, Intel Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <arch.h>
9 #include <arch_helpers.h>
10 #include <common/bl_common.h>
11 #include <common/debug.h>
12 #include <common/desc_image_load.h>
13 #include <drivers/generic_delay_timer.h>
14 #include <drivers/synopsys/dw_mmc.h>
15 #include <drivers/ti/uart/uart_16550.h>
16 #include <lib/xlat_tables/xlat_tables.h>
17
18 #include "qspi/cadence_qspi.h"
19 #include "socfpga_emac.h"
20 #include "socfpga_handoff.h"
21 #include "socfpga_mailbox.h"
22 #include "socfpga_private.h"
23 #include "socfpga_reset_manager.h"
24 #include "socfpga_system_manager.h"
25 #include "s10_clock_manager.h"
26 #include "s10_memory_controller.h"
27 #include "s10_pinmux.h"
28 #include "wdt/watchdog.h"
29
30 static struct mmc_device_info mmc_info;
31
32 const mmap_region_t plat_stratix10_mmap[] = {
33 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
34 MT_MEMORY | MT_RW | MT_NS),
35 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE,
36 MT_DEVICE | MT_RW | MT_NS),
37 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE,
38 MT_DEVICE | MT_RW | MT_SECURE),
39 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
40 MT_NON_CACHEABLE | MT_RW | MT_SECURE),
41 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
42 MT_DEVICE | MT_RW | MT_SECURE),
43 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE,
44 MT_DEVICE | MT_RW | MT_NS),
45 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE,
46 MT_DEVICE | MT_RW | MT_NS),
47 {0},
48 };
49
50 boot_source_type boot_source = BOOT_SOURCE;
51
bl2_el3_early_platform_setup(u_register_t x0,u_register_t x1,u_register_t x2,u_register_t x4)52 void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
53 u_register_t x2, u_register_t x4)
54 {
55 static console_t console;
56 handoff reverse_handoff_ptr;
57
58 generic_delay_timer_init();
59
60 if (socfpga_get_handoff(&reverse_handoff_ptr))
61 return;
62 config_pinmux(&reverse_handoff_ptr);
63
64 config_clkmgr_handoff(&reverse_handoff_ptr);
65 enable_nonsecure_access();
66 deassert_peripheral_reset();
67 config_hps_hs_before_warm_reset();
68
69 watchdog_init(get_wdt_clk());
70
71 console_16550_register(PLAT_UART0_BASE, get_uart_clk(), PLAT_BAUDRATE,
72 &console);
73
74 socfpga_emac_init();
75 socfpga_delay_timer_init();
76 init_hard_memory_controller();
77 mailbox_init();
78
79 if (!intel_mailbox_is_fpga_not_ready())
80 socfpga_bridges_enable();
81 }
82
83
bl2_el3_plat_arch_setup(void)84 void bl2_el3_plat_arch_setup(void)
85 {
86
87 const mmap_region_t bl_regions[] = {
88 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE,
89 MT_MEMORY | MT_RW | MT_SECURE),
90 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
91 MT_CODE | MT_SECURE),
92 MAP_REGION_FLAT(BL_RO_DATA_BASE,
93 BL_RO_DATA_END - BL_RO_DATA_BASE,
94 MT_RO_DATA | MT_SECURE),
95 #if USE_COHERENT_MEM_BAR
96 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
97 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
98 MT_DEVICE | MT_RW | MT_SECURE),
99 #endif
100 {0},
101 };
102
103 setup_page_tables(bl_regions, plat_stratix10_mmap);
104
105 enable_mmu_el3(0);
106
107 dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk());
108
109 mmc_info.mmc_dev_type = MMC_IS_SD;
110 mmc_info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
111
112 switch (boot_source) {
113 case BOOT_SOURCE_SDMMC:
114 dw_mmc_init(¶ms, &mmc_info);
115 socfpga_io_setup(boot_source);
116 break;
117
118 case BOOT_SOURCE_QSPI:
119 mailbox_set_qspi_open();
120 mailbox_set_qspi_direct();
121 cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL,
122 QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS,
123 QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0);
124 socfpga_io_setup(boot_source);
125 break;
126
127 default:
128 ERROR("Unsupported boot source\n");
129 panic();
130 break;
131 }
132 }
133
get_spsr_for_bl33_entry(void)134 uint32_t get_spsr_for_bl33_entry(void)
135 {
136 unsigned long el_status;
137 unsigned int mode;
138 uint32_t spsr;
139
140 /* Figure out what mode we enter the non-secure world in */
141 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
142 el_status &= ID_AA64PFR0_ELX_MASK;
143
144 mode = (el_status) ? MODE_EL2 : MODE_EL1;
145
146 /*
147 * TODO: Consider the possibility of specifying the SPSR in
148 * the FIP ToC and allowing the platform to have a say as
149 * well.
150 */
151 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
152 return spsr;
153 }
154
155
bl2_plat_handle_post_image_load(unsigned int image_id)156 int bl2_plat_handle_post_image_load(unsigned int image_id)
157 {
158 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
159
160 switch (image_id) {
161 case BL33_IMAGE_ID:
162 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
163 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry();
164 break;
165 default:
166 break;
167 }
168
169 return 0;
170 }
171
172 /*******************************************************************************
173 * Perform any BL3-1 platform setup code
174 ******************************************************************************/
bl2_platform_setup(void)175 void bl2_platform_setup(void)
176 {
177 }
178
179