1Sun Oct 31 2021 Todd Allen <todd.allen@etallen.com> 2 * Made new release. 3 4Sun Oct 31 2021 Todd Allen <todd.allen@etallen.com> 5 * cpuid.c: Support hypervisors which can move their range of leaves 6 to other base addresses, to support hypervisors under other 7 hypervisors: IS_HYPERVISOR_LEAF(), print_hypervisor_*(). 8 * cpuid.c: Separated out get_hypervisor(). This ended up being 9 unnecessary, but I prefer it anyway. 10 * cpuid.c: Added print_esc_substring() to print hypervisor_id values 11 that contain non-graphic characters. 12 13Fri Oct 29 2021 Todd Allen <todd.allen@etallen.com> 14 * cpuid.c: Improved (synth) decoding for Intel Xeon (3rd Gen) D2/M1 15 steppings. 16 17Wed Oct 27 2021 Todd Allen <todd.allen@etallen.com> 18 * cpuid.c: Added 0x40000001/eax support for ACRN hypervisor. Untested. 19 * cpuid.c: Added better decoding of 0x12/1 SECS.ATTRIBUTES fields. 20 21Tue Oct 26 2021 Todd Allen <todd.allen@etallen.com> 22 * cpuid.c: Added 5,3 model for Cyrix M1 6x86, based on Cyrix 6x86 23 Processor, Instruction Set document (M1-6). 24 * cpuid.c: Corrected wrong register passed to 25 print_40000009_edx_microsoft(). 26 27Mon Oct 25 2021 Todd Allen <todd.allen@etallen.com> 28 * cpuid.c: Adapted patch from Brian Inglis for easier Cygwin cygport, 29 but made an effort to reduce duplicate header file references, and 30 use of <sys/cpuset.h> for the right reasons (i.e. a more general 31 change). 32 * cpuid.c: For 12/n/ebx & 12/n/edx (n >= 2), mask the high 12 bits. 33 * cpuid.c: Added 0x40000001/eax(KVM) map gpa range hypercall & 34 MSR_KVM_MIGRATION_CONTROL. 35 36Sun Oct 24 2021 Todd Allen <todd.allen@etallen.com> 37 * cpuid.c: Add (synth) decoding for additional Alder Lake steppings. 38 * cpuid.c: Generalize (synth) decoding for Elkhart Lake B0. 39 * cpuid.c: Added 0x8000000a/edx guest SVME addr check. 40 * cpuid.c: Added 7/0/ecx bus lock detection. 41 * cpuid.c: Added 7/0/edx RTM transaction always aborts, TSX_FORCE_ABORT. 42 * cpuid.c: Added 0x40000001/eax (KVM) extended destination ID. 43 * cpuid.c: Added (synth) decoding for Vortex86EX2 & Vortex86DX2. Info 44 on these is almost nonexistent, so it's possible that these rules are 45 too specific or too vague. 46 * cpuid.c: Improved (synth) decoding for Tiger Lake: Pentium & Celeron. 47 * cpuid.c: Improved (synth) decoding for Elkhart Lake: Pentium & Celeron. 48 * cpuid.c: Improved (synth) decoding for Jasper Lake: Pentium & Celeron. 49 * cpuid.c: Improved (synth) decoding for (0,6)(10,5) Comet Lake: 50 Pentium, Celeron & Xeon. 51 * cpuid.c: Improved (synth) decoding for (0,6),(6,10) Ice Lake: 52 Xeon Scalable. 53 * cpuid.c: Improved (synth) decoding for AMD (8,15),(1,1) Raven Ridge: 54 Athlon Pro 200. 55 * cpuid.c: Improved (synth) decoding for AMD (8,15),(1,8) Picasso: 56 Athlon Pro 300. 57 * cpuid.c: Added (synth) decoding for AMD 4700S Desktop Kit. 58 * cpuid.c: Added (synth) decoding for AMD (8,15),(4,7) Lucienne. 59 60Sun Oct 24 2021 Todd Allen <todd.allen@etallen.com> 61 * cpuid.c: Added 0x80000008/ecx tscSize. 62 * cpuid.c: Added 0x8000001c/{eax,edx} continuous mode sampling. 63 * cpuid.c: Added 0x8000001c/{eax,edx] tsc in event record. 64 * cpuid.c: Added (synth) decoding for AMD Milan B1. 65 * cpuid.c: Added (synth) decoding for AMD Vermeer. 66 * cpuid.c: Added (synth) decoding for AMD Cezanne. 67 68Sat Oct 23 2021 Todd Allen <todd.allen@etallen.com> 69 * cpuid.c: Renamed 7/0/ecx 5-level paging to include LA57 & 57-bit addrs. 70 * cpuid.c: Improved 0xa/ebx presentation, and automatically mask bits 71 marked as invalid by 0xa/eax vector length. 72 * cpuid.c: Added 0x12/n/ecx new section property encoding. 73 * cpuid.c: Renamed Rocket Lake uarch to Cypress Cove. 74 * cpuid.c: Improved (synth) decoding for Tiger Lake. 75 * cpuid.c: Improved (synth) decoding for Rocket Lake. 76 77Fri Jul 16 2021 Ani Sinha <ani@anisinha.ca> 78 * cpuid.c: Add support for 0x40000003/eax reenlightenment control MSR 79 & 0x40000003/eax TscInvariant control MSR [on Microsoft Hyper-V]. 80 81Fri Jul 16 2021 Smita Koralahalli Channabasappa <Smita.KoralahalliChannabasappa@amd.com> 82 * cpuid.c: restoring the deleted "AMD (unknown model)" entry. 83 84Mon Jul 12 2021 Smita Koralahalli Channabasappa <Smita.KoralahalliChannabasappa@amd.com> 85 * cpuid.c: updates the existing leaf and subleaf in the CPUID with 86 features related to INVLPGB, CPPC, PSFD, SEV [affects 0x80000008/edx, 87 0x80000008/edx, and 0x8000001f/eax]. 88 * cpuid.c: defines new leaf 80000021/eax. 89 * cpuid.c: replaces the naming "Unknown Model" -> "AMD EPYC Milan" for 90 Family 19h and Model 01h [affects (synth) decoding]. 91 92Tue Feb 2 2021 Jonathan Teh <jonteh@ntlworld.com> 93 * From http://datasheets.chipdb.org/Cyrix/112ap.pdf (page 7, table 1): 94 * cpuid.c: Cyrix family 4 model 4 should be MediaGX or GXi 95 * cpuid.c: GXm is family 5, model 4 96 * cpuid.c: Cyrix MediaGX is derived from the 5x86 and unrelated to the 97 WinChip C6. Based on Wikipedia, the MediaGXm was renamed the Geode GXm 98 after it was sold to National Semi but the CPUs appear to have 99 continued to be sold under the Cyrix vendor up to and including the 100 Geode GX1. Hence, I've simply duplicated the names from NSC model 4 101 into Cyrix. 102 * cpuid.c: Model 9 for the WinChip 3 is moved to the Centaur section 103 [decode_synth_via()], from the datasheet page 3-11: 104 http://datasheets.chipdb.org/IDT/x86/WinChip3/winchip_3_datasheet.pdf 105 * cpuid.c: The Cyrix CPU detection guide [112ap] also offers some 106 possible codenames from page 20, table 17 Cx486SLC/DLC/SRx/DRx (M0.5) 107 up to table 26 for the GXm. 108 109Mon Jan 4 2021 Todd Allen <todd.allen@etallen.com> 110 * cpuid.c: Corrected decode_amd_model()'s (0,15),(4,0) decodings for bti 111 values 0x29, 0x2a, and 0x2b. 112 * cpuid.c: Corrected wrong register passed to print_40000001_edx_kvm(). 113 114Mon Nov 2 2020 Brian Inglis <Brian.Inglis@SystematicSw.ab.ca> 115 * Makefile: Set BUILDROOT=$(DESTDIR) for easier Cygwin cygport support. 116 117Mon Oct 12 2020 Todd Allen <todd.allen@etallen.com> 118 * cpuid.c: Added (synth) decoding for (6,15),(3,0) AMD R-Series Bald 119 Eagle based on instlatx64 sample. 120 * cpuid.c: Added rudimentary synth & uarch decoding for Montage Jintide 121 Gen1, a CPU based on Intel Skylake (0,6),(5,5), and detectable by brand 122 string. 123 * cpuid.c: Fixed append_uarch() to pass stash, which improves uarch 124 [suffix] for Montage, Zhaoxin, and ZhangJiang CPUs. 125 126Tue Oct 6 2020 Todd Allen <todd.allen@etallen.com> 127 * Made new release. 128 129Tue Oct 6 2020 Todd Allen <todd.allen@etallen.com> 130 * cpuid.c: Added 6/eax enhanced hardware feedback interface. 131 * cpuid.c: Added 6/ecx number of enh hardware feedback classes. 132 * cpuid.c: Added 7/0/ecx KL: key locker. 133 * cpuid.c: Added 7/0/edx UINTR: user interrupts. 134 * cpuid.c: Added 7/0/edx AVX512_FP16: fp16 support. 135 * cpuid.c: Added 7/1/eax AVX-VNNI: AVX VNNI neural network instrs. 136 * cpuid.c: Added 7/1/eax zero-length MOVSB. 137 * cpuid.c: Added 7/1/eax fast short STOSB. 138 * cpuid.c: Added 7/1/eax fast short CMPSB, SCASB. 139 * cpuid.c: Added 7/1/eax HRESET: history reset support. 140 * cpuid.c: Added 0xa/ecx fixed counter support enumeration. 141 * cpuid.c: Added 0xd/0/eax IA32_XSS UINTR state. 142 * cpuid.c: Added 0xd/n UINTR feature. 143 * cpuid.c: Added 0x19 key locker features. 144 * cpuid.c: Added 0x20 HRESET features. 145 146Mon Oct 5 2020 Todd Allen <todd.allen@etallen.com> 147 * cpuid.c: Added (7,5),(2,6) AMD Cato (synth) decoding based on 148 instlatx64 example (possibly an engr sample). 149 150Sun Oct 4 2020 Todd Allen <todd.allen@etallen.com> 151 * cpuid.c: Corrected 6/edx size field to use minus-one notation. 152 * cpuid.c: Added 7/0/edx AMX flags. 153 * cpuid.c: Added 0xd XTILECFG & XTILEDATA features. 154 * cpuid.c: Added 0xd/1/eax XFD: extended feature disable supported flag. 155 * cpuid.c: Added 0xd/n/ecx XFD: faulting supported flag. 156 * cpuid.c: Added 0x18/0/edx: load-only TLB & store-only TLB encodings. 157 * cpuid.c: Added 0x1d leaf (Tile info) decoding. 158 * cpuid.c: Added 0x1e leaf (TMUL) decoding. 159 * cpuid.c: Added 0x1c leaf (architectural LBR) decoding. 160 * cpuid.c: Added 0xd LBR features. 161 162Sun Oct 4 2020 Todd Allen <todd.allen@etallen.com> 163 * cpuid.c: Added (synth) steppings for Comet Lake (0,6),(10,6) CPUs. 164 For the first time in a long time, Intel actually provided this in 165 the revision guide (615213)! 166 * cpuid.c: Corrected (synth) decoding for AMD (8,15),(2,0) Dali CPUs. 167 * cpuid.c: Added (synth) decoding for AMD Dali A1 stepping. 168 * cpuid.c: Added (synth) decoding for AMD Picasso A1 stepping. 169 * cpuid.c: Added (synth) decoding for AMD Renoir A1 stepping. 170 171Sat Oct 3 2020 Todd Allen <todd.allen@etallen.com> 172 * cpuid.c: Added 7/0/ecx PKS flag. 173 * cpuid.c: Added 7/0/edx SRBDS flag, from Linux kernel. 174 * cpuid.c: Added 7/0/edx LBR flag. 175 * cpuid.c: Added 0xd/0/eax IA322_XSS HWP state flag. 176 * cpuid.c: Added synth decoding for Rocket Lake. 177 * cpuid.c: Added synth decoding for Elkhart Lake B0. 178 * cpuid.c: Added synth decoding for Alder Lake [Golden Cove]. 179 * cpuid.c: Clarified synth decoding for (0,6),(8,10) Lakefield. 180 * cpuid.c: Added KVM interrupt-based page-ready APF event flag. 181 182Sat Aug 8 2020 Todd Allen <todd.allen@etallen.com> 183 * cpuid.c: Corrected 0x20000001/edx header. 184 * cpuid.c: Detect bogus 0x20000000 leaf values and cap the maximum 185 valid register for the 0x2xxxxxxx range to avoid absurdly long dumps 186 on old CPUs. 187 188Mon Aug 3 2020 Todd Allen <todd.allen@etallen.com> 189 * cpuid.c: Added bzero before cpuid instruction, in case the cpuid 190 instruction quietly fails. This mostly is paranoia, but I don't see 191 how this ever could cause harm. 192 193Mon Jun 8 2020 Todd Allen <todd.allen@etallen.com> 194 * cpuid.c: Added Tiger Lake-U B0 stepping, from coreboot. 195 * cpuid.c: Added AMD (8,15),(2,0) Picasso model synth & uarch decoding. 196 197Sun May 24 2020 Todd Allen <todd.allen@etallen.com> 198 * cpuid.c: Added Zhaoxin KX-6000 decoding that still claims the vendor 199 CentaurHauls. Later Zhaoxin CPUs were supposed to use their own 200 vendor, but instlat64x showed an example that still used the old one. 201 202Sat May 16 2020 Todd Allen <todd.allen@etallen.com> 203 * cpuid.c: Added better (synth) decoding for Intel Comet Lake-H/S 204 Core i*-10000 CPUs, based on instlatx64 example and listings in 205 ark.intel.com. 206 207Tue Apr 28 2020 Todd Allen <todd.allen@etallen.com> 208 * cpuid.c: Added 0x8000000a/edx INVLPGB/TLBSYNC hypervisor intercept 209 enable flag. 210 211Mon Apr 27 2020 Todd Allen <todd.allen@etallen.com> 212 * Made new release. 213 214Wed Apr 22 2020 Todd Allen <todd.allen@etallen.com> 215 * cpuid.c: Added synth decoding for AMD Steppe Eagle/Crowned Eagle 216 (Puma 2014 G-Series), based on instlatx64 sample. 217 218Thu Apr 16 2020 Todd Allen <todd.allen@etallen.com> 219 * cpuid.c: Added 7/0/edx SERIALIZE & TSXLDTRK bit descriptions. 220 * cpuid.c: Added 0xf/1/eax Counter width & overflow flag. 221 * cpuid.c: Added 0x10/3/ecx per-thread MBA controls flag. 222 * cpuid.c: Added 0x8000001f fields. 223 * cpuid.man: Added AMD 24594 & 40332 docs. 224 225Tue Mar 3 2020 Todd Allen <todd.allen@etallen.com> 226 * cpuid.c: Corrected field lengths in 14/0 and 14/1 subleafs so that 227 columns line up. 228 229Thu Feb 27 2020 Todd Allen <todd.allen@etallen.com> 230 * cpuid.c: Added CC150 (Coffee Lake R0) synth decoding, based on 231 instlatx64 example. 232 233Wed Feb 26 2020 Todd Allen <todd.allen@etallen.com> 234 * cpuid.c: Added Jasper Lake A0 stepping (from Coreboot*). 235 * cpuid.c: Updated 1/ebx "cpu count" to modern terminology: "maximum 236 addressible IDs for CPUs in pkg" to avoid user confusion. It was a 237 reliable count of the number of CPUs for only a split second some time 238 around 2002. Maybe. 239 * cpuid.c: Updated 4/eax CPU & core count terminology in the same way. 240 241Tue Feb 11 2020 Todd Allen <todd.allen@etallen.com> 242 * Made new release. 243 244Mon Feb 10 2020 Todd Allen <todd.allen@etallen.com> 245 * cpuid.c: Clarified Intel NNP-I (Spring Hill). 246 * cpuid.c: In decode_vendor(), report "Zhaoxin" even with VENDOR_VIA, 247 if the brand string indicates so. 248 * cpuid.c: In 0xc0000004/ebx, make current voltage use the shift-4 + 700 249 encoding used for other VIA voltages. 250 251Fri Feb 7 2020 Todd Allen <todd.allen@etallen.com> 252 * cpuid.man: Use both Intel doc numbers for 329671/600827. 253 * cpuid.man: Added missing 329901/600834 Intel doc. 254 255Thu Feb 6 2020 Todd Allen <todd.allen@etallen.com> 256 * cpuid.c: Added VIA 0xc0000004 leaf decoding. 257 * cpuid.c: Added X2_IMAGES special flag to pretty-print values in the 258 2X encoding. 259 * cpuid.c: Added MINUS1_IMAGES special flag to pretty-print values with 260 the "- 1" encoding. (I finally got turned around about this being 261 better than the older "raw" values.) 262 263Wed Feb 5 2020 Todd Allen <todd.allen@etallen.com> 264 * cpuid.c: Add VIA C7-D and Eden brands to (0,6),(0,10) (synth). 265 * cpuid.c: Differentiate VIA (0,6),(0,13) (synth) based on brand strings. 266 * cpuid.c: Overhaul of VIA 0xc0000002 leaf decoding. 267 * cpuid.c: Updated VIA Nano steppings (synth). 268 * cpuid.c: Removed extraneous WinChip & core words from C3 and later 269 VIA CPUs (synth). 270 271Wed Feb 5 2020 Todd Allen <todd.allen@etallen.com> 272 * cpuid.c: Changed mp_synth fields to use '=' separator instead of ':', 273 like every other value. 274 * cpuid.c: Changed processor serial number to use '=' separator instead 275 of ':', like every other value. 276 277Tue Feb 4 2020 Todd Allen <todd.allen@etallen.com> 278 * cpuid.man: Added 336907 doc with 7/0/ecx/TME bit description. 279 * cpuid.c: Removed LX* comment from 7/0/ecx/TME bit description. It's 280 documented after all. 281 282Tue Feb 4 2020 Todd Allen <todd.allen@etallen.com> 283 * cpuid.c: Clarified (0,6),(10,6) Comet Lake-U (synth). 284 285Mon Feb 3 2020 Todd Allen <todd.allen@etallen.com> 286 * Made new release. 287 288Mon Feb 3 2020 Todd Allen <todd.allen@etallen.com> 289 * cpuid.c: Removed comments about (0,6),(8,14),10 contradiction. 290 Coreboot* removed the incorrect code claiming it was Coffee Lake D0. 291 The actual code already reflected this resolution. 292 * cpuid.c: Removed now-redundant lines from decode_uarch_intel() for 293 the individual (0,6),(8,14) steppings. They all say Kaby Lake now, 294 so they aren't necessary. 295 * cpuid.c: Added (0,6),(4,14),8 Kaby Lake G0 and (0,6),(5,14),8 296 Kaby Lake-H A0 steppings to both (synth) and (uarch synth) that I found 297 in Coreboot*. I realized I was worrying too much about them. They are 298 at least wholly distinct steppings, so they don't constitute the 299 intra-stepping blurring that I saw with {Kaby,Amber,Whiskey,Comet} 300 Lake. They are more akin to the already-existing Cascade Lake & 301 Cooper Lake steppings. Perhaps those two new entries were just early 302 engineering samples for Kaby Lake. 303 * cpuid.c: Added (0,6),(9,14),13 stepping to decode_uarch_intel. The 304 fallback without a stepping is weak, and it should be avoided for 305 any actual known stepping. (Added a comment too.) 306 * Makefile: Changed my own Todd's Development rules to build on very old 307 systems, so that the executables will run at all on very old systems. 308 * Makefile: Changed -Wextra to -W. That isn't recommended on modern 309 gcc versions, but still works. And it is necessary on really old 310 gcc versions, because -Wextra produces a hard error. 311 312Sun Feb 2 2020 Todd Allen <todd.allen@etallen.com> 313 * Made new release. 314 315Sun Feb 2 2020 Todd Allen <todd.allen@etallen.com> 316 * Makefile, cpuid.proto.spec: Added FAMILY.NOTES to the list of files to 317 be included in tarball & rpm doc directory. That file still is messy, 318 but I reference it a lot, so maybe it will be useful to others too. 319 320Sun Feb 2 2020 Todd Allen <todd.allen@etallen.com> 321 * cpuid.c: Added old (synth) models from sandpile.org: AMD Elan SC400, 322 NSC Geode LX. 323 * cpuid.c: Added some old (synth) and (uarch synth) die process numbers 324 from sandpile.org. 325 * cpuid.c: Added stepping values from sandpile.org. 326 * cpuid.c: sandpile.org calls (0,6),(4,6) "Crystalwell". Arguably, that 327 is just the name of the L4 cache. But even Intel's ARK calls these 328 CPUs "Crystal Well". So I'm changing the name to "Crystal Well". The 329 uarch still is Haswell, so that should clarify any confusion. 330 * cpuid.c: sandpile.org calls (0,6),(4,7) "Brystalwell". The situation 331 is similar, but Intel does not use that name at all. I'm not renaming 332 these cores. 333 334Sun Feb 2 2020 Todd Allen <todd.allen@etallen.com> 335 * cpuid.c: Added leaf walking of the 0x20000000 (Intel Phi) range and 336 decoding of a single bit in 0x20000001, based on information in 337 sandpile.org. I found only a vague hint about this in the Intel Xeon 338 Phi Coprocessor System Developers Guide, but no details. 339 * cpuid.c: For the (0,11) family of Phi processors, placing them within 340 a K1OM family. The (0,6) Phi cores are just Airmont-derived, so left 341 them alone. 342 343Sat Feb 1 2020 Todd Allen <todd.allen@etallen.com> 344 * cpuid.c: Reverted Cedar Trail back to Cedarview. (Atom uArch name vs. 345 Core name vs. Platform name vs. SoC name is very confusing.) 346 347Sat Feb 1 2020 Todd Allen <todd.allen@etallen.com> 348 * cpuid.c: Added Broadwell (0,6),(3,13) steppings based on Coreboot*. 349 * cpuid.c: Added Haswell (0,6),(3,12) steppings based on Coreboot*. 350 * cpuid.c: Added Haswell-ULT (0,6),(4,5),0 stepping based on Coreboot*. 351 * cpuid.c: Added some Skylake (0,6),(4,14) steppings based on Coreboot*. 352 * cpuid.c: Added some Skylake (0,6),(5,14) steppings based on Coreboot*. 353 * cpuid.c: Added Kaby Lake-H (0,6),(9,14),9 stepping based on Coreboot*. 354 * cpuid.c: Added Cannon Lake (0,6),(6,6) steppings based on Coreboot*. 355 * cpuid.c: Added Apollo Lake (0,6),(5,12) A0 stepping based on Coreboot*. 356 * cpuid.c: Added Gemini Lake (0,6),(7,10) A0 stepping, and corrected 357 R0 stepping, based on Coreboot*. 358 * cpuid.c: Added Ice Lake-U/Y (0,6),(7,14) A0 stepping based on 359 Coreboot*, and disregarding inconsistent info from spec update. 360 * cpuid.c: Added Tiger Lake (0,6),(8,12) A0 stepping based on Coreboot*. 361 * cpuid.c: Added Elkhart Lake (0,6),(9,6) A0 stepping based on Coreboot*. 362 * cpuid.c: Added Comet Lake (0,6),(10,6) steppings based on Coreboot*. 363 * cpuid.c: Added Comet Lake-H/S (0,6),(10,5) steppings based on 364 Coreboot*. 365 366Sat Feb 1 2020 Todd Allen <todd.allen@etallen.com> 367 * cpuid.c: Added (uarch synth) decoding for (6,15),(0,0) Bulldozer, 368 based on engineering sample. 369 * cpuid.c: Added (uarch synth) & (synth) (6,15),(6,0) Excavator Carrizo 370 and Toronto, based on instlatx64 samples. 371 * cpuid.c: Added (uarch synth) decoding for (8,15),(0,0) Zen, based on 372 engineering sample. 373 * cpuid.c: Added Zhaoxin (0,7),(1,15) based on example. 374 * cpuid.c: Differentiate Zhaoxin ZhangJiang from VIA Isaiah [C7] in 375 (synth) and (uarch synth). Sadly, this implies a need to use brand 376 information for (uarch synth). 377 * cpuid.c: Addedd (synth) for VIA version of Zhaoxin ZhangJaing at 378 (0,7),(0,11). 379 * cpuid.c: Added Westmere-EP A0 & B0 stepping (synth) based on instlatx64 380 sample & wikipedia article. 381 * cpuid.c: Fixed bogus stepping in Centerton fallback (synth). 382 * cpuid.c: Added (0,6),(5,5),10 Cooper Lake (synth) & (uarch synth), 383 based on Qemu. 384 * cpuid.c: Added "AMD PRO A" as a 2nd string to detect AMD A-Series. 385 * cpuid.c: Differentiate Raven Ridge from Great Horned Owl/ 386 Banded Kestrel (synth), based on "Embedded" string in brand. 387 * cpuid.c: Added Merlin Falcon as R-Series alternative everywhere 388 G-Series Brown Falcon appears. 389 * cpuid.c: Added rules for EPYC Embedded to differentiate (synth) for 390 Snowy Owl and Naples, based on EPYC 3000 series. Untested, because I 391 have no examples. 392 393Fri Jan 31 2020 Todd Allen <todd.allen@etallen.com> 394 * cpuid.man: Added instlatx64.atw.hu. 395 * cpuid.man: Added -l and -s options. 396 397Fri Jan 31 2020 Todd Allen <todd.allen@etallen.com> 398 * cpuid.c: Added rudimentary (10,15) (synth) for AMD Zen 3. 399 400Fri Jan 31 2020 Todd Allen <todd.allen@etallen.com> 401 * cpuid.man: Added linux kernel note about intel-family.h. 402 * cpuid.c: Added rudimentary Tremont (synth) & (uarch synth). 403 * cpuid.c: Added tentative Ice Lake NNPI (synth) & (uarch synth). 404 * cpuid.c: Added rudimentary (0,6),(10,6) Comet Lake [Coffee Lake] 405 (synth) & (uarch synth). 406 407Fri Jan 31 2020 Todd Allen <todd.allen@etallen.com> 408 * cpuid.man: Added Intel Microcode Update Guidance document. 409 * cpuid.c: Removed br.generic check from dc (Core) query. It was useful 410 in the Yonah era, but has been problematic since. Instead, add a dG 411 (Generic) query and use that where needed for the Yonah CPUs. And a 412 few other users of dc now use dG. 413 * cpuid.c: Added (synth) for Apollo Lake D0 (collision with B0/B1?) & E0. 414 * cpuid.c: Generalized P4500 & U4500 (Arrandale/Clarkdale) (synth) names. 415 * cpuid.c: Added Broadwell-DE V3 (synth) alternate stepping. 416 * cpuid.c: Added Broadwell H 43e (synth). 417 * cpuid.c: Added Pentium 3700U / 3800U (synth). 418 * cpuid.c: Added Apollo Lake (Broxton) (synth). 419 * cpuid.c: Added Atom x5-E8000 (synth). 420 * cpuid.c: Added Pentium G6900 (Clarkdale K0) (synth). 421 * cpuid.c: Added Core i*-900 (Clarksfield) (query dc) (synth). 422 * cpuid.c: Added E5-4600 (Ivy Bridge) (synth) names. 423 * cpuid.c: Prefixed E to Jasper Forest Xeon (synth) names. 424 * cpuid.c: Added Xeon E3-1200 (Kaby Lake) (synth) specific line. 425 * cpuid.c: Added Xeon 6500 names to Beckon (synth). 426 * cpuid.c: Generalized Pentium 900 (Sandy Bridge) (synth) names. 427 * cpuid.c: Added Celeron T3000 / 900 / SU2300 (Wolfdale) (synth) names. 428 * cpuid.c: Added Pentium T4000 (Wolfdale) (synth) names. 429 * cpuid.c: Added Celeron M ULV 700 (Penryn) (synth). 430 * cpuid.c: Correct query to dc for Sandy Bridge-E Core (synth). 431 * cpuid.c: Added Pentium 1405 (Sandy Bridge-E) (synth). 432 * cpuid.c: Added Xeon D-2100 (Skylake stepping 4) (synth) names. 433 * cpuid.c: Added Core i9-7000X (Skylake-X) (synth). 434 * cpuid.c: Changed case of x for SoFIA (synth). 435 * cpuid.c: Simplified Westmere-EP Xeon (synth) names. 436 * cpuid.c: Added Atom x*-A3900 (Apollo Lake) (synth) names. 437 * cpuid.c: Added Rangeley core name to Atom C2000 (synth) names. 438 * cpuid.c: Clarified that all (0,6),(4,15) CPUs are Broadwell-{E,EX} 439 in (synth) lines. 440 * cpuid.c: Clarified that (0,6),(3,13) is Broadwell-U. 441 * cpuid.c: For (0,6),(4,6) (synth), MRG* 2018-08-31 shows stepping 1, 442 so that must be the only known stepping: G0. 443 * cpuid.c: Corrected Broadwell-Y Core M (synth). 444 * cpuid.c: Added (0,6),(9,14),11 Coffee Lake Pentium & Celeron (synth). 445 * cpuid.c: Corrected (0,6),(9,14),11 fallback (synth). 446 * cpuid.c: Clarified transition from i*-8000 to i*-9000 at 447 (0,6),(9,14),12 stepping in (synth) lines. 448 * cpuid.c: Added Puma 7 (synth). 449 * cpuid.c: Generalized Pentium B900C (Ivy Bridge) (synth). 450 * cpuid.c: Added Celeron G2000 (Haswell) (synth). 451 * cpuid.c: Clarified Haswell-E (synth). 452 * cpuid.c: Aded -4000 series to (0,6),(4,6) Core (synth) names. 453 * cpuid.c: Added (0,6),(3,14) Ivy Bridge Celeron (synth). 454 * cpuid.c: Corrected (0,6),(3,14) Cores as Ivy Bridge-E (synth). 455 * cpuid.c: Differentiate i*-8700 and i*-7700 Kaby Lake (synth). 456 * cpuid.c: Added (0,6),(8,14),9 Kaby Lake Pentium & Celeron (synth). 457 * cpuid.c: Differentiate (0,6),(8,14),9 Kaby Lake-Y and Amber Lake-Y 458 (synth) with test for -8000 Series in brand name, because there seems 459 to be no other way to tell. 460 * cpuid.c: Added XMM 7272 (SoFIA) (synth). 461 * cpuid.c: Added Coffee Lake R0 Xeon (synth). 462 * cpuid.c: Added Whiskey Lake W0 Pentium & Celeron (synth). 463 * cpuid.c: Correct (8,14) (uarch synth) to just Kaby Lake once all 464 instances of Coffee lake had been eliminated from that family. The 465 (9,14) family continues to include both Kaby Lake & Coffee Lake. 466 467Fri Jan 31 2020 Todd Allen <todd.allen@etallen.com> 468 * cpuid.man: Added Intel 600827 spec update. 469 * cpuid.c: Generalized Bay Trail-M/D (synth) names and expanded them. 470 * cpuid.c: Added Bay Trail-M/D D0/D1 (synth). 471 472Thu Jan 30 2020 Todd Allen <todd.allen@etallen.com> 473 * cpuid.c: Added VIA die processes for as many uarchs/cores as I could 474 find. 475 476Wed Jan 29 2020 Todd Allen <todd.allen@etallen.com> 477 * cpuid.c: Added comments about various Intel spec updates. 478 * cpuid.man: Removed extra "315593" garbage line. 479 * cpuid.c: Added (synth) for Broadwell-E R0 stepping. 480 * cpuid.c: Added stepping number for Apollo Lake B0/B1. 481 * cpuid.c: Differentiate (synth) between Core & Xeon (0,6),(3,15) 482 Haswell. 483 * cpuid.c: Differentiate (synth) between Core & Xeon (0,6),(2,12) 484 Westmere/Gulftown. 485 * cpuid.c: Simplified more (synth) i*-*000 combinations. 486 * cpuid.c: Removed duplicate slash in one Haswell (synth) line. 487 * cpuid.c: Correct Itanium Merced model/stepping confusion. 488 * cpuid.c: Added KX-5000 & KH-20000 to Zhaoxin WuDaoKou (synth). 489 * cpuid.c: Added die proess to Zhaoxin WuDaoKou (uarch synth). 490 * cpuid.c: Added Zhaoxin LuJiaZiu (0,7),(3,11) model (synth) & 491 (uarch synth). 492 493Tue Jan 28 2020 Todd Allen <todd.allen@etallen.com> 494 * cpuid.c: Differentiate (synth) between Bay Trail Pentiums, Celerons 495 & Atoms. 496 * cpuid.c: Differentiate (synth) between Braswell Pentiums & Celerons. 497 * cpuid.c: Corrected (synth) steppings for Braswell. 498 * cpuid.c: Add J3000 series to (synth) for Braswell. 499 * cpuid.c: Remove Pentium & Celeron items from {Kaby,Coffee,Comet} Lake 500 Core (synth). I'd already created separate items for those, but 501 missed removing the names from the Core-specific line. 502 503Mon Jan 27 2020 Todd Allen <todd.allen@etallen.com> 504 * Made new release. 505 506Mon Jan 27 2020 Todd Allen <todd.allen@etallen.com> 507 * cpuid.c: Changed 0x8000001e/ecx to display nodes per processor in N-1 508 notation, after receiving confirmation from AMD that this is correct. 509 510Sat Jan 25 2020 Todd Allen <todd.allen@etallen.com> 511 * cpuid.c: Fixed spelling of (size synth). I meant to always have 512 "synth" at the end of synthesized fields, and had that one flipped 513 around. 514 * cpuid.c: Clarified AVX512_VNNI: neural network instructions. 515 * cpuid.c: Clarified AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND. 516 * cpuid.c: Clarified AVX512_BF16: bfloat16 is a data format, not an 517 instruction. 518 * cpuid.c: Added 7/0/edx md-clear feature, found from Xen & Qemu 519 hypervisors. 520 * cpuid.c: Added 0x80000008/ebx ppin feature, found from Xen hypervisor. 521 * cpuid.c: Added 0x40000001/eax (KVM) flags. 522 * cpuid.c: Got rid of the Transmeta 0x80860001/eax family description, 523 which I missed when I got rid of all 1/eax families. It wasn't so 524 egregious, but it wasn't very valuable either. The Transmeta Crusoe 525 name already was in the (synth) leaf. 526 * cpuid.c: Wrote a version of bits_needed() that uses __builtin_clz 527 with gcc 3.4 and later. 528 * cpuid.c: Fixed bug with old asm-based bits_needed() function when the 529 input value was 0. 530 531Sat Jan 25 2020 Todd Allen <todd.allen@etallen.com> 532 * cpuid.c: Further clarified descriptions in 0x8000001f leaf, based on 533 text in AMD64 Architecture Programmer's Manual, Vol 3, 3.28. I had 534 missed these new fields in my earlier pass through the manual. 535 * cpuid.c: Added comments for more undocumented fields, noting where 536 the information came from, particularly SKC*, LX*, and sandpile.org. 537 * cpuid.c: Changed case of new descriptions. 538 * cpuid.c: Created Synth_Family() & Synth_Model() macros based on 539 print_1_eax & SKC's AMD_Family() macro. 540 * cpuid.c: Added (family synth) and (model synth) to 0x80000001/eax, 541 (AMD and Hygon variants), just like for 1/eax. 542 * cpuid.c: Added Castle Peak B0 stepping (synth), now that I know the 543 stepping name. 544 * cpuid.c: Changed 0x80000008/ebx "RDPRU instruction" field. 545 * cpuid.c: Clarified 0x80000020 leaf descriptions based on AMD 55803 PPR. 546 * cpuid.c: Modified print_apic_synth's bit width computations to reflect 547 change in terminology (core => thread, CU => core) in AMD Family 17h. 548 * cpuid.man: Updated 54945 PPR name, using newer doc from 549 developer.amd.com. 550 * cpuid.man: Added 55803 PPR, found by URL provided by AMD. 551 * cpuid.man: Updated sandpile.org URL. 552 553Sat Jan 25 2020 Todd Allen <todd.allen@etallen.com> 554 * cpuid.c: Selectively applied changes from Smita Koralahalli 555 Channabasappa's patch: "Add PQoS feature to CPUID utility and display 556 subleaf 1 for leaf 0x80000020 in the raw CPUID data." 557 * cpuid.c: Renamed fields which no longer are Intel-specific: 558 RDT-CMT/PQoS cache monitoring and RDT-CAT/PQE cache allocation. 559 560Fri Jan 24 2020 Todd Allen <todd.allen@etallen.com> 561 * cpuid.c: Shortened 0x8000001f leaf descriptions to <= 40 chars. 562 563Fri Jan 24 2020 Smita Koralahalli Channabasappa <Smita.KoralahalliChannabasappa@amd.com> 564 * cpuid.c: Add AMD Secure Encryption feature bits to CPUID utility. 565 * cpuid.c: Update CPUID utility with additional AMD specific features. 566 * cpuid.c: Handle naming issues of cores->threads at register 567 80000008_ecx and compute unit->core at register 8000001e_ebx for 568 families greater than 16h. Retains previously assigned names if 569 families are lesser than or equal to 16h. Family values are 570 determined by adding family number and extended family 571 number(80000001_eax[8:11] + 80000001_eax[20:27]) as described in PPR 572 under CPUID_Fn00000001_eax. 573 574Wed Jan 22 2020 Todd Allen <todd.allen@etallen.com> 575 * Made new release. 576 577Wed Jan 22 2020 Todd Allen <todd.allen@etallen.com> 578 * cpuid.c: In print_80000001_ebx_amd, removed two checks for 579 __M(val_1_eax) >= _XM(0) + _M(0). Yes, gcc, I know that "comparison 580 of unsigned expression >= 0 is always true", and I also know even a 581 half-assed optimizer will get rid of it, so I preferred clarity. But 582 people freak out if the compiler emits any warnings, no matter what 583 crazy -W options the've chosen. So I'm removing them. 584 * cpuid.c: Changed a bunch of ccstring return types to cstring. The 585 extra const in ccstring was meaningless for return types, but it 586 caused a ton of additional -Wignored-qualifiers warnings. No grousing 587 about those warnings; they seem legit. 588 * Makefile: Added -Wextra, so I'll see these before people complain 589 about them in the future. 590 591Tue Jan 21 2020 Todd Allen <todd.allen@etallen.com> 592 * cpuid.c: Changed Cannon Lake to Palm Cove when talking about uarch. 593 * cpuid.c: Added extra (0,6),(8,14),12 (unknown type) fallback. 594 * cpuid.c: Fixed (0,6),(8,14) Whiskey Lake typo. 595 * cpuid.c: Added i*-9000 names to (0,6),(9,14) Coffee Lake CPUs. 596 597Mon Jan 20 2020 Todd Allen <todd.allen@etallen.com> 598 * Made new release. 599 600Sun Jan 19 2020 Todd Allen <todd.allen@etallen.com> 601 * cpuid.c: Fixed (synth) decoding of Kaby Lake vs. Coffee Lake (and 602 their myriad "optimizations"). 603 * cpuid.c: Correctly (synth) decoding of Comet Lake, which was wildly 604 wrong. 605 * cpuid.c: Treating Whiskey Lake, Amber Lake, and Comet Lake as distinct 606 uarchs just causes absurd "Coffee Lake / Whiskey Lake / Amber Lake / 607 Comet Lake" uarch strings. Instead, call all of them Coffee Lake, but 608 turn off the core_is_uarch flag. This ends up treating the other 3 as 609 core names within the Coffee Lake uarch, which seems clearer. 610 * cpuid.c: Renamed Ice Lake to Sunny Cove when talking about uarch. 611 * cpuid.c: Renamed Tiger Lake to Willow Cove when talking about uarch. 612 * cpuid.c: Added (synth) differentiation between Whiskey Lake (U line) 613 & and Amber Lake (Y line). 614 * cpuid.c: Added (synth) differentiation between Whiskey Lake (8000 615 Series) and Comet Lake (10000 Series). 616 * cpuid.c: Separated (synth) for Goldmont Plus into Pentium & Celeron. 617 * cpuid.c: Fixed Moorefield (synth) to say Z3500 instead of Z3400. 618 * cpuid.c: Fixed (0,6),(5,5),7 to Cascade Lake-X. Core names should be 619 as specific as possible (in contrast to uarch names). 620 * cpuid.c: added (0,6),(2,7) Atom Z2000 Medfield (synth) based on 621 example found on instlatx64. 622 * cpuid.c: Renamed Cedarview (SoC name) to Cedar Trail (core name). 623 * cpuid.c: Added (0,6),(1,15) Havendale/Auburndale (synth). 624 * cpuid.c: Added VIA (0,6),(0,15) Esther C5J (synth). 625 * cpuid.c: Added VIA Nano steppings to (synth). 626 * cpuid.c: Added AMD Ryzen vs. EPYC (synth) differentiation to 627 Castle Peak / Rome. 628 * cpuid.c: Separated Mullins into Mullins (tablets) and Beema (desktop). 629 * cpuid.c: Separated Kabini into Kabini (desktop) and Kyoto (servers). 630 Also added Temash for A-Series, although they're all mixed up with 631 Kabini. 632 * cpuid.c: Added AMD (6,15),(3,8) Godavari (synth) decoding. 633 * cpuid.c: Added AMD (2,15),(0,3) Griffin (synth) decodings. 634 * cpuid.c: Removed duplicate junk code for AMD (1,15),(0,2) which 635 prevented the 3 and 10 steppings from being used. 636 * cpuid.c: Corrected some AMD (0,6),(0,8) Duron Applebred (synth) names. 637 * cpuid.c: Added AMD DG02SRTBP4MFA based on example found on instlatx64. 638 639Fri Jan 17 2020 Todd Allen <todd.allen@etallen.com> 640 * cpuid.c: Merged 0xb and 0x1f leaf code, much like what Len Brown of 641 Intel suggested a year ago. I don't know why I didn't just do that in 642 the first place. Merged field names look more like the 0x1f names, 643 because I thought they were clearer. 644 * cpuid.c: Removed type descriptions from "--- level ---" sub-headers. 645 Intel docs clarify the levels and types are not related. 646 * cpuid.c: Got rid of the ridiculously overloaded 1/eax family 647 descriptions. That information is nearly useless in isolation and 648 described much better in the new (uarch synth) field. 649 * cpuid.c: Also got rid of 0x80000001/eax family descriptions. It 650 wasn't nearly as bad, but still better to use the (uarch synth) field. 651 * cpuid.c: Because I removed that family information, also updated the 652 decode_uarch* functions with information about older CPU makers' 653 information. 654 * cpuid.c: Added vendor name to (uarch synth). 655 * cpuid.c: Fixed 4 and 0x8000001d leaf descriptions to say that the 656 values are in "minus 1" notation. Steven Noonan hinted that there was 657 something to check here, and there was. 658 * cpuid.c: Added (synth size) field to the 4 and 0x8000001d leaves to 659 compute the cache size, also based on a hint from Steven Noonan. 660 * cpuid.c: Added preliminary Zhaoxin decoding based on limited 661 information I could find. 662 * cpuid.c: Added missing uarch names to decode_uarch_intel(). 663 * cpuid.c: Added note about P5 Tillamook CPUs. 664 * cpuid.c: Added some more die process values. 665 666Thu Jan 16 2020 Todd Allen <todd.allen@etallen.com> 667 * Made new release. 668 669Thu Jan 16 2020 Todd Allen <todd.allen@etallen.com> 670 * cpuid.c: Added decode_uarch*() and moved the uarch suffixes there from 671 print_synth*(). print_synth_intel() and print_synth_amd() now call 672 that function to get the suffixes. 673 * cpuid.c: Added print_uarch_synth() to display just those suffixes. 674 * cpuid.c: Added (synth) decoding for Itanium Poulson & Kittson. 675 * cpuid.c: Correct (synth) decoding for Itanium Montecito, Millington, 676 Montvale, Tukwila. 677 * cpuid.c: Cleaned up AMD [Excavator] core names. 678 * cpuid.man: Added some missing Intel spec updates. 679 680Wed Jan 15 2020 Todd Allen <todd.allen@etallen.com> 681 * cpuid.c: Added "(family synth)" and "(model synth)" to do the combined 682 values used by the linux kernel and AMD. That is: 683 Family = XF + F 684 Model = (XM << 4) + M 685 * cpuid.c: Hunt down the fallback (synth) decodings that just list tons 686 of different possible meanings, all copied from the more specific 687 lines above them. They almost always are wrong; if they were right, 688 the more specific tests would've detected them. So, they're pure 689 guesswork. Replace them with "(unknown type)", which is more honest. 690 * cpuid.c: Simplified Intel Xeon Scalable descriptions. 691 * cpuid.c: Eliminated reiteration of i3-XXXX, i5-XXXX, i7-XXXX CPUs, 692 using i*-XXXX instead. 693 * cpuid.c: Added (synth) decoding for Core i*-4000U seen in the wild. 694 * cpuid.c: Correct missing = symbol in 0x80000001/eax transmeta leaf. 695 * cpuid.c: Added [K6], [K7], [K8] (synth) clarifications for AMD K8 CPUs. 696 * cpuid.c: Added (6,15),(6,5) (synth) based on sample from Alexandros 697 Couloumbis. 698 * cpuid.c: Added AMD "*-Series" queries for the various latters and 699 (synth) rules to use them. Added more rules for AMD architectures 700 that used this nomenclature. 701 * cpuid.c: Changed dO query to sO. 702 703Wed Jan 15 2020 Todd Allen <todd.allen@etallen.com> 704 * cpuid.c: Clarified (synth) for each microarchitecture to include 705 process-neutral microarchitecture names too: 706 {P6} = (Pentium Pro, Klamath, Deschutes, Katmai, Coppermine, 707 Tualatin, Mendocino, Cascades) 708 {Netburst} = [Willamette, Northwood, Prescott, Cedar Mill] 709 {P6 Pentium M} = (Banias), [Dothan, Yonah] 710 {Core} = [Merom, Penryn] 711 {Nehalem} = [Nehalem, Westmere] 712 {Sandy Bridge} = (Sandy Bridge, Ivy Bridge) 713 {Haswell} = (Haswell, Broadwell) 714 {Skylake} = (Skylake, Kaby Lake, Coffee Lake, Whiskey Lake, 715 Amber Lake, Cascade Lake, Comet Lake, Cooper Lake, 716 Cannon Lake) 717 {Sunny Cove} = (Ice Lake, Tiger Lake) 718 The similarities are hazy in places. But this seems useful to help 719 people who, for example, don't know "Cedar Mill", but do know 720 "Netburst". Also the number of Skylake-related architecture names 721 exploded, and not all "Lake" names belong to Skylake, so this helps to 722 clarify. 723 * cpuid.c: Corrected (synth) for Tolapai to 90nm process. 724 725Tue Jan 14 2020 Todd Allen <todd.allen@etallen.com> 726 * cpuid.c: Clarified Arrandale & Clarkdale as [Westmere]. 727 * cpuid.c: Clarified Bloomfield, Gainestown & Beckton as [Nehalem]. 728 * cpuid.c: Added [Merom] clarification to a couple CPUs that missed it. 729 * cpuid.c: Added [Cedar Mill] clarification to a couple CPUs that missed 730 it. 731 * cpuid.c: Clarified Dothan, Stealey, Crofton & Tolopai as [Dothan]. 732 * cpuid.c: Clarified Yonah, Sossaman as [Yonah]. 733 * cpuid.c: Did not clarify Banias as [Banias] because it appears there 734 are no non-Banias chips based on it. 735 * cpuid.man: Added handy wiki pages about microarchitectures. 736 737Mon Jan 13 2020 Todd Allen <todd.allen@etallen.com> 738 * cpuid.c: Added 6/eax HW_FEEDBACK flag. 739 * cpuid.c: Added 7/0/ecx ENQCMD flag. 740 * cpuid.c: Added 7/0/edx AVX512_VP2INTERSECT flag. 741 * cpuid.c: Added 7/1/eax AVX512_BF16 flag. 742 * cpuid.c: Added 0xd/0/eax flags for CET_U & CET_S state. 743 * cpuid.c: Added 0x80000008/ebx WBNOINVD flag. 744 * cpuid.c: Added 0x80000008/ebx SSBD flags from AMD white paper. 745 * cpuid.c: In 7/0/edx leaf, clarified PCONFIG as an instruction. 746 * cpuid.c: Added synth detection for Cyrix MediaGX (circa 1997 SoC). 747 * cpuid.c: Added 7/0/ecx TME flag, discovered in the linux-5.5-rc6 748 kernel source. 749 * cpuid.c: Added 0x80000008/ebx additional STIBP always on flag, 750 discovered in the linux-5.5-rc6 kernel source. 751 * cpuid.man: Added AMD SSBD white paper. 752 * cpuid.man: Added linux kernel note and clue on what to look for. 753 754Sun Jan 12 2020 Todd Allen <todd.allen@etallen.com> 755 * cpuid.c: Added Matisse B0 stepping based on sample from Steven Noonan. 756 * cpuid.c: Removed redundant dR lines from Pinnacle Ridge. (They could 757 come back if I see an EPYC based on Pinnacle Ridge, but they're 758 redundant now.) 759 760Sun Jan 12 2020 Todd Allen <todd.allen@etallen.com> 761 * Made new release. 762 763Sun Jan 12 2020 Todd Allen <todd.allen@etallen.com> 764 * Makefile, cpuid.proto.spec: Added INSTALL_STRIP to allow disabling the 765 install -s option. This makes rpmbuild & find-debuginfo.sh happy, 766 because they can find the cpuid debug information and create the 767 cpuid-debuginfo rpm. 768 * Makefile: Updated release target to move debugsource rpms too. 769 770Sun Jan 12 2020 Todd Allen <todd.allen@etallen.com> 771 * cpuid.c: Added 0x40000004 leaf for Xen hypervisor. 772 * cpuid.c: Added 0x40000005 leaf for Xen hypervisor. 773 * cpuid.c: Fixed errors with static ccstring arrays that were not large 774 enough to hold NULLs for all reserved bit field values. 775 * cpuid.c: Added AMD's CMT "compute unit" concept to print_apic_synth 776 by adding that architectural level above the "cores" level, which 777 relects AMD's portrayal. This level is displayed only if it is 778 present. 779 * cpuid.c: Added some undocumented synth decodings found on 780 https://en.wikichip.org/wiki/amd/cpuid. Not everything there makes 781 sense, so I didn't take everything. Marked with comments. 782 * cpuid.c: Added architecture tags to Intel synth decodings: 783 [Willamette], [Northwood], [Prescott], [Merom], [Penryn], [Nehalem], 784 [Westmere]. After that, Intel dropped the hyper-specific code names 785 in favor of suffix letters. 786 * cpuid.c: Added architecture tags to Intel synth decodings: [Bonnell], 787 [Saltwell], [Silvermont], [Airmont], [Goldmont], [Goldmont Plus]. 788 Intel continues to use hyper-specific names for Atom CPUs. 789 790Sat Jan 11 2020 Todd Allen <todd.allen@etallen.com> 791 * Makefile: Added -Wimplicit-fallthrough -Wunused-parameter options. 792 * cpuid.c: Clarified 4/edx WBINV/INVD flag. 793 * cpuid.c: Added new 7/edx flags, especially including new features to 794 mitigate speculative execution exploits. 795 * cpuid.c: Cleaned up output of 0x10 subleaves. 796 * cpuid.c: Added 0x12/0/ebx CPINFO for #CP exceptions in enclave. 797 * cpuid.c: Properly display 0x18 sub-leaf number. 798 * cpuid.c: Added leaf 0x1f V2 Topology logic to decode_mp_synth() and 799 print_apic_synth(). I have no physical examples, so I only could test 800 with artificial input files. 801 * cpuid.c: Added 3-way and 6-way associativity to 0x80000006 and 802 0x80000019 leaves. 803 * cpuid.c: Fixed incorrect fallthrough in switch for "41322 3.74: 804 table 16". 805 * cpuid.c: Fixed incorrect fallthrough's in switch for Family 12h tables. 806 * cpuid.c: Added UNUSED macro to make newer gcc's shut up about unused 807 formals. (They have one complaint if the name is omitted, and another 808 complaint if it's specified but unused. There's just no pleasing gcc.) 809 * cpuid.c: Added break after usage() to make gcc shut up about a 810 nonexistent fallthrough (even though it was marked with NOTREACHED). 811 * cpuid.c: Added missing newlines to all the print_2_byte Cyrix/VIA 812 special cases. 813 * cpuid.c: Fixed print_f_0_edx: QoS monitoring was in 0xf/0 bit 1, not 814 bit 0. 815 * cpuid.c: Added print_40000001_edx_kvm and appropriate call. 816 * cpuid.c: For 0x80000001/ebx amd, display PkgType for all family 16h 817 or higher systems, even if no specific BrandId breakdown is known. 818 Added encodings from AMD BKDG and PPR documents. 819 820Sat Jan 11 2020 Todd Allen <todd.allen@etallen.com> 821 * cpuid.c: Added proper synth decoding for Atom C3000 (Denverton). 822 * cpuid.c: Clarified Goldmont into eithe Apollo Lake or Denverton. 823 * cpuid.c: Corrected (0,6),(9,14) synth decoding to be Coffee Lake. 824 * cpuid.c: Added (0,6),(9,14) Coffee Lake synth decoding steppings. 825 * cpuid.c: Added (0,6),(9,14) Coffee Lake synth decoding for Xeon E-2100 826 & E-2200. 827 * cpuid.c: Added (0,6),(5,5),7 synth decoding for Xeon 2nd Gen Scalable. 828 * cpuid.c: Added (0,6),(5,5),7 synth decoding for Xeon D-2100. 829 * cpuid.c: Added synth decoding for Gemini Lake R0 stepping (same as B0). 830 * cpuid.c: Added vague synth decoding for (0,6),(6,6) Cannon Lake. 831 * cpuid.c: Added vague synth decoding for (0,6),(6,10) Ice Lake. 832 * cpuid.c: Added vague synth decoding for (0,6),(6,12) Ice Lake. 833 * cpuid.c: Added vague synth decoding for (0,6),(7,13) Ice Lake. 834 * cpuid.c: Added additional synth decodings for AMD Ryzen, including 835 Pinnacle Ridge. 836 * cpuid.c: Differentiate Ryzen from EPYC using brand string and new 837 query functions. 838 * cpuid.man: Added new spec updates, revision guides, etc. 839 840Sat Jan 11 2020 Todd Allen <todd.allen@etallen.com> 841 * Prettification of Masanori Misono's 0x40000001/eax KVM fields. 842 * Formatting changes & URL removal from Jeffrey Walton's SunOS patch. 843 * Prettification of Thomas Friebel's 0x40000003 leaf fix: while loop. 844 * Reverted print_header() to use !raw (personal preference of mine). 845 * Format changes to & rearrangement of fanjinke's Hygon patch. 846 847Fri Jan 3 2020 Thomas Friebel <friebelt@amazon.de> 848 * Fixed bug that skipped half the subleaves in the 0x40000003 hypervisor 849 leaf. 850 * Fixed contradictory try logic in print_header() for leaf 0x40000003. 851 * Fixed to use 0x40000003/ebx for high 32 bits of vtsc_offset, 852 instead of using eax for both high & low 32 bits. 853 854Mon May 13 2019 fanjinke <fanjinke@hygon.cn> 855 * Added Hygon support. 856 857Wed May 8 2019 Jeffrey Walton <noloader@gmail.com> 858 * cpuid.c: Added support for SunOS build. 859 860Sat Mar 2 2019 Masanori Misonoc <m.misono760@gmail.com> 861 * cpuid.c: Added 0x40000001/eax KVM bit fields. 862 863Fri Jun 1 2018 Tony Luck <tony.luck@intel.com> 864 * cpuid.c: Added decoding of 0x10/3 subleaf. 865 866Sat May 26 2018 Todd Allen <todd.allen@etallen.com> 867 * cpuid.c: Fixed 7/ecx spelling error: intruction. 868 * cpuid.c: Fixed main spelling error: unrecogized. 869 870Sat May 19 2018 Todd Allen <todd.allen@etallen.com> 871 * Made new release. 872 873Sat May 19 2018 Todd Allen <todd.allen@etallen.com> 874 * cpuid.c: Added some more fields reported by Stefan Kanthak, after 875 tracking down some documentation that explains them: 876 * cpuid.c: Added 7/ecx bit 7: CET_SS and 7/edx bit 20: CET_IBT fields. 877 So far, the only documentation for these is Control-flow Enforcement 878 Technology Preview (334525), section 8.2 Feature Enumeration. 879 * cpuid.c: Added 7/ecx bit 16: 5-level paging. So far, the only 880 documentation for this is 5-Level Paging and 5-Level EPT White Paper 881 (335252). 882 * cpuid.c: Improved 14/0/ecx descriptions. 883 * cpuid.c: Added hypervisor leaf descriptions from Microsoft's 884 Hypervisor Top Level Functional Specification (Released Version 5.0b). 885 * cpuid.man: Added the above mentioned docs. 886 887Thu May 17 2018 Todd Allen <todd.allen@etallen.com> 888 * cpuid.c: Added CPUID features documented in PPR for AMD Family 17h 889 Model 01h B1 (54945 Rev 1.14): 890 * cpuid.c: Added PCOMMIT to 7/ebx: PCOMMIT instruction (a deprecated 891 instruction). 892 * cpuid.c: Added bits to 80000001/ecx (amd). 893 * cpuid.c: Added 80000007/ebx. 894 * cpuid.c: Added 80000007/ecx. 895 * cpuid.c: Added bits to 80000007/edx. 896 * cpuid.c: Added 80000008/ebx. 897 * cpuid.c: Added bits to 8000000a/edx. 898 * cpuid.c: Added bits to 8000001a/eax. 899 * cpuid.c: Added bits to 8000001b/eax. 900 * cpuid.c: Added tentative 8000001f descriptions. Information obtained 901 from Linux kernel 4.17-rc5 arch/x86/kernel/cpu/scattered.c (as patched 902 by Tom Lendacky of AMD on 18-Apr-2017 via LKML), and from Secure 903 Encrypted Virtualization API Version 0.16 Technical Preview 904 (55766 Rev 3.06). 905 * cpuid.man: Added 54945 & 55766 docs. 906 907Thu Apr 19 2018 Todd Allen <todd.allen@etallen.com> 908 * Made new release. 909 910Wed Apr 19 2018 Todd Allen <todd.allen@etallen.com> 911 * cpuid.c: Fixed various bugs reported by Stefan Kanthak: 912 * cpuid.c: Fixed bug in print_2_meaning: 0x49 normal & special cases. 913 * cpuid.c: Fixed bug in print_2_meaning: 0x63 additional 2M/4M, 4-way, 914 32 entries item. 915 * cpuid.c: Collapsed print_2_meaning into print_2_byte so that the 916 prefix and CONT are known in one place. 917 * cpuid.c: Fixed bug in print_2_byte: 0x7d is not sectored. 918 * cpuid.c: Fixed bug in print_2_byte: 0xc2 is 4K, not 4M. 919 * cpuid.c: Changed 6/ecx bit 0 to "hardware coordination feedback". 920 * cpuid.c; Changed 7/ebx bit 3 to "BMI1 instructions". 921 * cpuid.c: Change 7/ebx bit 12 to RDT-M. 922 * cpuid.c: Change 7/ebx bit 15 to RDT-A. 923 * cpuid.c: Corrected "0x40000003/ecx" label. 924 * cpuid.c; print_40000003_edx_microsoft: corrected "idle" spelling. 925 926Wed Apr 19 2018 Todd Allen <todd.allen@etallen.com> 927 * cpuid.c: Added mnemonic letters for some 1/ecx, 1/edx, and 7/ebx leaf 928 fields. 929 * cpuid.c: Fixed bug with 4/ecx: field name should be "number of sets". 930 * cpuid.c: Fixed bug with 4/ecx leaf: pass ECX to it! 931 * cpuid.c; Fixed bug with 0x10/ecx: pass ECX to it! 932 * cpuid.c: Fixed bug with 0x10/edx: pass EDX to it! 933 934Sun Apr 8 2018 Todd Allen <todd.allen@etallen.com> 935 * cpuid.c: Added 2 leaf 0xfe encoding: TLB data in leaf 0x18. 936 * cpuid.c: Added new Intel 6/eax bit fields. 937 * cpuid.c: Added new Intel a/edx bit field: anythread deprecation. 938 * cpuid.c: Added new Intel d/0/eax bit field: IA32_XSS HDC state. 939 * cpuid.c: Added new Intel 10/0/ebx bit field: memory bandwidth alloc. 940 * cpuid.c: Added new Intel 12/0/eax bit fields 941 * cpuid.c: Added new Intel 18 leaf: deterministic address translation. 942 * cpuid.c: Added new Intel 7/ecx bit fields from Intel Architecture 943 Instruction Set Extensions and Future Features Programming Reference. 944 * cpuid.c: Added new Intel 1b leaf from Intel Architecture 945 Instruction Set Extensions and Future Features Programming Reference. 946 * cpuid.c: Added synth decoding for Avoton C0 stepping (same as B0). 947 * cpuid.c: Corrected synth decoding for Bay Trail-M C0 steppings. 948 * cpuid.c: Added synth decoding for Bay Trail-I (E3800). 949 * cpuid.c: Added synth decoding for Xeon D-1500N (Broadwell-DE A1). 950 * cpuid.c: Added synth decoding for Xeon E7-4800/8800 (Broadwell-EX B0). 951 * cpuid.c: Correct synth decoding for Bay Trail A0. 952 * cpuid.c: Added synth decoding for Bay Trail D0. 953 * cpuid.c: Added synth decoding for Core X-Series (Skylake-X). 954 * cpuid.c: Added synth decoding for Xeon Scalable (Bronze, Silver, Gold, 955 Platinium) (Skylake). 956 * cpuid.c: Added synth decoding for Pentium Silver (Gemini Lake). 957 * cpuid.c: Added synth decoding for AMD Zen. 958 * cpuid.man: Added new spec updates & PPR. 959 960Fri Nov 3 2017 Todd Allen <todd.allen@etallen.com> 961 * cpuid.c, cpuid.man: Attribute whitepaper to Shih Kuo. 962 963Wed Jun 22 2017 Lars Wendler <polynomial-c@gentoo.org> 964 * cpuid.c: recent glibc versions no longer automagically include 965 sysmacros.h headers. This needs to be done by the source files itself 966 now. 967 968Fri Mar 3 2017 Todd Allen <todd.allen@etallen.com> 969 * cpuid.c: Added missing SDBG bit to 1/ecx leaf. 970 971Sun Jan 22 2017 Todd Allen <todd.allen@etallen.com> 972 * Made new release. 973 * cpuid.c: Use __cpuid_count macro for "cpuid" instruction if possible. 974 This macro is present in gcc 4.3.0 and later, and works around the fact 975 that the cpuid instruction writes on the PIC register. This is only 976 important when compiling PIC/PIE. 977 * cpuid.c: Added synth decoding for Intel Knights Landing B0. The Intel 978 docs still don't specify the stepping numbers, but all examples seen 979 so far have stepping number 1, and so far B0 is the only stepping. 980 * cpuid.c: Added new synth decodings for Intel Kaby Lake. 981 * cpuid.c: Fixed synth decodings for AMD Steamroller. 982 * cpuid.c: Fixed synth decodings for AMD Jaguar. 983 * cpuid.c: Added synth decodings for AMD Puma. 984 * cpuid.c: Added synth decodings for AMD Excavator. 985 * cpuid.c: For (6,15),(0,2) Piledriver processors, detect FX series 986 and report it as Vishera instead of Abu Dhabi/Seoul/Delhi. 987 * cpuid.c: Added general microarchitecure names for AMD (e.g. 988 Piledriver) in addition to specific core names (e.g. Trinity) for 989 later generation processors. If I have trouble remembering these, 990 it seems likely other people do too. 991 * cpuid.c: Added synth decoding for Quark X1000. 992 * cpuid.c: Added Intel Atom Z2760 (Clover Trail). 993 * cpuid.c: Added extra synth decodings for some Sandy Bridge processors. 994 * cpuid.c: Added extra synth decodings for some Ivy Bridge processors. 995 * cpuid.man: Added new & missing spec updates & revision guides. 996 * FUTURE: Cleaned this up somewhat. 997 998Mon Dec 5 2016 Todd Allen <todd.allen@etallen.com> 999 * cpuid.c: Removed stale len variable from do_file(). 1000 1001Thu Dec 1 2016 Todd Allen <todd.allen@etallen.com> 1002 * Made new release. 1003 1004Wed Nov 30 2016 Todd Allen <todd.allen@etallen.com> 1005 * cpuid.c: Fixed bugs in the subleaf walks for 0x8000001d (AMD cache 1006 information) and 0x40000003 (Xen hypervisor information) because the 1007 code for them was under wholly the wrong loops. Thanks to Brice 1008 Goglin for detecting this and working out the cause of the bug. 1009 1010Wed Nov 16 2016 Todd Allen <todd.allen@etallen.com> 1011 * cpuid.c: Updated comments referencing 325462 Table 35-1 to also 1012 specify Volume 3. 1013 * cpuinfo2cpuid: Added grep commands to EXAMPLES. 1014 1015Mon Nov 14 2016 Todd Allen <todd.allen@etallen.com> 1016 * Made new release. 1017 * cpuid.man: Added 334663 & 334820 spec updates. 1018 1019Sun Nov 13 2016 Todd Allen <todd.allen@etallen.com> 1020 * cpuid.c: Fixed bug reported by Andrew Cooper where, in do_real, for 1021 the 0xd leaf, the lower half of the valid bit set for XSS should've 1022 used 0xd/1/ecx instead of 0xd/1/eax. Sadly, this bug affects raw 1023 dumps too. 1024 * cpuid.c: Added -l/--leaf and -s/--subleaf options to cause cpuid 1025 to dump just the specified leaf and subleaf. If -s/--subleaf is not 1026 specified, it is assumed to be 0. The intended purpose for this is 1027 to display raw dumps of not-yet-supported leaves, or to workaround 1028 bugs like the above. 1029 1030Sat Nov 12 2016 Todd Allen <todd.allen@etallen.com> 1031 * cpuid.c: In bits_needed, add a further check for !defined(__ILP32__), 1032 which should help with building a 32-bit version of cpuid on a 64-bit 1033 system. 1034 1035Sat Nov 12 2016 Todd Allen <todd.allen@etallen.com> 1036 * cpuid.c: Made editorial changes to Piotr Luc's patches (spelling, 1037 capitalization, register order, comments, etc.). 1038 * cpuid.c: Added AVX512DQ, AVX512IFMA, AVX512BW, AVX512VL, and CLWB 1039 decoding to 7/ebx. 1040 * cpuid.c: Added AVX512VBMI to 7/ecx. 1041 * cpuid.c: Added print_f_0_edx to show L3 cache QoS monitoring support. 1042 * cpuid.c: Added total & local bandwidth monitoring to 0xf/1/edx. 1043 * cpuid.c: Added 0x15/ecx nominal core crystal clock decoding. 1044 * cpuid.c: In print_17_0_ebx, corrected reversed scheme encodings. 1045 * cpuid.c: Added synth decoding for Xeon D-1500 (Broadwell-DE) Y0 1046 stepping. 1047 * cpuid.c: Added synth decoding comment about Braswell D1 stepping, but 1048 its stepping number isn't documented. 1049 * cpuid.c: Added synth decoding for (0,6),(8,14) Kaby Lake processors. 1050 * cpuid.c: Added synth decoding for Apollo Lake processors. 1051 * cpuid.c: Added vague synth decoding for (0,6),(9,14) Kaby Lake 1052 processors. 1053 * cpuid.c: Re-sorted (0,6),(5,7) Knights Landing to correct position. 1054 * cpuid.c: Re-sorted (0,6),(5,15) Goldmont to correct position. 1055 1056Sat Oct 27 2016 Piotr Luc <Piotr.Luc@intel.com> 1057 * cpuid.c: Add AVX512_4VNNIW & AVX512_4FMAPS flags. 1058 * cpuid.c: Add Knights Mill (KNM) CPUID. 1059 1060Sun Aug 14 2016 Todd Allen <todd.allen@etallen.com> 1061 * Made new release. 1062 * Makefile: Added clean rules to remove tarballs & rpm's with other 1063 version numbers. 1064 1065Sun Aug 14 2016 Todd Allen <todd.allen@etallen.com> 1066 * cpuinfo2cpuid: Added a script that takes input from a /proc/cpuinfo 1067 file and converts it into suitable input to cpuid. The information 1068 that cpuid is capable of producing based on this very limited input 1069 information is slight, but apparently there is interest in getting the 1070 synthesized (synth) leaf from this. There isn't much value in using 1071 it with an actual /proc/cpuinfo file on the local system, because just 1072 allowing cpuid to read the local cpuid info will provide better 1073 output. But it could be useful for interpreted saved /proc/cpuinfo 1074 files from another system. I slapped together the basic logic, and 1075 Jirka Hladky turned it into a proper perl script, with actual options, 1076 a help screen, and even documentation. I then made some changes to 1077 give it some more uniform indentation, whitespace, and such. And to 1078 give Jirka Hladky more credit, since his contribution to the script is 1079 larger than my own. 1080 * Makefile: Added rules to generate cpuinfo2cpuid.man from the =pod data 1081 in the script. 1082 * Makefile: Added cpuinfo2cpuid & cpuinfo2cpuid.man to the released 1083 materials. 1084 * cpuid.proto.spec: Added cpuinfo2cpuid & cpuinfo2cpuid.1.gz to released 1085 materials. 1086 1087Sun Aug 14 2016 Todd Allen <todd.allen@etallen.com> 1088 * cpuid.c: Changed instances of Kb to KB. In print_2_meaning, changed 1089 an instance of 4k to 4K. 1090 1091Sat Aug 13 2016 Todd Allen <todd.allen@etallen.com> 1092 * cpuid.c: Added 7/ebx SGX & FDP_EXCPTN_ONLY flags. 1093 * cpuid.c: Added 7/ecx BNDLDX/BNDSTX MAWAU value field, RDPID & SGX_LC. 1094 * cpuid.c: Added d/0/eax MPX state field. 1095 * cpuid.c: In print_d_0_eax, split MPX and AVX-512 all_or_none fields 1096 into their component parts. Also added IA32_XSS PT state. 1097 * cpuid.c: In print_d_n_ecx, clarify XCR0 as user state and IA32_CXX as 1098 supervisor state. 1099 * cpuid.c: In print_d_n, add MPX and PT features. 1100 * cpuid.c: Renamed leaf 0x10 to Intel's new name. Corrected totally 1101 bogus interpretation of subleaf 0. 1102 * cpuid.c: Generalize subleaf 0x10/1 to also include 0x10/2, and 1103 provide new Intel correct names for each. 1104 * cpuid.c: Added 0x14/0 PTWRITE & power event trace. 1105 * cpuid.c: Added description for leaf 0x12 (SGX Capability) and all its 1106 subleaves. 1107 * cpuid.c: Added descriptionf or leaf 0x17 (SoC vendor) and its 1108 subleaves. 1109 * cpuid.c: Decode new leaf 2 cache descriptors: 0x64 & 0xc4. 1110 * cpuid.c: Updated Atom C2000 (Avoton) with A0/A1 steppings. 1111 * cpuid.c: Added Atom Z3n00 (Bay Trail-T B2/B3) specific stepping 1. 1112 * cpuid.c: Added Xeon D-1500 (Broadwell-DE) V2 stepping. 1113 * cpuid.c: Corrected Atom Z8000 (Cherry Trail) with correct model, per 1114 changes in its spec update. 1115 * cpuid.c: Change the (0,6),(5,14) Skylake descriptions to be more vague 1116 to reflect the larger set of existing processors now. 1117 * cpuid.c: Add actual information for the (0,6),(4,14) Skylake 1118 processors. 1119 * cpuid.c: Add actual information for the (0,6),(5,14) Broadwell-E 1120 processors. 1121 * cpuid.c: Add actual information for the (0,6),(4,15) Broadwell and 1122 Broadwell-EX processors. 1123 * cpuid.c: Added vague mentions of Goldmont (0,6),(5,12) and (0,6),(5,15) 1124 based on 325462 Table 35-1. 1125 * cpuid.c: Add Atom S1200 (Centerton) under (0,6),(3,6) thanks to an 1126 example provided by Jirka Hladky. 1127 * cpuid.c: Added Eden to the list of possible meanings of VIA 1128 (0,6),(6,13). An example provided by Daniel Wyatt shows that they 1129 sometimes use the simple Eden brand for this architecture. 1130 * cpuid.man: Added various new Intel documents used while making the 1131 above changes. 1132 * cpuid.c: Made -f - operate on stdin. 1133 1134Wed Jun 22 2016 Alan Cox <alan@lxorguk.ukuu.org.uk> 1135 * cpuid.c: Added out-of-memory checks to strregexp. 1136 1137Mon Oct 19 2015 Todd Allen <todd.allen@etallen.com> 1138 * Updated cpuid.man's list of information sources with new sources used 1139 in the 20151017 release (and one renamed source). 1140 1141Sat Oct 17 2015 Todd Allen <todd.allen@etallen.com> 1142 * Made new release. 1143 * cpuid.c: Updated synth decoding for Broadwell processors. 1144 * cpuid.c: Added 0xd leaf field. 1145 * cpuid.c: Updated and expanded 0x14 leaf fields. 1146 * cpuid.c: Added synth decoding for Intel Xeon E7 v2 (Ivy Bridge-EX). 1147 * cpuid.c: Added synth decoding for Intel Core i5/i7 (Skylake). 1148 * cpuid.c: Added vague synth decodings for a few more future processor 1149 models from Intel 64 and IA-32 Architectures Software Developer's 1150 Manual (325462), Table 35-1. 1151 1152Thu Oct 15 2015 Hubert Chrzaniuk <hubert.chrzaniuk@intel.com> 1153 * cpuid.c: Decode new leaf 2 cache descriptors: 6a, 6b, 6c, 6d. 1154 * cpuid.c: added synth decoding for Knights Landing. 1155 [NOTE FROM Todd Allen: There is no datasheet or spec update for 1156 Knights Landing yet, but Intel 64 and IA-32 Architectures Software 1157 Developer's Manual (325462), Table 35-1 mentions that it will have the 1158 family & model (0,6),(5,7). 1159 1160Sat Jun 6 2015 Todd Allen <todd.allen@etallen.com> 1161 * Made new release. 1162 * cpuid.man: Added 325462 manual. 1163 * cpuid.c: Added new & missing decodings for: 4/ecx, 6/eax, 7/ebx, 7/ecx. 1164 * cpuid.c: Overhauled handling of 0xd leaf, based on new and more 1165 extensive information in the Intel CPUID documentation, particularly 1166 on how to decide which leaves are valid. The approach functions 1167 correctly for the subset described in the AMD documentation, too. 1168 This overhaul includes information on the XSAVEC, XGETBV, and 1169 XSAVES/XRSTORS instructions. 1170 * cpuid.c: Renamed 0xf leaves to include "Monitoring". 1171 * cpuid.c: Added 0x10 leaves for QoS Enforcement. 1172 * cpuid.c: Added new leaf 2 cache meanings: 0x1d, 0x24, 0xa0, 0xc3. 1173 * cpuid.c: Added missing i7 synth decoding for (0,6),(3,14). 1174 * cpuid.c: Corrected Atom Z3000 model & stepping which were bafflingly 1175 wrong: (0,6)(3,5),1 -> (0,6)(3,7),8. 1176 * cpuid.c: Corrected other Bay Trail stepping names for Celeron/Pentium 1177 N and J series. 1178 * cpuid.man: Added references to a bunch of new Intel manuals. 1179 * cpuid.c: Added synth decoding for Intel Xeon Phi (Knights Corner). 1180 * cpuid.c: Added synth decoding for Intel Atom C2000 (Avoton). 1181 * cpuid.c: Added synth decoding for Intel Xeon E5-x600 (Haswell-EP). 1182 * cpuid.c: Added synth decoding for Intel Xeon E5-[48]800 (Haswell-EP). 1183 * cpuid.c: Added synth decoding for Intel Core M (Broadwell-Y). 1184 * cpuid.c: Added synth decoding for Intel Xeon D-1500 (Broadwell-DE). 1185 * cpuid.c: Added synth decoding for Intel i7-5000 Extreme (Haswell R2). 1186 * cpuid.c: Added synth decoding for Intel Atom Z8000 (Cherry Trail). 1187 * cpuid.c: Added synth decoding for Intel Pentium/Celeron N3000 1188 (Braswell). 1189 * cpuid.c: Added synth decoding for Intel i7 5th gen (Broadwell). 1190 * cpuid.c: Added synth decoding for Intel E3-1200 v4 (Broadwell). 1191 * cpuid.c: Added Xeon E5-4600 to synth decoding for other Sandy Bridge 1192 E5 processors (it was omitted accidentally). 1193 * cpuid.c: Added Pentium D 9xx Processor to synth decoding for Presler 1194 D0 (it was omitted accidentally). 1195 1196Fri Mar 21 2014 Todd Allen <todd.allen@etallen.com> 1197 * cpuid.c: Deal with 0-width PKG_width fields in print_apic_synth(), 1198 for CPUs where the SMT_width + CORE_width >= 8. This happens on 1199 Xeon Phi chips. 1200 1201Wed Feb 12 2014 Todd Allen <todd.allen@etallen.com> 1202 * cpuid.c: Added CLFLUSHOPT instruction field to leaf 7, ebx. 1203 * cpuid.c: Added Processor Frequency Information leaf (0x16). 1204 1205Tue Feb 11 2014 Todd Allen <todd.allen@etallen.com> 1206 * Makefile: Added src_tar rule. 1207 1208Tue Feb 11 2014 Todd Allen <todd.allen@etallen.com> 1209 * cpuid.c: Made changes to allow building and running on kFreeBSD. This 1210 started out as a patch from Andrey Rahmatullin, but I refactored it. 1211 The changes to disable the cpuid kernel support are protected by a 1212 USE_CPUID_MODULE definition. And there's an additional sanity check 1213 to reject -k in that case. The changes to use the library versions of 1214 sched_setaffinity are protected by USE_KERNEL_SCHED_SETAFFINITY. I 1215 continue to go straight to the kernel on linux, though. 1216 1217Tue Feb 11 2014 Todd Allen <todd.allen@etallen.com> 1218 * Makefile: Reorganized Andrey Rahmatullin's changes a bit and used 1219 them in my development build rules (make todd) too. 1220 1221Tue Feb 11 2014 Andrey Rahmatullin <wrar@wrar.name> 1222 * Makefile: Honor CPPFLAGS, CFLAGS and LDFLAGS from the environment. 1223 1224Mon Jan 27 2014 Todd Allen <todd.allen@etallen.com> 1225 * Makefile: Change to my development build rules (make todd) to use ld's 1226 --hash-style=both to avoid a SIGFPE when running on very old 32-bit 1227 systems. It has no effect on the tool for anyone else. 1228 1229Thu Jan 23 2014 Todd Allen <todd.allen@etallen.com> 1230 * Made new release. 1231 1232Thu Jan 23 2014 Todd Allen <todd.allen@etallen.com> 1233 * cpuid.c: Stop displaying raw hex for 0xc and 0xe leaves, because they 1234 are reserved and just contain zeroes. 1235 * cpuid.c: Fixed missing leaf 0xf subleaf 1 in do_real(). 1236 * cpuid.man: Added reference to Intel Architecture Instruction Set 1237 Extensions Programming Reference (319433). 1238 * cpuid.c: Added new feature flags from that document. 1239 1240Sun Jan 12 2014 Todd Allen <todd.allen@etallen.com> 1241 * Made new release. 1242 1243Sun Jan 12 2014 Todd Allen <todd.allen@etallen.com> 1244 * cpuid.c: Added Celeron B800 synth decoding. 1245 * cpuid.c: Added Pentium G3000 & Celeron G1800 synth decoding. 1246 * cpuid.c: Added 4th Gen Core family mobile processors synth decoding. 1247 * cpuid.c: Added information about E5 v2 processors (no longer just 1248 engineering samples) and related Ivy Bridge-EP processors. 1249 * cpuid.c: Added Bay Trail (Atom Z3000, etc.) processors synth decoding. 1250 1251Sun Jan 12 2014 Todd Allen <todd.allen@etallen.com> 1252 * cpuid.man: Added reference to Intel decoding from Intel 64 and IA-32 1253 Architectures Software Developer's Manual Volume 2A: Instruction Set 1254 Reference, A-M (253666). 1255 * cpuid.c: Added new Intel decodings from that document. 1256 1257Sun Jan 12 2014 Todd Allen <todd.allen@etallen.com> 1258 * cpuid.c: Added new (instruction supported synth) field to report on 1259 instruction support when knowledge of that is scattered across 1260 multiple CPUID leaves. PREFETCH/PREFETCHW is the weirdest example. 1261 * cpuid.c: Clarified the raw PREFETCH/PREFETCHW field in 80000001 edx 1262 leaf with the 3DNow! prefix, similar to the description in the AMD 1263 CPUID docs. Thanks to Chris Orgill for reporting these two issues. 1264 1265Fri Sep 27 2013 Todd Allen <todd.allen@etallen.com> 1266 * cpuid.c: Added missing break to decode_amd_model(), family (0,15), 1267 model (4,0), case 0x18. Thanks to David Binderman for reporting this. 1268 1269Mon Jun 10 2013 Todd Allen <todd.allen@etallen.com> 1270 * Made new release. 1271 1272Mon Jun 10 2013 Todd Allen <todd.allen@etallen.com> 1273 * cpuid.c: Added mention of Opteron 3200 (Zurich) chips, accidentally 1274 omitted from yesterday's updates. 1275 1276Sun Jun 9 2013 Todd Allen <todd.allen@etallen.com> 1277 * Made new release. 1278 1279Sun Jun 9 2013 Todd Allen <todd.allen@etallen.com> 1280 * cpuid.c: Updated 14h Model 00h-0Fh AMD model tables. 1281 * cpuid.c: Added synth decoding for Opteron x300 (Piledriver) chips. 1282 * cpuid.c: Added synth decoding for family 16h processors, tentatively 1283 identified as Steamroller. 1284 * cpuid.man: Added new AMD 15h Model 10h-1Fh, and AMD 16h Model 00h-0Fh 1285 manuals. 1286 1287Sat Jun 8 2013 Todd Allen <todd.allen@etallen.com> 1288 * cpuid.c: Added sanity check to 0xCxxxxxxx leaves to check for an 1289 unreasonably large indicated maximum leaf number. If found, further 1290 walk of them is halted. 1291 * cpuid.c: Skip 0x4xxxxxxx leaves if cpuid does not indicate that the 1292 environment is a guest. This was suggested by Steven Levine, although 1293 I implemented it differently. 1294 1295Sat Jun 8 2013 Todd Allen <todd.allen@etallen.com> 1296 * cpuid.c: Clarified some KVM hypervisor leaf feature flags that Eduardo 1297 Habkost pointed out. Added a couple new flags. 1298 1299Sat Jun 8 2013 Todd Allen <todd.allen@etallen.com> 1300 * cpuid.c: Extended Eduardo Habkost's stash separation to include the 1301 0x80000008 leaf, and the leaves that inform transmeta_info. 1302 1303Sat Jun 8 2013 Eduardo Habkost <ehabkost@raisama.net> 1304 * cpuid.c: This patch separates the code that changes fields in the 1305 'stash' struct from the code that prints that information. This way, 1306 the stash struct will get updated even when in raw mode, so other 1307 parts of the code can use that information. 1308 [NOTE FROM Todd Allen: It used to be that the stash was only set and 1309 used in cooked mode, but some uses dealing with the hypervisor snuck 1310 out and were used all the time. This new separation is only really 1311 necessary for the hypervisor fields, but it's good practice to do all 1312 the fields this way, so I'm accepting the patch as is.] 1313 1314Sat Jun 8 2013 Todd Allen <todd.allen@etallen.com> 1315 * cpuid.c: Added synth decoding for Celeron G400/G500. 1316 * cpuid.c: Added synth decoding for Cedarview B3. 1317 * cpuid.c: Added synth decoding for Ivy Bridge i3 processors. 1318 * cpuid.c: Added synth decoding for Ivy Bridge Pentium G1600/G2000/G2100. 1319 * cpuid.c: Added synth decoding for Ivy Bridge Pentium 1320 900/1000/2000/2100. 1321 * cpuid.c: Clarified that Ivy Bridge Xeon E3-1200 is actually E3-1200 v2. 1322 * cpuid.c: Added vague synth decoding for Haswell, but spec updates 1323 show no specific chips or steppings yet. 1324 * cpuid.c: Expanded A100/A110 synth decoding to include semi-official 1325 Pentium M (Crofton) processors in Apple TV boxes. 1326 * cpuid.c: Added Xeon E5-2600 v2 engineering sample. Perhaps this will 1327 be the final synth decoding for them, but for now it's just marked as 1328 an engineering sample. 1329 * cpuid.man: Added new Intel manuals. 1330 1331Fri Aug 24 2012 Todd Allen <todd.allen@etallen.com> 1332 * cpuid.c: Added sanity check to 0x4xxxxxxx leaves to check for an 1333 unrecognized hypervisor and an unreasonably large indicated maximum 1334 leaf number. If found, further walk of them is halted. 1335 1336Tue Aug 21 2012 Todd Allen <todd.allen@etallen.com> 1337 * cpuid.c: Cleaned up printf(name) statements that were admonished by 1338 clang. 1339 1340Fri Jun 1 2012 Todd Allen <todd.allen@etallen.com> 1341 * Made new release. 1342 1343Thu May 31 2012 Todd Allen <todd.allen@etallen.com> 1344 * cpuid.c: Updated CPUID feature flags. 1345 * cpuid.c: Updated CPUID function 7 to support sub-leaves (mostly for 1346 future functionality that might be added to them). 1347 * cpuid.c: Updated synth decoding for Intel Dothan C0 because some use 1348 65nm process now. 1349 * cpuid.c: Updated Intel EP80579 synth to mention 65nm process. 1350 * cpuid.c: Added synth decoding for Intel Atom E600 series. 1351 * cpuid.c: Updated synth decoding for Intel Sandy Bridge D2 to include J1 1352 and Q0, which have the same CPUID. 1353 * cpuid.c: Added synth decoding for Intel Atom D2000/N2000 (Cedarview). 1354 * cpuid.c: Added synth decoding for Intel Sandy Bridge-E. 1355 * cpuid.c: Added synth decoding for AMD Llano. 1356 * cpuid.c: Improved distinction between AMD Interlagos & Zambezi. 1357 * cpuid.c: Added synth decoding for RDC IAD 100. 1358 * cpuid.c: Fixed some formatting bugs for Transmeta-specific leaves. 1359 * cpuid.c: Added synth decoding for some of VIA's versions of WinChips. 1360 * cpuid.man: Added mentions of spec updates for several Atoms, i7 for 1361 LGA-2011, and Xeon E5; and AMD 12h family. 1362 1363Wed May 30 2012 Todd Allen <todd.allen@etallen.com> 1364 * cpuid.c: Fixed ancient bug in distinguishing Irwindale from Nocona 1365 (they differ only by L2 cache size). 1366 * cpuid.c: Added synth decoding for desktop and mobile Ivy Bridge. 1367 1368Sat Feb 25 2012 Todd Allen <todd.allen@etallen.com> 1369 * Made new release. 1370 * cpuid.c: Cleaned up hypervisor-specific leaves for KVM. 1371 * cpuid.man: Added mention of KVM cpuid documentation. 1372 1373Fri Feb 24 2012 Todd Allen <todd.allen@etallen.com> 1374 * cpuid.c: Added synth decoding for Intel Westmere-EX processors. 1375 * cpuid.c: Added synth decoding for AMD family 15h chips: AMD FX 1376 (Zambezi), Opteron 6200 (Interlagos), and Opteron 4200 (Valencia). 1377 * cpuid.c: Added synth decoding for AMD Z-Series and other Fusion 1378 chip ON-C0 steppings. 1379 * cpuid.c: Added synth decoding for Atom Z600 (Lincroft). 1380 * cpuid.c: Updated AMD model decoding for family 10h processors. 1381 * cpuid.man: Added mention of AMD family 14h and 15h documents, and 1382 Intel Westmere-EX & Lincroft documents. 1383 * cpuid.man: Removed obsolete limitation about 0x8000001b. 1384 * cpuid.c: Added support for hypervisor leaves (0x4000000 and after). 1385 Interpreted known generic leaves. Interpreted hypervisor-specific 1386 leaves for Xen (deduced from source, as no documentation on them 1387 exists). Interpreted hypervisor-specific leaves for KVM. Interpreted 1388 hypervisor-specific leaves for Microsoft. 1389 1390Tue Jan 3 2012 Todd Allen <todd.allen@etallen.com> 1391 * cpuid.c: Added synth decoding for Athlon 64 (Venice DH-E6) chips. 1392 1393Wed Nov 2 2011 Todd Allen <todd.allen@etallen.com> 1394 * cpuid.c: Added saw_4 and saw_b stash flags to deal with chips that 1395 report 0xc codes but still omit 0xb codes. This way, a maximum code 1396 of 0xc no longer implies the presence of 0xb codes for things like 1397 APIC decoding. 1398 1399Mon Mar 28 2011 Todd Allen <todd.allen@etallen.com> 1400 * cpuid.c: Added APIC synth decoding for AMD, deduced by analogy to Intel 1401 code and the multiprocessor synth logic. 1402 1403Mon Mar 7 2011 Todd Allen <todd.allen@etallen.com> 1404 * cpuid.c: Added some decoding for VIA 0xc0000002 codes, based on 1405 information from Juerg Haefliger. Very incomplete because VIA 1406 doesn't document their functions well. 1407 * cpuid.c: Fixed output of 0xc0000001 raw dump to conform to new style. 1408 1409Sat Mar 5 2011 Todd Allen <todd.allen@etallen.com> 1410 * Made new release. 1411 1412Fri Mar 4 2011 Todd Allen <todd.allen@etallen.com> 1413 * cpuid.c,cpuid.man: Added Celeron T1000 series, previously missing. 1414 * cpuid.c,cpuid.man: Added Celeron Mobile P4000, U3000 series. 1415 * cpuid.c,cpuid.man: Added current Sandy Bridge processors. 1416 1417Thu Mar 3 2011 Todd Allen <todd.allen@etallen.com> 1418 * cpuid.c: Added detection of PCIDs & TSC-DEADLINE. 1419 * cpuid.c: Verified Mike Stroyan CPUID 2 cache meanings from Intel CPUID 1420 document (241618-037). Added 0x76 meaning. 1421 * cpuid.c: Added various new flags from Intel 241618-037. 1422 * cpuid.c,cpuid.man: Added AMD family 14h processors. 1423 * cpuid.c,cpuid.man: Updated Intel process id table, mostly as just 1424 generalizations. 1425 1426Tue Nov 9 2010 Todd Allen <todd.allen@etallen.com> 1427 * cpuid.c: Update the usage() screen, since some of its -i and -1 1428 comments are incorrect now. 1429 1430Mon Oct 4 2010 Todd Allen <todd.allen@etallen.com> 1431 * cpuid.c, cpuid.man: Added AMD Geode LX. 1432 * cpuid.c: Added NSC Geode GX2 and AMD Geode GX. 1433 * cpuid.c, cpuid.man: Added AMD Geode NX. 1434 1435Sat Oct 2 2010 Todd Allen <todd.allen@etallen.com> 1436 * Made new release. 1437 * cpuid.c,cpuid.man: Added Intel Atom N500. 1438 1439Thu Sep 30 2010 Todd Allen <todd.allen@etallen.com> 1440 * cpuid.c,cpuid.man: Added support for Intel Tolapai (SoC). 1441 * cpuid.c,cpuid.man: Added support for Intel Clarkdale chips from 1442 specification update 323179. 1443 * cpuid.c: Generalized decode_amd_model by adding full brand tables for 1444 AMD chips. If a BIOS doesn't recognize a chip it writes 1445 "model unknown" into its brand string via MSR's. 1446 decode_override_brand detects that and uses the decode_amd_model brand 1447 to differentiate CPUs. 1448 * cpuid.c: Corrected 80000001/ebx PkgType, BrandId, and str1 bit fields. 1449 * cpuid.c: Corrected problems with brand field decoding because its bit 1450 field with differs from architecture to architecture. 1451 * cpuid.c: decode_amd_model: the partialmodel decrement special case 1452 applies only to XF=1,F=15; and not to XF=2,F=15. 1453 1454Mon Sep 27 2010 Todd Allen <todd.allen@etallen.com> 1455 * cpuid.c: Added support for NSC/AMD Geode GX1. 1456 1457Wed Sep 8 2010 Todd Allen <todd.allen@etallen.com> 1458 * cpuid.c: Corrected the Transmeta processor revisions, which should've 1459 been in hex instead of octal. 1460 1461Thu Sep 2 2010 Todd Allen <todd.allen@etallen.com> 1462 * cpuid.c: Added a couple vague steppings for Transmeta Efficeon TM8000 1463 processors. Updated some transmeta bitfields. This is all done 1464 blind, as I have no examples of these chips, little documentation, and 1465 the company is long defunct. 1466 1467Thu Sep 2 2010 Todd Allen <todd.allen@etallen.com> 1468 * Made new release. 1469 * cpuid.c: Fixed a few header strings that had incorrect function hex 1470 codes or registers. 1471 1472Wed Sep 1 2010 Todd Allen <todd.allen@etallen.com> 1473 * Made new release. 1474 * cpuid.c: Fixed buffer size in do_file() to be able to read new 1475 raw dumps with ecx information. It needed a couple more characters. 1476 * cpuid.c: Added Celeron M (Yonah D0) & Celeron M (Merom-L1 A1) synth 1477 entries. 1478 * cpuid.c: added Xeon Processor LV (Sossaman D0). 1479 * cpuid.c: Update Itanium chips in the synth tables. Sadly, this all 1480 still is being done blind, as I have no access to any Itanium chips. 1481 * cpuid.c: Wrote an x86_64 counterpart to the assembly code for 1482 bits_needed(). 1483 * Makefile, cpuid.proto.spec: Changed to support building for both i386 1484 and x86_64. 1485 1486Tue Aug 31 2010 Todd Allen <todd.allen@etallen.com> 1487 * Made new release. 1488 * cpuid.c: Rearranged synth rules and substantially simplified query 1489 macros into something like the form I was hoping for when I started 1490 this redesign. 1491 * cpuid.c: Added changes from the new AMD CPUID document that claims to 1492 have been released in September 2010! 1493 * cpuid.c: Changed raw dump to include %ecx values to accomodate CPUID 1494 functions with gaps in the useful %ecx range (e.g. 0xd). The file 1495 parser accepts either the old or new forms. 1496 * Makefile, cpuid.proto.spec: Updated build scheme for my current 1497 systems. 1498 * LICENSE: Changed to a GPL license. 1499 1500Mon Aug 30 2010 Todd Allen <todd.allen@etallen.com> 1501 * cpuid.c: Semi-mechanically eliminated the codes used to 1502 disambiguate in the synth string and replaced them with queries, 1503 which I think will be more general-purpose and will allow me to 1504 eliminate a lot of the problem with codes appropriate for one 1505 model being a problem for subsequent models (e.g. the Core Solo 1506 vs. Core Duo distinction). There still are general-purpose 1507 queries like there were general-purpose codes, but the 1508 special-case queries will only matter for those families that 1509 care about them. This does mean that it's possible for multiple 1510 queries to register as true, so I have to be more careful with 1511 the order of chips in the synth tables. 1512 1513Fri Aug 27 2010 Todd Allen <todd.allen@etallen.com> 1514 * Tested on a variety of CPUs. 1515 * cpuid.c: Corrected Mobile Turion checking in decode_brand. 1516 * cpuid.c: Added synth entries for 6/15/4 pre-production 1517 Conroe B0/Woodcrest B0. 1518 * cpuid.c: Added synth entries for Santa Rosa F3 stepping 1519 (undocumented). 1520 * cpuid.c: Fixed synth entries for Brisbane, Toledo, and Windsor to 1521 expect code DA (for dual-core Athlons). 1522 * cpuid.c: Generalized the check for Intel Extreme Edition chips. 1523 * cpuid.c: Added synth entries Core 2 Quad (Conroe) chips. 1524 * cpuid.c: Added synth entry for VIA 6/13/0 chip. Unfortunately, there 1525 is no documentation and very little anecdotal evidence of this chip, 1526 so the description is vague. 1527 * cpuid.c: Added addition CPUID function 2 cache codes from Mike 1528 Stroyan. 1529 * cpuid.c: Fixed some cut&paste errors that had EAX where it should 1530 have been EBX, as reported by Mike Stroyan 1531 * cpuid.c: Added very short synth table for SiS chips. I found no 1532 documentation on these, so I just have the one case. 1533 * cpuid.c: Fixed the (synth) strings for oddball chips, which suffered 1534 from a cut&paste error. 1535 * cpuid.c: Simplified some of the fallback strings that had grown 1536 ridiculously long. 1537 1538Thu Aug 26 2010 Todd Allen <todd.allen@etallen.com> 1539 * Tested on a variety of CPUs. 1540 * cpuid.c: Added more logic for Woodcrest pre-production chips. 1541 * cpuid.c: Corrected synth logic for VIA Antaur chips. 1542 * cpuid.c: Added synth for plain vanilla Thoroughbred Athlon. 1543 1544Wed Aug 25 2010 Todd Allen <todd.allen@etallen.com> 1545 * Tested on a variety of CPUs. 1546 * cpuid.c: Fixed a couple bugs with decoding processor numbers in 1547 print_synth_amd_model. 1548 1549Tue Aug 24 2010 Todd Allen <todd.allen@etallen.com> 1550 * cpuid.c: Further changes to mp_synth decoding, including tracking 1551 of the decoding method used (there are around 4 major approaches, 1552 depending on how you count). 1553 * cpuid.c: Added apic_synth decoding to find the appropriate field 1554 widths and decode the process local APIC physical ID. This is useful 1555 in its own right, but also helps convince me that many Intel chips 1556 really do claim to have hyperthreads even though they don't. 1557 * cpuid.c: Added support for direct instruction (-i) functionality to 1558 report on all CPUs by calling sched_setaffinity to reschedule the 1559 process on each CPU. This is now the default behavior for -i, but 1560 it can be overridden with the -1 option. 1561 * cpuid.c: added Barcelona B1 (undocumented chip) synth decoding. 1562 1563Mon Aug 23 2010 Todd Allen <todd.allen@etallen.com> 1564 * cpuid.c: Made real_get pass the requested ecx values even when 1565 using -k. Modern linux kernel expect the ecx values in the upper 1566 32 bits of the file offset (i.e. lseek64). 1567 * cpuid.c: Worked out a fallback for determining mp_synth information 1568 for Intel chips which lack CPUID function 4. 1569 * cpuid.c: Added mechanism for determining mp_synth information from 1570 CPUID function 11 information if it's available (because if it's 1571 present on Intel chips, it's the only reliable way; the older 1572 mechanisms return gibberish). 1573 1574Fri Aug 20 2010 Todd Allen <todd.allen@etallen.com> 1575 * cpuid.c, cpuid.man: Added to synth even more Nehalem chips. 1576 * cpuid.c: Added 6/15 model for VIA Nano, but there's very little 1577 detailed information on this chip, so that's it. 1578 * cpuid.c: Corrected some AMD codename confusion from 2006: 1579 Dublin->ClawHammer/Odessa, Sonora->Dublin, 1580 Palermo(mobile)->Georgetown/Sonora, Lancaster->Lancaster/Richmond, 1581 Richmond->Taylor/Trinidad. 1582 * cpuid.c: Overhauled the AMD model dumping code to understand new 1583 families. 1584 * cpuid.c: Tweaked decode_mp_synth to use ApicIdCoreIdSize, per AMD's 1585 CPUID recommendations. 1586 1587Thu Aug 19 2010 Todd Allen <todd.allen@etallen.com> 1588 * cpuid.c, cpuid.man: Updated synth tables for Intel Xeons. 1589 * cpuid.c: Removed all the "How to distinguish" comments, since 1590 it seems to be very common for Intel to have indistinguishable 1591 processors nowadays (the old cache-checking tricks are unreliable 1592 now). 1593 * cpuid.c, cpuid.man: Added to synth additional Nehalem chips as I'm 1594 able to hunt them down. 1595 1596Wed Aug 18 2010 Todd Allen <todd.allen@etallen.com> 1597 * cpuid.c, cpuid.man: Updated synth tables for Intel Core 2, Atom, 1598 Celeron, and Pentium chips based on the same cores. 1599 1600Tue Aug 17 2010 Todd Allen <todd.allen@etallen.com> 1601 * cpuid.c, cpuid.man: Updated synth tables for AMD family 10h (K10) 1602 and family 11h processors. 1603 * cpuid.c: simplified print_x_synth_amd by pruning its table down to 1604 just the three families that differ from normal 1/eax simple synth, 1605 and falling back on 1/eax simple synth otherwise. 1606 1607Mon Aug 16 2010 Todd Allen <todd.allen@etallen.com> 1608 * cpuid.c: Added new steppings to synth tables using latest spec 1609 updates for all AMD processor families already in them. 1610 * cpuid.c, cpuid.man: Updated synth tables for AMD family 0Fh (K8) 1611 processors. 1612 1613Fri Aug 13 2010 Todd Allen <todd.allen@etallen.com> 1614 * cpuid.c: Updated raw data dump based on latest CPUID documentation 1615 from Intel & AMD. 1616 * cpuid.c: Fixed dump of function 4 to iterate over all caches. 1617 1618Thu Aug 12 2010 Todd Allen <todd.allen@etallen.com> 1619 * cpuid.c: Reorganized synth tables to always use extended family 1620 and extended model numbers since they are so prevalent on modern 1621 chips. 1622 * cpuid.c: Added new steppings to synth tables using latest spec 1623 updates for all Intel processor families already in them. 1624 1625Sun Nov 26 2006 Todd Allen <todd.allen@etallen.com> 1626 * cpuid.c: Recognize Intel Core 2 Extreme Edition from brand string. 1627 Thanks to Tony Freitas for explaining that Ennnn means desktop while 1628 Xnnnn means Extreme Edition for those processors. 1629 1630Wed Nov 22 2006 Todd Allen <todd.allen@etallen.com> 1631 * cpuid.c: Recognize Itanium2 Montecito C2. 1632 * cpuid.c: Recognize Intel Core 2 Duo Mobile (Conroe B2). 1633 * cpuid.c: Recognize Intel Quad-Core Xeon Processor 5300 (Woodcrest B3) 1634 and Intel Core 2 Extreme Quad-Core Processor QX6700 (Woodcrest B3). 1635 * cpuid.c: Recognize Intel Celeron D Processor 36x (Cedar Mill D0). 1636 * cpuid.c: Distinguish Core 2 Duo from Core 2 Extreme Edition based on 1637 presence or absence of hyperthreading. Thanks to Tony Seacow for 1638 providing output for numerous processors and the advice about 1639 hyperthreading. 1640 1641Thu Nov 2 2006 Todd Allen <todd.allen@etallen.com> 1642 * cpuid.c: Changed "number of logical CPU cores - 1" to "number of CPU 1643 cores - 1". 1644 1645Sun Sep 17 2006 Todd Allen <todd.allen@etallen.com> 1646 * Made new release. 1647 * cpuid.c: Made the cpuid instruction (-i, --inst options) the default. 1648 * cpuid.c: Added -k, --kernel option to cause the kernel module to be 1649 used. 1650 * cpuid.c: Removed confusing CPU number from output when using 1651 the cpuid instruction. 1652 * cpuid.man: Updated with new options. 1653 * cpuid.c, Makefile: Changed i386 _llseek kludge to workaround 1654 offsets >= 0x80000000. Now using -D_FILE_OFFSET_BITS=64 in the 1655 Makefile instead. This should allow the i386 cpuid to work on 1656 an x86_64 system. 1657 * cpuid.c: Added knowledge of CPU modules to synthesized field: Tulsa, 1658 Woodcrest B1 (pre-production) 1659 * cpuid.c: In synthesized model field, properly distinguish between 1660 Intel Pentium D Processor 8x0 and Intel Pentium Extreme Edition 1661 Processor 840 (both Smithfields). 1662 * cpuid.man: Added mention of new 7100 series spec updates. 1663 * cpuid.spec: Changed Copyright to License. 1664 1665Thu Aug 23 2006 Todd Allen <todd.allen@etallen.com> 1666 * cpuid.c: Removed unnecessary one_cpu argument from do_file. 1667 * cpuid.c: Added -v option to display version number. 1668 1669Wed Aug 23 2006 Todd Allen <todd.allen@etallen.com> 1670 * Made new release. 1671 1672Tue Aug 22 2006 Todd Allen <todd.allen@etallen.com> 1673 * cpuid.c, cpuid.man: Added -i option to use the CPUID instruction 1674 directly instead of the CPUID kernel module. 1675 * cpuid.c: Change Pentium Processor 9x0 to 9xx because of 9x5 1676 processors. 1677 * cpuid.man: Updated information about determining synthesized model 1678 information, and added information about determining synthesized 1679 multiprocessor information. 1680 1681Mon Aug 7 2006 Todd Allen <todd.allen@etallen.com> 1682 * cpuid.proto.spec: Change URL to cpuid-specific page. 1683 1684Sun Aug 6 2006 Todd Allen <todd.allen@etallen.com> 1685 * Made new release. 1686 1687Sat Aug 5 2006 Todd Allen <todd.allen@etallen.com> 1688 * cpuid.c: Added support for differentiating Core 2 Duo CPUs from Xeon 1689 5100 CPUs based on the brand string. 1690 * cpuid.c: Clarified that CPUID 4 ECX contains one less than the 1691 number of sets. 1692 * cpuid.c: Added support for CPUID 5 ecx & edx. 1693 * cpuid.c: Added support for CPUID 6 ecx. 1694 * cpuid.c: Added support for CPUID 0xa eax & ebx. 1695 * cpuid.c: Made CPUID functions 7, 8, and 9 reserved (i.e. say nothing 1696 until and unless they are defined). 1697 * cpuid.c: Corrected CPUID 1 ecx xTPR disabnle. 1698 1699Wed Aug 2 2006 Todd Allen <todd.allen@etallen.com> 1700 * cpuid.c: Corrected bug with Core 2 Duo recognition. 1701 * cpuid.c: Distinguish between Allendale and Conroe cores based on 1702 L2 cache size. 1703 * cpuid.c: Added VIA C7 & C7-M names to Esther WinChip C5J core CPUs. 1704 * cpuid.man: Mention wikipedia pages for CPUs. 1705 1706Tue Aug 1 2006 Todd Allen <todd.allen@etallen.com> 1707 * cpuid.c: On help screen, clarified that -f option reads output from 1708 -r option. 1709 * cpuid.proto.spec: Used %{} macros for external command invocations. 1710 1711Mon Jul 31 2006 Todd Allen <todd.allen@etallen.com> 1712 * Makefile: Removed install -o 0 -g 0 options. For installations 1713 from the tarball, the user will have to be root anyway. And for 1714 rpm, the %defattr() attribute in the spec is handling this more 1715 cleanly. Finally, those options are causing some non-root 1716 installations to have to be done by the root user, which is 1717 undesirable. 1718 * cpuid.c: Improved identification for VIA C3 (Samuel WinChip C5A core). 1719 * cpuid.c: Loosened up check for "Mobile AMD Athlon(tm) XP" by 1720 removing "-M" suffix. 1721 * cpuid.c: Recognize mobile Athlon XP (Thoroughbred). 1722 1723Sun Jul 30 2006 Todd Allen <todd.allen@etallen.com> 1724 * Made new release. 1725 * cpuid.c: Fixed "deterministic cache parameters (4)", so that its 1726 children aren't staggered. 1727 * cpuid.c: Corrected Venice and Palermo processors with DH-E3 and 1728 DH-E6 steppings that had been reported as Toledo processors 1729 incorrectly. 1730 * cpuid.c: Corrected codename for the Athlon Thoroughbred's Duron 1731 counterpart: Applebred. 1732 * cpuid.c: Added code to distinguish Athlon XP Thortons from Bartons, 1733 based on L2 cache size. 1734 * cpuid.c: Added code to distinguish Athlon 64 X2 Manchester E6 from 1735 Athlon 64 X2 Toledo. 1736 * cpuid.c: Added Celeron Yonah C0. 1737 * cpuid.c: Added Core Yonah D0. 1738 * cpuid.c: Added Xeon Nocona R0 / Irwindale R0 stepping. 1739 * cpuid.c: Added Pentium 4 Cedar Mill C1, Pentium D Presler C1, and 1740 Xeon Dempsey C1. 1741 * cpuid.c: Added Xeon Woodcrest B2. 1742 * cpuid.c: Added Core 2 Conroe B1 & B2 & Core 2 Extreme Processor B1 & 1743 B2. 1744 * cpuid.c: Updated Itanium2 processors. 1745 * cpuid.man: Added Intel specification updates for new CPUs. 1746 1747Wed Jul 26 2006 Todd Allen <todd.allen@etallen.com> 1748 * cpuid.c: In decode_brand, added check for "Athlon(TM) XP", equivalent 1749 to "Athlon(tm) XP". 1750 * cpuid.c: Fixed "80000002" typo in print_80860002_eax(). 1751 1752Mon Jul 24 2006 Todd Allen <todd.allen@etallen.com> 1753 * cpuid.c: Distinguish properly between Core Solo, Core Duo, and 1754 Xeon Processor LV. Reorganized multi-processor decoding to 1755 support that. 1756 1757Sun Jul 23 2006 Todd Allen <todd.allen@etallen.com> 1758 * cpuid.c: Fixed emission of raw values for cpuid code 2. 1759 * cpuid.c: Added -f file option to read raw hexadecimal input from a 1760 file and parse it instead of executing the cpuid instruction, and 1761 code reorganization to support this. 1762 1763Mon May 22 2006 Todd Allen <todd.allen@etallen.com> 1764 * cpuid.c: Fixed "unrecogninzed" typo in error. 1765 1766Fri Apr 7 2006 Todd Allen <todd.allen@etallen.com> 1767 * cpuid.proto.spec: Added %defattr so that the files in the rpm's are 1768 owned by "root" and not "todd". (Why did no one scream bloody murder 1769 about this before?) 1770 1771Mon Apr 3 2006 Todd Allen <todd.allen@etallen.com> 1772 * Made new release. 1773 * cpuid.c: Added code to distinguish between the two different Dual-Core 1774 Xeon (Paxville A0) and Dual-Core Xeon Processor 7000 (Paxville A0). 1775 Empirically, the significant differences are the VMX flag and the 1776 "execution disable" flag. The VMX flag is in an Intel-defined 1777 CPUID function, so it's used. Thanks to Jason Nicholls for providing 1778 the Dual-Core Xeon (Paxville A0) output that made this possible. 1779 * cpuid.c: Added detection for Xeon Processor LV (Sossaman C0). 1780 1781Mon Mar 13 2006 Todd Allen <todd.allen@etallen.com> 1782 * Made new release. 1783 * cpuid.c: Fixed code that distinguished processors based on 1784 presence or absence of L3 cache. Some of the cache codes weren't 1785 being recognized as L3 cache. 1786 1787Sun Feb 26 2006 Todd Allen <todd.allen@etallen.com> 1788 * Made new release. 1789 1790Wed Feb 22 2006 Todd Allen <todd.allen@etallen.com> 1791 * cpuid.c: Added VMX: virtual machine extensions to CPUID function 1, 1792 register ecx. 1793 * cpuid.c: Added SVM LBR virtualization to CPUID function 8000000a, 1794 register edx. 1795 * cpuid.c: Fixed cut & paste header error in print_8000000a_eax. 1796 1797Tue Feb 21 2006 Todd Allen <todd.allen@etallen.com> 1798 * cpuid.c: Renamed "hyper-threading technology" field to 1799 "hyper-threading / multi-core supported" to eliminate some confusing 1800 situations, such as Northwood chips which nominally support hyper- 1801 threading, but where it is disabled in the chip; or where hyper- 1802 threading is disabled in the BIOS; or AMD multi-core chips, which 1803 indicate TRUE here, but all of which lack hyper-threading at present. 1804 * cpuid.c: Updated family 15 description, which had grown very stale. 1805 * cpuid.c: Generalized Intel Pentium D Processor 900 to 9x0. 1806 * cpuid.c: Added Processor Number info to Smithfield processors. 1807 1808Wed Feb 8 2006 Todd Allen <todd.allen@etallen.com> 1809 * Made new release. 1810 * cpuid.c: Use defined(i386) instead of __LONG_MAX__ to determine 1811 whether or not it's necessary to use _llseek(). Fixes handling of 1812 functions >= 2**31 on some build systems, like the one I used to 1813 build the binary rpm. (D'oh!) And also indirectly affects the 1814 (synth) field. 1815 * cpuid.c: Fix a busted error check in read_reg() that caused it to 1816 return success if the read() failed and quiet was true. 1817 * LICENSE: Created LICENSE file (using content straight out of the 1818 man page). 1819 1820Tue Feb 7 2006 Todd Allen <todd.allen@etallen.com> 1821 * Made new release. 1822 * cpuid.c: Correctly distinguish Egypt/Italy processors. 1823 * cpuid.c: Fixed minor problems in error checking in open_file(). 1824 * cpuid.spec: Fixed bad Packager field. 1825 * cpuid.spec: Include ChangeLog. 1826 * cpuid.man: Added -r/--raw description. 1827 * cpuid.man: Clarified info used for (synth) field. 1828 * cpuid.man: Fixed version number & date. 1829 * Makefile: Reworked to make it easy for people other than me to build 1830 and install. 1831 * cpuid.spec: Used new Makefile organization 1832 * Makefile: Fixed production of spec file so that it's possible to 1833 rebuild with the srpm without having to specify %version and 1834 %release. 1835 1836Mon Feb 6 2006 Todd Allen <todd.allen@etallen.com> 1837 * Initial public release. 1838