1 /** @file 2 3 This file contains the definination for host controller register operation routines. 4 5 Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR> 6 SPDX-License-Identifier: BSD-2-Clause-Patent 7 8 **/ 9 10 #ifndef _EFI_EHCI_REG_H_ 11 #define _EFI_EHCI_REG_H_ 12 13 // 14 // EHCI register offset 15 // 16 17 18 // 19 // Capability register offset 20 // 21 #define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset 22 #define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h 23 #define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset 24 25 // 26 // Capability register bit definition 27 // 28 #define HCSP_NPORTS 0x0F // Number of root hub port 29 #define HCSP_PPC 0x10 // Port Power Control 30 #define HCCP_64BIT 0x01 // 64-bit addressing capability 31 32 // 33 // Operational register offset 34 // 35 #define EHC_USBCMD_OFFSET 0x0 // USB command register offset 36 #define EHC_USBSTS_OFFSET 0x04 // Statue register offset 37 #define EHC_USBINTR_OFFSET 0x08 // USB interrutp offset 38 #define EHC_FRINDEX_OFFSET 0x0C // Frame index offset 39 #define EHC_CTRLDSSEG_OFFSET 0x10 // Control data structure segment offset 40 #define EHC_FRAME_BASE_OFFSET 0x14 // Frame list base address offset 41 #define EHC_ASYNC_HEAD_OFFSET 0x18 // Next asynchronous list address offset 42 #define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset 43 #define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset 44 45 #define EHC_FRAME_LEN 1024 46 47 // 48 // Register bit definition 49 // 50 #define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC 51 52 #define USBCMD_RUN 0x01 // Run/stop 53 #define USBCMD_RESET 0x02 // Start the host controller reset 54 #define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule 55 #define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule 56 #define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell 57 58 #define USBSTS_IAA 0x20 // Interrupt on async advance 59 #define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status 60 #define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status 61 #define USBSTS_HALT 0x1000 // Host controller halted 62 #define USBSTS_SYS_ERROR 0x10 // Host system error 63 #define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC 64 // (write clean) bits in USBSTS register 65 66 #define PORTSC_CONN 0x01 // Current Connect Status 67 #define PORTSC_CONN_CHANGE 0x02 // Connect Status Change 68 #define PORTSC_ENABLED 0x04 // Port Enable / Disable 69 #define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change 70 #define PORTSC_OVERCUR 0x10 // Over current Active 71 #define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change 72 #define PORSTSC_RESUME 0x40 // Force Port Resume 73 #define PORTSC_SUSPEND 0x80 // Port Suspend State 74 #define PORTSC_RESET 0x100 // Port Reset 75 #define PORTSC_LINESTATE_K 0x400 // Line Status K-state 76 #define PORTSC_LINESTATE_J 0x800 // Line Status J-state 77 #define PORTSC_POWER 0x1000 // Port Power 78 #define PORTSC_OWNER 0x2000 // Port Owner 79 #define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits, 80 // they are WC (write clean) 81 // 82 // PCI Configuration Registers 83 // 84 #define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10 85 86 // 87 // Debug port capability id 88 // 89 #define EHC_DEBUG_PORT_CAP_ID 0x0A 90 91 #define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0) 92 93 #define EHC_ADDR(High, QhHw32) \ 94 ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0))) 95 96 #define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80) 97 98 // 99 // Structure to map the hardware port states to the 100 // UEFI's port states. 101 // 102 typedef struct { 103 UINT16 HwState; 104 UINT16 UefiState; 105 } USB_PORT_STATE_MAP; 106 107 // 108 // Ehci Data and Ctrl Structures 109 // 110 #pragma pack(1) 111 typedef struct { 112 UINT8 ProgInterface; 113 UINT8 SubClassCode; 114 UINT8 BaseCode; 115 } USB_CLASSC; 116 #pragma pack() 117 118 /** 119 Read EHCI capability register. 120 121 @param Ehc The EHCI device. 122 @param Offset Capability register address. 123 124 @return The register content. 125 126 **/ 127 UINT32 128 EhcReadCapRegister ( 129 IN USB2_HC_DEV *Ehc, 130 IN UINT32 Offset 131 ); 132 133 /** 134 Check whether the host controller has an in-use debug port. 135 136 @param[in] Ehc The Enhanced Host Controller to query. 137 138 @param[in] PortNumber If PortNumber is not NULL, then query whether 139 PortNumber is an in-use debug port on Ehc. (PortNumber 140 is taken in UEFI notation, i.e., zero-based.) 141 Otherwise, query whether Ehc has any in-use debug 142 port. 143 144 @retval TRUE PortNumber is an in-use debug port on Ehc (if PortNumber is 145 not NULL), or some port on Ehc is an in-use debug port 146 (otherwise). 147 148 @retval FALSE PortNumber is not an in-use debug port on Ehc (if PortNumber 149 is not NULL), or no port on Ehc is an in-use debug port 150 (otherwise). 151 **/ 152 BOOLEAN 153 EhcIsDebugPortInUse ( 154 IN CONST USB2_HC_DEV *Ehc, 155 IN CONST UINT8 *PortNumber OPTIONAL 156 ); 157 158 /** 159 Read EHCI Operation register. 160 161 @param Ehc The EHCI device. 162 @param Offset The operation register offset. 163 164 @return The register content. 165 166 **/ 167 UINT32 168 EhcReadOpReg ( 169 IN USB2_HC_DEV *Ehc, 170 IN UINT32 Offset 171 ); 172 173 174 /** 175 Write the data to the EHCI operation register. 176 177 @param Ehc The EHCI device. 178 @param Offset EHCI operation register offset. 179 @param Data The data to write. 180 181 **/ 182 VOID 183 EhcWriteOpReg ( 184 IN USB2_HC_DEV *Ehc, 185 IN UINT32 Offset, 186 IN UINT32 Data 187 ); 188 189 /** 190 Set one bit of the operational register while keeping other bits. 191 192 @param Ehc The EHCI device. 193 @param Offset The offset of the operational register. 194 @param Bit The bit mask of the register to set. 195 196 **/ 197 VOID 198 EhcSetOpRegBit ( 199 IN USB2_HC_DEV *Ehc, 200 IN UINT32 Offset, 201 IN UINT32 Bit 202 ); 203 204 /** 205 Clear one bit of the operational register while keeping other bits. 206 207 @param Ehc The EHCI device. 208 @param Offset The offset of the operational register. 209 @param Bit The bit mask of the register to clear. 210 211 **/ 212 VOID 213 EhcClearOpRegBit ( 214 IN USB2_HC_DEV *Ehc, 215 IN UINT32 Offset, 216 IN UINT32 Bit 217 ); 218 219 /** 220 Add support for UEFI Over Legacy (UoL) feature, stop 221 the legacy USB SMI support. 222 223 @param Ehc The EHCI device. 224 225 **/ 226 VOID 227 EhcClearLegacySupport ( 228 IN USB2_HC_DEV *Ehc 229 ); 230 231 232 233 /** 234 Set door bell and wait it to be ACKed by host controller. 235 This function is used to synchronize with the hardware. 236 237 @param Ehc The EHCI device. 238 @param Timeout The time to wait before abort (in millisecond, ms). 239 240 @retval EFI_SUCCESS Synchronized with the hardware. 241 @retval EFI_TIMEOUT Time out happened while waiting door bell to set. 242 243 **/ 244 EFI_STATUS 245 EhcSetAndWaitDoorBell ( 246 IN USB2_HC_DEV *Ehc, 247 IN UINT32 Timeout 248 ); 249 250 251 /** 252 Clear all the interrutp status bits, these bits are Write-Clean. 253 254 @param Ehc The EHCI device. 255 256 **/ 257 VOID 258 EhcAckAllInterrupt ( 259 IN USB2_HC_DEV *Ehc 260 ); 261 262 263 264 /** 265 Whether Ehc is halted. 266 267 @param Ehc The EHCI device. 268 269 @retval TRUE The controller is halted. 270 @retval FALSE It isn't halted. 271 272 **/ 273 BOOLEAN 274 EhcIsHalt ( 275 IN USB2_HC_DEV *Ehc 276 ); 277 278 279 /** 280 Whether system error occurred. 281 282 @param Ehc The EHCI device. 283 284 @retval TRUE System error happened. 285 @retval FALSE No system error. 286 287 **/ 288 BOOLEAN 289 EhcIsSysError ( 290 IN USB2_HC_DEV *Ehc 291 ); 292 293 294 /** 295 Reset the host controller. 296 297 @param Ehc The EHCI device. 298 @param Timeout Time to wait before abort (in millisecond, ms). 299 300 @retval EFI_SUCCESS The host controller is reset. 301 @return Others Failed to reset the host. 302 303 **/ 304 EFI_STATUS 305 EhcResetHC ( 306 IN USB2_HC_DEV *Ehc, 307 IN UINT32 Timeout 308 ); 309 310 311 /** 312 Halt the host controller. 313 314 @param Ehc The EHCI device. 315 @param Timeout Time to wait before abort. 316 317 @return EFI_SUCCESS The EHCI is halt. 318 @return EFI_TIMEOUT Failed to halt the controller before Timeout. 319 320 **/ 321 EFI_STATUS 322 EhcHaltHC ( 323 IN USB2_HC_DEV *Ehc, 324 IN UINT32 Timeout 325 ); 326 327 328 /** 329 Set the EHCI to run. 330 331 @param Ehc The EHCI device. 332 @param Timeout Time to wait before abort. 333 334 @return EFI_SUCCESS The EHCI is running. 335 @return Others Failed to set the EHCI to run. 336 337 **/ 338 EFI_STATUS 339 EhcRunHC ( 340 IN USB2_HC_DEV *Ehc, 341 IN UINT32 Timeout 342 ); 343 344 345 346 /** 347 Initialize the HC hardware. 348 EHCI spec lists the five things to do to initialize the hardware: 349 1. Program CTRLDSSEGMENT 350 2. Set USBINTR to enable interrupts 351 3. Set periodic list base 352 4. Set USBCMD, interrupt threshold, frame list size etc 353 5. Write 1 to CONFIGFLAG to route all ports to EHCI 354 355 @param Ehc The EHCI device. 356 357 @return EFI_SUCCESS The EHCI has come out of halt state. 358 @return EFI_TIMEOUT Time out happened. 359 360 **/ 361 EFI_STATUS 362 EhcInitHC ( 363 IN USB2_HC_DEV *Ehc 364 ); 365 366 #endif 367