1/** @file 2 This file contains the SystemAgent PCI Configuration space 3 definition. 4 It defines various System Agent PCI Configuration Space registers 5 which will be used to dynamically produce all resources in the Host Bus. 6 7 Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> 8 SPDX-License-Identifier: BSD-2-Clause-Patent 9**/ 10 11// 12// Define various System Agent (SA) PCI Configuration Space 13// registers which will be used to dynamically produce all 14// resources in the Host Bus _CRS. 15// 16OperationRegion (HBUS, PCI_Config, 0x00, 0x100) 17Field (HBUS, DWordAcc, NoLock, Preserve) 18{ 19 Offset(0x40), // EPBAR (0:0:0:40) 20 EPEN, 1, // Enable 21 , 11, 22 EPBR, 20, // EPBAR [31:12] 23 24 Offset(0x48), // MCHBAR (0:0:0:48) 25 MHEN, 1, // Enable 26 , 14, 27 MHBR, 17, // MCHBAR [31:15] 28 29 Offset(0x50), // GGC (0:0:0:50) 30 GCLK, 1, // GGCLCK 31 32 Offset(0x54), // DEVEN (0:0:0:54) 33 D0EN, 1, // DEV0 Enable 34 D1F2, 1, // DEV1 FUN2 Enable 35 D1F1, 1, // DEV1 FUN1 Enable 36 D1F0, 1, // DEV1 FUN0 Enable 37 38 Offset(0x60), // PCIEXBAR (0:0:0:60) 39 PXEN, 1, // Enable 40 PXSZ, 2, // PCI Express Size 41 , 23, 42 PXBR, 6, // PCI Express BAR [31:26] 43 44 Offset(0x68), // DMIBAR (0:0:0:68) 45 DIEN, 1, // Enable 46 , 11, 47 DIBR, 20, // DMIBAR [31:12] 48 49 Offset(0x70), // MESEG_BASE (0:0:0:70) 50 , 20, 51 MEBR, 12, // MESEG_BASE [31:20] 52 53 Offset(0x80), // PAM0 Register (0:0:0:80) 54 PMLK, 1, // PAM Lock bit. 55 , 3, 56 PM0H, 2, // PAM 0, High Nibble 57 , 2, 58 59 Offset(0x81), // PAM1 Register (0:0:0:81) 60 PM1L, 2, // PAM1, Low Nibble 61 , 2, 62 PM1H, 2, // PAM1, High Nibble 63 , 2, 64 65 Offset(0x82), // PAM2 Register (0:0:0:82) 66 PM2L, 2, // PAM2, Low Nibble 67 , 2, 68 PM2H, 2, // PAM2, High Nibble 69 , 2, 70 71 Offset(0x83), // PAM3 Register (0:0:0:83) 72 PM3L, 2, // PAM3, Low Nibble 73 , 2, 74 PM3H, 2, // PAM3, High Nibble 75 , 2, 76 77 Offset(0x84), // PAM4 Register (0:0:0:84) 78 PM4L, 2, // PAM4, Low Nibble 79 , 2, 80 PM4H, 2, // PAM4, High Nibble 81 , 2, 82 83 Offset(0x85), // PAM5 Register (0:0:0:85) 84 PM5L, 2, // PAM5, Low Nibble 85 , 2, 86 PM5H, 2, // PAM5, High Nibble 87 , 2, 88 89 Offset(0x86), // PAM6 Register (0:0:0:86) 90 PM6L, 2, // PAM6, Low Nibble 91 , 2, 92 PM6H, 2, // PAM6, High Nibble 93 , 2, 94 95 Offset(0xA8), // Top of Upper Usable DRAM Register (0:0:0:A8) 96 , 20, 97 TUUD, 19, // TOUUD [38:20] 98 99 Offset(0xBC), // Top of Lower Usable DRAM Register (0:0:0:BC) 100 , 20, 101 TLUD, 12, // TOLUD [31:20] 102 103 Offset(0xC8), // ERRSTS register (0:0:0:C8) 104 , 7, 105 HTSE, 1 // Host Thermal Sensor Event for SMI/SCI/SERR 106} 107 108// 109// Define a buffer that will store all the bus, memory, and IO information 110// relating to the Host Bus. This buffer will be dynamically altered in 111// the _CRS and passed back to the OS. 112// 113Name(BUF0,ResourceTemplate() 114{ 115 // 116 // Bus Number Allocation: Bus 0 to 0xFF 117 // 118 WORDBusNumber(ResourceProducer,MinFixed,MaxFixed,PosDecode,0x00, 119 0x0000,0x00FF,0x00,0x0100,,,PB00) 120 121 // 122 // I/O Region Allocation 0 ( 0x0000 - 0x0CF7 ) 123 // 124 DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange, 125 0x00,0x0000,0x0CF7,0x00,0x0CF8,,,PI00) 126 127 // 128 // PCI Configuration Registers ( 0x0CF8 - 0x0CFF ) 129 // 130 Io(Decode16,0x0CF8,0x0CF8,1,0x08) 131 132 // 133 // I/O Region Allocation 1 ( 0x0D00 - 0xFFFF ) 134 // 135 DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange, 136 0x00,0x0D00,0xFFFF,0x00,0xF300,,,PI01) 137 138 // 139 // Video Buffer Area ( 0xA0000 - 0xBFFFF ) 140 // 141 DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, 142 ReadWrite,0x00,0xA0000,0xBFFFF,0x00,0x20000,,,A000) 143 144 // 145 // ISA Add-on BIOS Area ( 0xC0000 - 0xC3FFF ) 146 // 147 DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, 148 ReadWrite,0x00,0xC0000,0xC3FFF,0x00,0x4000,,,C000) 149 150 // 151 // ISA Add-on BIOS Area ( 0xC4000 - 0xC7FFF ) 152 // 153 DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, 154 ReadWrite,0x00,0xC4000,0xC7FFF,0x00,0x4000,,,C400) 155 156 // 157 // ISA Add-on BIOS Area ( 0xC8000 - 0xCBFFF ) 158 // 159 DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, 160 ReadWrite,0x00,0xC8000,0xCBFFF,0x00,0x4000,,,C800) 161 162 // 163 // ISA Add-on BIOS Area ( 0xCC000 - 0xCFFFF ) 164 // 165 DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, 166 ReadWrite,0x00,0xCC000,0xCFFFF,0x00,0x4000,,,CC00) 167 168 // 169 // ISA Add-on BIOS Area ( 0xD0000 - 0xD3FFF ) 170 // 171 DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, 172 ReadWrite,0x00,0xD0000,0xD3FFF,0x00,0x4000,,,D000) 173 174 // 175 // ISA Add-on BIOS Area ( 0xD4000 - 0xD7FFF ) 176 // 177 DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, 178 ReadWrite,0x00,0xD4000,0xD7FFF,0x00,0x4000,,,D400) 179 180 // 181 // ISA Add-on BIOS Area ( 0xD8000 - 0xDBFFF ) 182 // 183 DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, 184 ReadWrite,0x00,0xD8000,0xDBFFF,0x00,0x4000,,,D800) 185 186 // 187 // ISA Add-on BIOS Area ( 0xDC000 - 0xDFFFF ) 188 // 189 DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, 190 ReadWrite,0x00,0xDC000,0xDFFFF,0x00,0x4000,,,DC00) 191 192 // 193 // BIOS Extension Area ( 0xE0000 - 0xE3FFF ) 194 // 195 DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, 196 ReadWrite,0x00,0xE0000,0xE3FFF,0x00,0x4000,,,E000) 197 198 // 199 // BIOS Extension Area ( 0xE4000 - 0xE7FFF ) 200 // 201 DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, 202 ReadWrite,0x00,0xE4000,0xE7FFF,0x00,0x4000,,,E400) 203 204 // 205 // BIOS Extension Area ( 0xE8000 - 0xEBFFF ) 206 // 207 DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, 208 ReadWrite,0x00,0xE8000,0xEBFFF,0x00,0x4000,,,E800) 209 210 // 211 // BIOS Extension Area ( 0xEC000 - 0xEFFFF ) 212 // 213 DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, 214 ReadWrite,0x00,0xEC000,0xEFFFF,0x00,0x4000,,,EC00) 215 216 // 217 // BIOS Area ( 0xF0000 - 0xFFFFF ) 218 // 219 DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, 220 ReadWrite,0x00,0xF0000,0xFFFFF,0x00,0x10000,,,F000) 221 222// // 223// // Memory Hole Region ( 0xF00000 - 0xFFFFFF ) 224// // 225// DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, 226// ReadWrite,0x00,0xF00000,0xFFFFFF,0x00,0x100000,,,HOLE) 227 228 // 229 // PCI Memory Region ( TOLUD - 0xDFFFFFFF ) 230 // 231 DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable, 232 ReadWrite,0x00,0x00000000,0xDFFFFFFF,0x00,0xE0000000,,,PM01) 233 234 // 235 // PCI Memory Region ( TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE) ) 236 // (This is dummy range for OS compatibility, will patch it in _CRS) 237 // 238 QWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable, 239 ReadWrite,0x00,0x10000,0x1FFFF,0x00,0x10000,,,PM02) 240 241 // 242 // PCH reserved resources ( 0xFC800000 - 0xFE7FFFFF ) 243 // 244 DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable, 245 ReadWrite,0x00,0xFC800000,0xFE7FFFFF,0x00,0x2000000,,,PM03) 246}) 247 248Name(EP_B, 0) // to store EP BAR 249Name(MH_B, 0) // to store MCH BAR 250Name(PC_B, 0) // to store PCIe BAR 251Name(PC_L, 0) // to store PCIe BAR Length 252Name(DM_B, 0) // to store DMI BAR 253 254// 255// Get EP BAR 256// 257Method(GEPB,0,Serialized) 258{ 259 if(LEqual(EP_B,0)) 260 { 261 ShiftLeft(\_SB.PCI0.EPBR,12,EP_B) 262 } 263 Return(EP_B) 264} 265 266// 267// Get MCH BAR 268// 269Method(GMHB,0,Serialized) 270{ 271 if(LEqual(MH_B,0)) 272 { 273 ShiftLeft(\_SB.PCI0.MHBR,15,MH_B) 274 } 275 Return(MH_B) 276} 277 278// 279// Get PCIe BAR 280// 281Method(GPCB,0,Serialized) 282{ 283 if(LEqual(PC_B,0)) 284 { 285 ShiftLeft(\_SB.PCI0.PXBR,26,PC_B) 286 } 287 Return(PC_B) 288} 289 290// 291// Get PCIe Length 292// 293Method(GPCL,0,Serialized) 294{ 295 if(LEqual(PC_L,0)) { 296 ShiftRight(0x10000000, \_SB.PCI0.PXSZ,PC_L) 297 } 298 Return(PC_L) 299} 300 301// 302// Get DMI BAR 303// 304Method(GDMB,0,Serialized) 305{ 306 if(LEqual(DM_B,0)) 307 { 308 ShiftLeft(\_SB.PCI0.DIBR,12,DM_B) 309 } 310 Return(DM_B) 311} 312 313 314Method(_CRS,0,Serialized) 315{ 316 // 317 // Fix up Max Bus Number and Length 318 // 319 Store(\_SB.PCI0.GPCL(),Local0) 320 CreateWordField(BUF0, ^PB00._MAX, PBMX) 321 Store(Subtract(ShiftRight(Local0,20),2), PBMX) 322 CreateWordField(BUF0, ^PB00._LEN, PBLN) 323 Store(Subtract(ShiftRight(Local0,20),1), PBLN) 324 // 325 // Fix up all of the Option ROM areas from 0xC0000-0xFFFFF. 326 // 327 If(PM1L) // \_SB.PCI0 328 { 329 // PAMx != 0. Set length = 0. 330 331 CreateDwordField(BUF0, ^C000._LEN,C0LN) 332 Store(Zero,C0LN) 333 } 334 335 If(LEqual(PM1L,1)) 336 { 337 CreateBitField(BUF0, ^C000._RW,C0RW) 338 Store(Zero,C0RW) 339 } 340 341 If(PM1H) 342 { 343 CreateDwordField(BUF0, ^C400._LEN,C4LN) 344 Store(Zero,C4LN) 345 } 346 347 If(LEqual(PM1H,1)) 348 { 349 CreateBitField(BUF0, ^C400._RW,C4RW) 350 Store(Zero,C4RW) 351 } 352 353 If(PM2L) 354 { 355 CreateDwordField(BUF0, ^C800._LEN,C8LN) 356 Store(Zero,C8LN) 357 } 358 359 If(LEqual(PM2L,1)) 360 { 361 CreateBitField(BUF0, ^C800._RW,C8RW) 362 Store(Zero,C8RW) 363 } 364 365 If(PM2H) 366 { 367 CreateDwordField(BUF0, ^CC00._LEN,CCLN) 368 Store(Zero,CCLN) 369 } 370 371 If(LEqual(PM2H,1)) 372 { 373 CreateBitField(BUF0, ^CC00._RW,CCRW) 374 Store(Zero,CCRW) 375 } 376 377 If(PM3L) 378 { 379 CreateDwordField(BUF0, ^D000._LEN,D0LN) 380 Store(Zero,D0LN) 381 } 382 383 If(LEqual(PM3L,1)) 384 { 385 CreateBitField(BUF0, ^D000._RW,D0RW) 386 Store(Zero,D0RW) 387 } 388 389 If(PM3H) 390 { 391 CreateDwordField(BUF0, ^D400._LEN,D4LN) 392 Store(Zero,D4LN) 393 } 394 395 If(LEqual(PM3H,1)) 396 { 397 CreateBitField(BUF0, ^D400._RW,D4RW) 398 Store(Zero,D4RW) 399 } 400 401 If(PM4L) 402 { 403 CreateDwordField(BUF0, ^D800._LEN,D8LN) 404 Store(Zero,D8LN) 405 } 406 407 If(LEqual(PM4L,1)) 408 { 409 CreateBitField(BUF0, ^D800._RW,D8RW) 410 Store(Zero,D8RW) 411 } 412 413 If(PM4H) 414 { 415 CreateDwordField(BUF0, ^DC00._LEN,DCLN) 416 Store(Zero,DCLN) 417 } 418 419 If(LEqual(PM4H,1)) 420 { 421 CreateBitField(BUF0, ^DC00._RW,DCRW) 422 Store(Zero,DCRW) 423 } 424 425 If(PM5L) 426 { 427 CreateDwordField(BUF0, ^E000._LEN,E0LN) 428 Store(Zero,E0LN) 429 } 430 431 If(LEqual(PM5L,1)) 432 { 433 CreateBitField(BUF0, ^E000._RW,E0RW) 434 Store(Zero,E0RW) 435 } 436 437 If(PM5H) 438 { 439 CreateDwordField(BUF0, ^E400._LEN,E4LN) 440 Store(Zero,E4LN) 441 } 442 443 If(LEqual(PM5H,1)) 444 { 445 CreateBitField(BUF0, ^E400._RW,E4RW) 446 Store(Zero,E4RW) 447 } 448 449 If(PM6L) 450 { 451 CreateDwordField(BUF0, ^E800._LEN,E8LN) 452 Store(Zero,E8LN) 453 } 454 455 If(LEqual(PM6L,1)) 456 { 457 CreateBitField(BUF0, ^E800._RW,E8RW) 458 Store(Zero,E8RW) 459 } 460 461 If(PM6H) 462 { 463 CreateDwordField(BUF0, ^EC00._LEN,ECLN) 464 Store(Zero,ECLN) 465 } 466 467 If(LEqual(PM6H,1)) 468 { 469 CreateBitField(BUF0, ^EC00._RW,ECRW) 470 Store(Zero,ECRW) 471 } 472 473 If(PM0H) 474 { 475 CreateDwordField(BUF0, ^F000._LEN,F0LN) 476 Store(Zero,F0LN) 477 } 478 479 If(LEqual(PM0H,1)) 480 { 481 CreateBitField(BUF0, ^F000._RW,F0RW) 482 Store(Zero,F0RW) 483 } 484 485 // 486 // Create pointers to Memory Sizing values. 487 // 488 CreateDwordField(BUF0, ^PM01._MIN,M1MN) 489 CreateDwordField(BUF0, ^PM01._MAX,M1MX) 490 CreateDwordField(BUF0, ^PM01._LEN,M1LN) 491 492 // 493 // Set Memory Size Values. TLUD represents bits 31:20 of phyical 494 // TOM, so shift these bits into the correct position and fix up 495 // the Memory Region available to PCI. 496 // 497 Store (0x50800000, M1LN) 498 Store (0x8F800000, M1MN) 499 Subtract (Add (M1MN, M1LN), 1, M1MX) 500 501 // 502 // Create pointers to Memory Sizing values. 503 // Patch PM02 range basing on memory size and OS type 504 // 505 CreateQwordField(BUF0, ^PM02._LEN,MSLN) 506 // 507 // Set resource length to 0 508 // 509 Store (0, MSLN) 510 511 D8XH (0, 0xC5) 512 D8XH (1, 0xAA) 513 514 Return(BUF0) 515} 516 517