1 /** @file
2   Silicon Init APIs for MinPlatform BoardInitLib implementations.
3 
4 Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
6 
7 **/
8 
9 #include <PiPei.h>
10 #include <Guid/TcoWdtHob.h>
11 #include <Library/IoLib.h>
12 #include <Library/DebugLib.h>
13 #include <Library/HobLib.h>
14 #include <Library/PcdLib.h>
15 #include <Library/PeiServicesLib.h>
16 #include <Library/PchCycleDecodingLib.h>
17 #include <Library/PmcLib.h>
18 #include <Register/PchRegsLpc.h>
19 #include <Register/PchRegsPmc.h>
20 
21 /**
22   Early Silicon initialization
23 **/
24 VOID
25 EarlySiliconInit (
26   VOID
27   )
28 {
29   UINT16       Data16;
30   UINT8        Data8;
31   UINT8        TcoRebootHappened;
32   TCO_WDT_HOB  *TcoWdtHobPtr;
33   EFI_STATUS   Status;
34 
35   ///
36   /// LPC I/O Configuration
37   ///
38   PchLpcIoDecodeRangesSet (
39     (V_LPC_CFG_IOD_LPT_378 << N_LPC_CFG_IOD_LPT)    |
40     (V_LPC_CFG_IOD_COMB_3E8 << N_LPC_CFG_IOD_COMB)  |
41     (V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA)
42     );
43 
44   PchLpcIoEnableDecodingSet (
45     B_LPC_CFG_IOE_ME2 |
46     B_LPC_CFG_IOE_SE  |
47     B_LPC_CFG_IOE_ME1 |
48     B_LPC_CFG_IOE_KE  |
49     B_LPC_CFG_IOE_HGE |
50     B_LPC_CFG_IOE_LGE |
51     B_LPC_CFG_IOE_FDE |
52     B_LPC_CFG_IOE_PPE |
53     B_LPC_CFG_IOE_CBE |
54     B_LPC_CFG_IOE_CAE
55     );
56 
57   ///
58   /// Halt the TCO timer
59   ///
60   Data16 = IoRead16 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT);
61   Data16 |= B_TCO_IO_TCO1_CNT_TMR_HLT;
62   IoWrite16 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT, Data16);
63 
64   ///
65   /// Read the Second TO status bit
66   ///
67   Data8 = IoRead8 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS);
68   if ((Data8 & B_TCO_IO_TCO2_STS_SECOND_TO) == B_TCO_IO_TCO2_STS_SECOND_TO) {
69     TcoRebootHappened = 1;
70     DEBUG ((DEBUG_INFO, "PlatformInitPreMem - TCO Second TO status bit is set. This might be a TCO reboot\n"));
71   }
72   else {
73     TcoRebootHappened = 0;
74   }
75 
76   ///
77   /// Create HOB
78   ///
79   Status = PeiServicesCreateHob (EFI_HOB_TYPE_GUID_EXTENSION, sizeof(TCO_WDT_HOB), (VOID **)&TcoWdtHobPtr);
80   if (!EFI_ERROR (Status)) {
81     TcoWdtHobPtr->Header.Name = gTcoWdtHobGuid;
82     TcoWdtHobPtr->TcoRebootHappened = TcoRebootHappened;
83   }
84 
85   ///
86   /// Clear the Second TO status bit
87   ///
88   IoWrite8 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS, B_TCO_IO_TCO2_STS_SECOND_TO);
89 }
90 
91 /**
92   Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal inversion registers
93 
94 **/
95 VOID
96 SiliconInit (
97   VOID
98   )
99 {
100   UINT16       ABase;
101 
102   ABase = PmcGetAcpiBase ();
103 
104   ///
105   /// Clear all pending SMI. On S3 clear power button enable so it will not generate an SMI.
106   ///
107   IoWrite16 (ABase + R_ACPI_IO_PM1_EN, 0);
108   IoWrite32 (ABase + R_ACPI_IO_GPE0_EN_127_96, 0);
109 }
110