1 /** @file 2 ME config block for PEI phase 3 4 Copyright (c) 2019 Intel Corporation. All rights reserved. <BR> 5 6 SPDX-License-Identifier: BSD-2-Clause-Patent 7 **/ 8 9 #ifndef _ME_PEI_CONFIG_H_ 10 #define _ME_PEI_CONFIG_H_ 11 12 #include <ConfigBlock.h> 13 14 #define ME_PEI_PREMEM_CONFIG_REVISION 2 15 extern EFI_GUID gMePeiPreMemConfigGuid; 16 17 #ifndef PLATFORM_POR 18 #define PLATFORM_POR 0 19 #endif 20 #ifndef FORCE_ENABLE 21 #define FORCE_ENABLE 1 22 #endif 23 #ifndef FORCE_DISABLE 24 #define FORCE_DISABLE 2 25 #endif 26 27 #pragma pack (push,1) 28 29 /** 30 ME Pei Pre-Memory Configuration Structure. 31 32 <b>Revision 1:</b> 33 - Initial version. 34 <b>Revision 2</b>: 35 - Change DidInitStat bit width. 36 **/ 37 typedef struct { 38 CONFIG_BLOCK_HEADER Header; ///< Config Block Header 39 UINT32 HeciTimeouts : 1; ///< 0: Disable; <b>1: Enable</b> - HECI Send/Receive Timeouts. 40 /** 41 <b>(Test)</b> 42 <b>0: Disabled</b> 43 1: ME DID init stat 0 - Success 44 2: ME DID init stat 1 - No Memory in Channels 45 3: ME DID init stat 2 - Memory Init Error 46 **/ 47 UINT32 DidInitStat : 2; 48 /** 49 <b>(Test)</b> 50 <b>0: Set to 0 to enable polling for CPU replacement</b> 51 1: Set to 1 will disable polling for CPU replacement 52 **/ 53 UINT32 DisableCpuReplacedPolling : 1; 54 UINT32 SendDidMsg : 1; ///< <b>(Test)</b> 0: Disable; <b>1: Enable</b> - Enable/Disable to send DID message. 55 /** 56 <b>(Test)</b> 57 <b>0: Set to 0 to enable retry mechanism for HECI APIs</b> 58 1: Set to 1 will disable retry mechanism for HECI APIs 59 **/ 60 UINT32 DisableHeciRetry : 1; 61 /** 62 <b>(Test)</b> 63 <b>0: ME BIOS will check each messages before sending</b> 64 1: ME BIOS always sends messages without checking 65 **/ 66 UINT32 DisableMessageCheck : 1; 67 /** 68 <b>(Test)</b> 69 The SkipMbpHob policy determines whether ME BIOS Payload data will be requested during boot 70 in a MBP message. If set to 1, BIOS will send the MBP message with SkipMbp flag 71 set causing CSME to respond with MKHI header only and no MBP data 72 <b>0: ME BIOS will keep MBP and create HOB for MBP data</b> 73 1: ME BIOS will skip MBP data 74 **/ 75 UINT32 SkipMbpHob : 1; 76 UINT32 HeciCommunication2 : 1; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Enable - Enable/Disable HECI2. 77 UINT32 KtDeviceEnable : 1; ///< <b>(Test)</b> 0: Disable; <b>1: Enable</b> - Enable/Disable Kt Device. 78 UINT32 RsvdBits : 22; ///< Reserved for future use & Config block alignment 79 UINT32 Heci1BarAddress; ///< HECI1 BAR address. 80 UINT32 Heci2BarAddress; ///< HECI2 BAR address. 81 UINT32 Heci3BarAddress; ///< HECI3 BAR address. 82 } ME_PEI_PREMEM_CONFIG; 83 #pragma pack (pop) 84 85 86 #define ME_PEI_CONFIG_REVISION 2 87 extern EFI_GUID gMePeiConfigGuid; 88 89 #pragma pack (push,1) 90 91 /** 92 ME Pei Post-Memory Configuration Structure. 93 94 <b>Revision 1:</b> 95 - Initial version. 96 <b>Revision 2</b>: 97 - Add MctpBroadcastCycle test setting. 98 **/ 99 typedef struct { 100 CONFIG_BLOCK_HEADER Header; ///< Config Block Header 101 102 UINT32 EndOfPostMessage : 2; ///< 0: Disabled; 1: Send in PEI; <b>2: Send in DXE</b> - Send EOP at specific phase. 103 /** 104 HECI3 state from Mbp for reference in S3 path only 105 <b>0: Disabled</b>; 1: Enabled 106 **/ 107 UINT32 Heci3Enabled : 1; 108 UINT32 DisableD0I3SettingForHeci : 1; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Enable - Enable/Disable D0i3 for HECI. 109 /** 110 Enable/Disable Me Unconfig On Rtc Clear. If enabled, BIOS will send MeUnconfigOnRtcClearDisable Msg with parameter 0. 111 It will cause ME to unconfig if RTC is cleared. 112 - 0: Disable 113 - <b>1: Enable</b> 114 - 2: Cmos is clear, status unkonwn 115 - 3: Reserved 116 **/ 117 UINT32 MeUnconfigOnRtcClear : 2; 118 UINT32 MctpBroadcastCycle : 1; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Enable - Program registers for MCTP Cycle. 119 UINT32 RsvdBits : 25; ///< Reserved for future use & Config block alignment 120 } ME_PEI_CONFIG; 121 122 #pragma pack (pop) 123 124 #endif // _ME_PEI_CONFIG_H_ 125