1 /** @file 2 Definitions required to create RstHob 3 4 Copyright (c) 2019 Intel Corporation. All rights reserved. <BR> 5 6 SPDX-License-Identifier: BSD-2-Clause-Patent 7 **/ 8 9 #ifndef _PCH_RST_HOB_ 10 #define _PCH_RST_HOB_ 11 12 extern EFI_GUID gPchRstHobGuid; 13 14 // 15 // This struct is used to record the fields that should be restored during device wake up 16 // 17 typedef struct { 18 UINT8 PmCapPtr; 19 UINT8 PcieCapPtr; 20 UINT16 L1ssCapPtr; 21 UINT8 EndpointL1ssControl2; 22 UINT32 EndpointL1ssControl1; 23 UINT16 LtrCapPtr; 24 UINT32 EndpointLtrData; 25 UINT16 EndpointLctlData16; 26 UINT16 EndpointDctlData16; 27 UINT16 EndpointDctl2Data16; 28 UINT16 RootPortDctl2Data16; 29 } SAVED_DEVICE_CONFIG_SPACE; 30 31 // 32 // This structure is used to record the result of PCIe storageremapping for each cycle router 33 // 34 typedef struct { 35 UINT8 RootPortNum; // Indicates the root port number with RST PCIe Storage Remapping remapping supported and PCIe storage device plugged on, numbering is 0-based 36 UINT8 DeviceInterface; // Indicates the interface of the PCIe storage device (AHCI or NVMe) 37 UINT32 EndPointUniqueMsixTableBar; // Records the PCIe storage device's MSI-X Table BAR if it supports unique MSI-X Table BAR 38 UINT32 EndPointUniqueMsixTableBarValue; // Records the PCIe storage device's MSI-X Table BAR value if it supports unique MSI-X Table BAR 39 UINT32 EndPointUniqueMsixPbaBar; // Records the PCIe storage device's MSI-X PBA BAR if it supports unique MSI-X PBA BAR 40 UINT32 EndPointUniqueMsixPbaBarValue; // Records the PCIe storage device's MSI-X PBA BAR value if it supports unique MSI-X PBA BAR 41 } RST_CR_CONFIGURATION; 42 43 // 44 // Passes to DXE results of PCIe storage remapping 45 // 46 typedef struct { 47 // 48 // Stores configuration information about cycle router 49 // 50 RST_CR_CONFIGURATION RstCrConfiguration[PCH_MAX_RST_PCIE_STORAGE_CR]; 51 52 // 53 // Saved fields from hidden device config space to be used later by RST driver 54 // 55 SAVED_DEVICE_CONFIG_SPACE SavedRemapedDeviceConfigSpace[PCH_MAX_RST_PCIE_STORAGE_CR]; 56 } PCH_RST_HOB; 57 58 #endif 59