1 /** @file 2 Register names for PCH USB devices 3 4 Conventions: 5 6 - Prefixes: 7 Definitions beginning with "R_" are registers 8 Definitions beginning with "B_" are bits within registers 9 Definitions beginning with "V_" are meaningful values within the bits 10 Definitions beginning with "S_" are register sizes 11 Definitions beginning with "N_" are the bit position 12 - In general, PCH registers are denoted by "_PCH_" in register names 13 - Registers / bits that are different between PCH generations are denoted by 14 "_PCH_[generation_name]_" in register/bit names. 15 - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. 16 Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. 17 e.g., "_PCH_H_", "_PCH_LP_" 18 Registers / bits names without _H_ or _LP_ apply for both H and LP. 19 - Registers / bits that are different between SKUs are denoted by "_[SKU_name]" 20 at the end of the register/bit names 21 - Registers / bits of new devices introduced in a PCH generation will be just named 22 as "_PCH_" without [generation_name] inserted. 23 24 Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> 25 SPDX-License-Identifier: BSD-2-Clause-Patent 26 27 **/ 28 #ifndef _PCH_REGS_USB_H_ 29 #define _PCH_REGS_USB_H_ 30 31 // 32 // USB3 (XHCI) related definitions 33 // 34 #define PCI_BUS_NUMBER_PCH_XHCI 0 35 #define PCI_DEVICE_NUMBER_PCH_XHCI 20 36 #define PCI_FUNCTION_NUMBER_PCH_XHCI 0 37 38 // 39 // XHCI PCI Config Space registers 40 // 41 #define R_PCH_XHCI_MEM_BASE 0x10 42 #define R_PCH_XHCI_MEM_BASE_2 0x14 43 #define V_PCH_XHCI_MEM_LENGTH 0x10000 44 #define N_PCH_XHCI_MEM_SHIFT 32 45 #define N_PCH_XHCI_MEM_ALIGN 16 46 #define B_PCH_XHCI_MEM_ALIGN_MASK 0xFFFF 47 48 #define R_PCH_XHCI_XHCC1 0x40 49 #define B_PCH_XHCI_XHCC1_ACCTRL BIT31 50 #define B_PCH_XHCI_XHCC1_RMTASERR BIT24 51 #define B_PCH_XHCI_XHCC1_URD BIT23 52 #define B_PCH_XHCI_XHCC1_URRE BIT22 53 #define B_PCH_XHCI_XHCC1_IIL1E (BIT21 | BIT20 | BIT19) 54 #define V_PCH_XHCI_XHCC1_IIL1E_DIS 0 55 #define V_PCH_XHCI_XHCC1_IIL1E_32 (BIT19) 56 #define V_PCH_XHCI_XHCC1_IIL1E_64 (BIT20) 57 #define V_PCH_XHCI_XHCC1_IIL1E_128 (BIT20 | BIT19) 58 #define V_PCH_XHCI_XHCC1_IIL1E_256 (BIT21) 59 #define V_PCH_XHCI_XHCC1_IIL1E_512 (BIT21 | BIT19) 60 #define V_PCH_XHCI_XHCC1_IIL1E_1024 (BIT21 | BIT20) 61 #define V_PCH_XHCI_XHCC1_IIL1E_131072 (BIT21 | BIT20 | BIT19) 62 #define B_PCH_XHCI_XHCC1_XHCIL1E BIT18 63 #define B_PCH_XHCI_XHCC1_D3IL1E BIT17 64 #define B_PCH_XHCI_XHCC1_UNPPA (BIT16 | BIT15 | BIT14 | BIT13 | BIT12) 65 #define B_PCH_XHCI_XHCC1_SWAXHCI BIT11 66 #define B_PCH_XHCI_XHCC1_L23HRAWC (BIT10 | BIT9 | BIT8) 67 #define B_PCH_XHCI_XHCC1_UTAGCP (BIT7 | BIT6) 68 #define B_PCH_XHCI_XHCC1_UDAGCNP (BIT5 | BIT4) 69 #define B_PCH_XHCI_XHCC1_UDAGCCP (BIT3 | BIT2) 70 #define B_PCH_XHCI_XHCC1_UDAGC (BIT1 | BIT0) 71 72 #define R_PCH_XHCI_XHCC2 0x44 73 #define B_PCH_XHCI_XHCC2_OCCFDONE BIT31 74 #define B_PCH_XHCI_XHCC2_XHCUPRDROE BIT11 75 #define B_PCH_XHCI_XHCC2_IOSFSRAD BIT10 76 #define B_PCH_XHCI_XHCC2_SWACXIHB (BIT9 | BIT8) 77 #define B_PCH_XHCI_XHCC2_SWADMIL1IHB (BIT7 | BIT6) 78 #define B_PCH_XHCI_XHCC2_L1FP2CGWC (BIT5 | BIT4 | BIT3) 79 #define B_PCH_XHCI_XHCC2_RDREQSZCTRL (BIT2 | BIT1 | BIT0) 80 81 #define R_PCH_XHCI_XHCLKGTEN 0x50 82 #define B_PCH_XHCI_XHCLKGTEN_SSLSE BIT26 83 #define B_PCH_XHCI_XHCLKGTEN_USB2PLLSE BIT25 84 #define B_PCH_XHCI_XHCLKGTEN_IOSFSTCGE BIT24 85 #define B_PCH_XHCI_XHCLKGTEN_HSTCGE (BIT23 | BIT22 | BIT21 | BIT20) 86 #define B_PCH_XHCI_XHCLKGTEN_SSTCGE (BIT19 | BIT18 | BIT17 | BIT16) 87 #define B_PCH_XHCI_XHCLKGTEN_XHCIGEU3S BIT15 88 #define B_PCH_XHCI_XHCLKGTEN_XHCFTCLKSE BIT14 89 #define B_PCH_XHCI_XHCLKGTEN_XHCBBTCGIPISO BIT13 90 #define B_PCH_XHCI_XHCLKGTEN_XHCHSTCGU2NRWE BIT12 91 #define B_PCH_XHCI_XHCLKGTEN_XHCUSB2PLLSDLE (BIT11 | BIT10) 92 #define B_PCH_XHCI_XHCLKGTEN_HSPLLSUE (BIT9 | BIT8) 93 #define B_PCH_XHCI_XHCLKGTEN_SSPLLSUE (BIT7 | BIT6 | BIT5) 94 #define B_PCH_XHCI_XHCLKGTEN_XHCBLCGE BIT4 95 #define B_PCH_XHCI_XHCLKGTEN_HSLTCGE BIT3 96 #define B_PCH_XHCI_XHCLKGTEN_SSLTCGE BIT2 97 #define B_PCH_XHCI_XHCLKGTEN_IOSFBTCGE BIT1 98 #define B_PCH_XHCI_XHCLKGTEN_IOSFGBLCGE BIT0 99 100 #define R_PCH_XHCI_USB_RELNUM 0x60 101 #define B_PCH_XHCI_USB_RELNUM 0xFF 102 #define R_PCH_XHCI_FL_ADJ 0x61 103 #define B_PCH_XHCI_FL_ADJ 0x3F 104 #define R_PCH_XHCI_PWR_CAPID 0x70 105 #define B_PCH_XHCI_PWR_CAPID 0xFF 106 #define R_PCH_XHCI_NXT_PTR1 0x71 107 #define B_PCH_XHCI_NXT_PTR1 0xFF 108 #define R_PCH_XHCI_PWR_CAP 0x72 109 #define B_PCH_XHCI_PWR_CAP_PME_SUP 0xF800 110 #define B_PCH_XHCI_PWR_CAP_D2_SUP BIT10 111 #define B_PCH_XHCI_PWR_CAP_D1_SUP BIT9 112 #define B_PCH_XHCI_PWR_CAP_AUX_CUR (BIT8 | BIT7 | BIT6) 113 #define B_PCH_XHCI_PWR_CAP_DSI BIT5 114 #define B_PCH_XHCI_PWR_CAP_PME_CLK BIT3 115 #define B_PCH_XHCI_PWR_CAP_VER (BIT2 | BIT1 | BIT0) 116 #define R_PCH_XHCI_PWR_CNTL_STS 0x74 117 #define B_PCH_XHCI_PWR_CNTL_STS_PME_STS BIT15 118 #define B_PCH_XHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13) 119 #define B_PCH_XHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 | BIT10 | BIT9) 120 #define B_PCH_XHCI_PWR_CNTL_STS_PME_EN BIT8 121 #define B_PCH_XHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0) 122 #define V_PCH_XHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0) 123 #define R_PCH_XHCI_MSI_MCTL 0x82 124 #define R_PCH_XHCI_HSCFG2 0xA4 125 #define R_PCH_XHCI_SSCFG1 0xA8 126 #define R_PCH_XHCI_HSCFG1 0xAC 127 #define R_PCH_XHCI_U2OCM 0xB0 128 #define R_PCH_XHCI_U3OCM 0xD0 129 #define V_PCH_XHCI_NUMBER_OF_OC_PINS 8 130 131 #define R_PCH_XHCI_FUS 0xE0 132 #define B_PCH_XHCI_FUS_USBR (BIT5) 133 #define V_PCH_XHCI_FUS_USBR_EN 0 134 #define V_PCH_XHCI_FUS_USBR_DIS (BIT5) 135 136 #define R_PCH_XHCI_FC 0xFC 137 138 #define B_PCH_XHCI_FUS_SSPRTCNT (BIT4 | BIT3) 139 #define V_PCH_XHCI_FUS_SSPRTCNT_00B 0 140 #define V_PCH_XHCI_FUS_SSPRTCNT_01B (BIT3) 141 #define V_PCH_XHCI_FUS_SSPRTCNT_10B (BIT4) 142 #define V_PCH_XHCI_FUS_SSPRTCNT_11B (BIT4 | BIT3) 143 144 #define B_PCH_XHCI_FUS_HSPRTCNT (BIT2 | BIT1) 145 #define V_PCH_XHCI_FUS_HSPRTCNT_00B 0 146 #define V_PCH_XHCI_FUS_HSPRTCNT_01B (BIT1) 147 #define V_PCH_XHCI_FUS_HSPRTCNT_10B (BIT2) 148 #define V_PCH_XHCI_FUS_HSPRTCNT_11B (BIT2 | BIT1) 149 150 #define V_PCH_H_XHCI_FUS_SSPRTCNT_00B_CNT 6 151 #define V_PCH_H_XHCI_FUS_SSPRTCNT_01B_CNT 4 152 #define V_PCH_H_XHCI_FUS_SSPRTCNT_10B_CNT 2 153 #define V_PCH_H_XHCI_FUS_SSPRTCNT_11B_CNT 0 154 #define V_PCH_H_XHCI_FUS_SSPRTCNT_00B_MASK 0x3F 155 #define V_PCH_H_XHCI_FUS_SSPRTCNT_01B_MASK 0x0F 156 #define V_PCH_H_XHCI_FUS_SSPRTCNT_10B_MASK 0x03 157 #define V_PCH_H_XHCI_FUS_SSPRTCNT_11B_MASK 0x00 158 159 #define V_PCH_H_XHCI_FUS_HSPRTCNT_00B_CNT 14 160 #define V_PCH_H_XHCI_FUS_HSPRTCNT_01B_CNT 12 161 #define V_PCH_H_XHCI_FUS_HSPRTCNT_10B_CNT 10 162 #define V_PCH_H_XHCI_FUS_HSPRTCNT_11B_CNT 8 163 #define V_PCH_H_XHCI_FUS_HSPRTCNT_00B_MASK 0x3FFF 164 #define V_PCH_H_XHCI_FUS_HSPRTCNT_01B_MASK 0x3F3F 165 #define V_PCH_H_XHCI_FUS_HSPRTCNT_10B_MASK 0x03FF 166 #define V_PCH_H_XHCI_FUS_HSPRTCNT_11B_MASK 0x00FF 167 168 #define V_PCH_LP_XHCI_FIXED_SSPRTCNT 4 169 #define V_PCH_LP_XHCI_FIXED_SSPRTCNT_MASK 0x0F 170 171 #define V_PCH_LP_XHCI_FIXED_HSPRTCNT 8 172 #define V_PCH_LP_XHCI_FIXED_HSPRTCNT_MASK 0x00FF 173 174 // 175 // xHCI MMIO registers 176 // 177 178 // 179 // 0x00 - 0x1F - Capability Registers 180 // 181 #define R_PCH_XHCI_CAPLENGTH 0x00 182 #define R_PCH_XHCI_HCIVERSION 0x02 183 #define R_PCH_XHCI_HCSPARAMS1 0x04 184 #define R_PCH_XHCI_HCSPARAMS2 0x08 185 #define R_PCH_XHCI_HCSPARAMS3 0x0C 186 #define B_PCH_XHCI_HCSPARAMS3_U2DEL 0xFFFF0000 187 #define B_PCH_XHCI_HCSPARAMS3_U1DEL 0x0000FFFF 188 #define R_PCH_XHCI_HCCPARAMS 0x10 189 #define B_PCH_XHCI_HCCPARAMS_LHRC BIT5 190 #define B_PCH_XHCI_HCCPARAMS_MAXPSASIZE 0xF000 191 #define R_PCH_XHCI_DBOFF 0x14 192 #define R_PCH_XHCI_RTSOFF 0x18 193 194 // 195 // 0x80 - 0xBF - Operational Registers 196 // 197 #define R_PCH_XHCI_USBCMD 0x80 198 #define B_PCH_XHCI_USBCMD_RS BIT0 ///< Run/Stop 199 #define B_PCH_XHCI_USBCMD_RST BIT1 ///< HCRST 200 #define R_PCH_XHCI_USBSTS 0x84 201 #define B_PCH_XHCI_USBSTS_HCH BIT0 202 #define B_PCH_XHCI_USBSTS_CNR BIT11 203 204 // 205 // 0x480 - 0x5CF - Port Status and Control Registers 206 // 207 #define R_PCH_LP_XHCI_PORTSC01USB2 0x480 208 #define R_PCH_LP_XHCI_PORTSC02USB2 0x490 209 #define R_PCH_LP_XHCI_PORTSC03USB2 0x4A0 210 #define R_PCH_LP_XHCI_PORTSC04USB2 0x4B0 211 #define R_PCH_LP_XHCI_PORTSC05USB2 0x4C0 212 #define R_PCH_LP_XHCI_PORTSC06USB2 0x4D0 213 #define R_PCH_LP_XHCI_PORTSC07USB2 0x4E0 214 #define R_PCH_LP_XHCI_PORTSC08USB2 0x4F0 215 #define R_PCH_LP_XHCI_PORTSC09USB2 0x500 216 #define R_PCH_LP_XHCI_PORTSC10USB2 0x510 217 218 #define R_PCH_LP_XHCI_PORTSC11USBR 0x520 219 #define R_PCH_LP_XHCI_PORTSC12USBR 0x530 220 221 #define R_PCH_LP_XHCI_PORTSC01USB3 0x540 222 #define R_PCH_LP_XHCI_PORTSC02USB3 0x550 223 #define R_PCH_LP_XHCI_PORTSC03USB3 0x560 224 #define R_PCH_LP_XHCI_PORTSC04USB3 0x570 225 #define R_PCH_LP_XHCI_PORTSC05USB3 0x580 226 #define R_PCH_LP_XHCI_PORTSC06USB3 0x590 227 228 // 229 // 0x480 - 0x5CF - Port Status and Control Registers 230 // 231 #define R_PCH_H_XHCI_PORTSC01USB2 0x480 232 #define R_PCH_H_XHCI_PORTSC02USB2 0x490 233 #define R_PCH_H_XHCI_PORTSC03USB2 0x4A0 234 #define R_PCH_H_XHCI_PORTSC04USB2 0x4B0 235 #define R_PCH_H_XHCI_PORTSC05USB2 0x4C0 236 #define R_PCH_H_XHCI_PORTSC06USB2 0x4D0 237 #define R_PCH_H_XHCI_PORTSC07USB2 0x4E0 238 #define R_PCH_H_XHCI_PORTSC08USB2 0x4F0 239 #define R_PCH_H_XHCI_PORTSC09USB2 0x500 240 #define R_PCH_H_XHCI_PORTSC10USB2 0x510 241 #define R_PCH_H_XHCI_PORTSC11USB2 0x520 242 #define R_PCH_H_XHCI_PORTSC12USB2 0x530 243 #define R_PCH_H_XHCI_PORTSC13USB2 0x540 244 #define R_PCH_H_XHCI_PORTSC14USB2 0x550 245 246 #define R_PCH_H_XHCI_PORTSC15USBR 0x560 247 #define R_PCH_H_XHCI_PORTSC16USBR 0x570 248 249 #define R_PCH_H_XHCI_PORTSC01USB3 0x580 250 #define R_PCH_H_XHCI_PORTSC02USB3 0x590 251 #define R_PCH_H_XHCI_PORTSC03USB3 0x5A0 252 #define R_PCH_H_XHCI_PORTSC04USB3 0x5B0 253 #define R_PCH_H_XHCI_PORTSC05USB3 0x5C0 254 #define R_PCH_H_XHCI_PORTSC06USB3 0x5D0 255 #define R_PCH_H_XHCI_PORTSC07USB3 0x5E0 256 #define R_PCH_H_XHCI_PORTSC08USB3 0x5F0 257 #define R_PCH_H_XHCI_PORTSC09USB3 0x600 258 #define R_PCH_H_XHCI_PORTSC10USB3 0x610 259 260 #define B_PCH_XHCI_PORTSCXUSB2_WPR BIT31 ///< Warm Port Reset 261 #define B_PCH_XHCI_PORTSCXUSB2_CEC BIT23 ///< Port Config Error Change 262 #define B_PCH_XHCI_PORTSCXUSB2_PLC BIT22 ///< Port Link State Change 263 #define B_PCH_XHCI_PORTSCXUSB2_PRC BIT21 ///< Port Reset Change 264 #define B_PCH_XHCI_PORTSCXUSB2_OCC BIT20 ///< Over-current Change 265 #define B_PCH_XHCI_PORTSCXUSB2_WRC BIT19 ///< Warm Port Reset Change 266 #define B_PCH_XHCI_PORTSCXUSB2_PEC BIT18 ///< Port Enabled Disabled Change 267 #define B_PCH_XHCI_PORTSCXUSB2_CSC BIT17 ///< Connect Status Change 268 #define B_PCH_XHCI_PORTSCXUSB2_LWS BIT16 ///< Port Link State Write Strobe 269 #define B_PCH_XHCI_USB2_U3_EXIT (BIT5 | BIT6 | BIT7 | BIT8) 270 #define B_PCH_XHCI_USB2_U0_MASK (BIT5 | BIT6 | BIT7 | BIT8) 271 #define B_PCH_XHCI_PORTSCXUSB2_PP BIT9 272 #define B_PCH_XHCI_PORTSCXUSB2_PLS (BIT5 | BIT6 | BIT7 | BIT8) ///< Port Link State 273 #define B_PCH_XHCI_PORTSCXUSB2_PR BIT4 ///< Port Reset 274 #define B_PCH_XHCI_PORTSCXUSB2_PED BIT1 ///< Port Enable/Disabled 275 #define B_PCH_XHCI_PORTSCXUSB2_CCS BIT0 ///< Current Connect Status 276 #define B_PCH_XHCI_PORT_CHANGE_ENABLE_MASK (B_PCH_XHCI_PORTSCXUSB2_CEC | B_PCH_XHCI_PORTSCXUSB2_PLC | B_PCH_XHCI_PORTSCXUSB2_PRC | B_PCH_XHCI_PORTSCXUSB2_OCC | B_PCH_XHCI_PORTSCXUSB2_WRC | B_PCH_XHCI_PORTSCXUSB2_PEC | B_PCH_XHCI_PORTSCXUSB2_CSC | B_PCH_XHCI_PORTSCXUSB2_PED) 277 #define B_PCH_XHCI_PORTPMSCXUSB2_PTC (BIT28 | BIT29 | BIT30 | BIT31) ///< Port Test Control 278 279 #define B_PCH_XHCI_PORTSCXUSB3_WPR BIT31 ///< Warm Port Reset 280 #define B_PCH_XHCI_PORTSCXUSB3_CEC BIT23 ///< Port Config Error Change 281 #define B_PCH_XHCI_PORTSCXUSB3_PLC BIT22 ///< Port Link State Change 282 #define B_PCH_XHCI_PORTSCXUSB3_PRC BIT21 ///< Port Reset Change 283 #define B_PCH_XHCI_PORTSCXUSB3_OCC BIT20 ///< Over-current Change 284 #define B_PCH_XHCI_PORTSCXUSB3_WRC BIT19 ///< Warm Port Reset Change 285 #define B_PCH_XHCI_PORTSCXUSB3_PEC BIT18 ///< Port Enabled Disabled Change 286 #define B_PCH_XHCI_PORTSCXUSB3_CSC BIT17 ///< Connect Status Change 287 #define B_PCH_XHCI_PORTSCXUSB3_LWS BIT16 ///< Port Link State Write Strobe 288 #define B_PCH_XHCI_PORTSCXUSB3_PP BIT9 ///< Port Power 289 #define B_PCH_XHCI_PORTSCXUSB3_PLS (BIT8 | BIT7 | BIT6 | BIT5) ///< Port Link State 290 #define V_PCH_XHCI_PORTSCXUSB3_PLS_POLLING 0x000000E0 ///< Link is in the Polling State 291 #define V_PCH_XHCI_PORTSCXUSB3_PLS_RXDETECT 0x000000A0 ///< Link is in the RxDetect State 292 #define V_PCH_XHCI_PORTSCXUSB3_PLS_DISABLED 0x00000080 ///< Link is in the RxDetect State 293 #define B_PCH_XHCI_PORTSCXUSB3_PR BIT4 ///< Port Reset 294 #define B_PCH_XHCI_PORTSCXUSB3_PED BIT1 ///< Port Enable/Disabled 295 #define B_PCH_XHCI_PORTSCXUSB3_CHANGE_ENABLE_MASK (B_PCH_XHCI_PORTSCXUSB3_CEC | B_PCH_XHCI_PORTSCXUSB3_PLC | B_PCH_XHCI_PORTSCXUSB3_PRC | B_PCH_XHCI_PORTSCXUSB3_OCC | B_PCH_XHCI_PORTSCXUSB3_WRC | B_PCH_XHCI_PORTSCXUSB3_PEC | B_PCH_XHCI_PORTSCXUSB3_CSC | B_PCH_XHCI_PORTSCXUSB3_PED) 296 // 297 // 0x2000 - 0x21FF - Runtime Registers 298 // 0x3000 - 0x307F - Doorbell Registers 299 // 300 #define R_PCH_XHCI_XECP_SUPP_USB2_2 0x8008 301 #define R_PCH_XHCI_XECP_SUPP_USB3_2 0x8028 302 #define R_PCH_XHCI_HOST_CTRL_SCH_REG 0x8094 303 #define R_PCH_XHCI_HOST_CTRL_IDMA_REG 0x809C 304 #define R_PCH_XHCI_PMCTRL 0x80A4 305 #define R_PCH_XHCI_PGCBCTRL 0x80A8 ///< PGCB Control 306 #define R_PCH_XHCI_HOST_CTRL_MISC_REG 0x80B0 ///< Host Controller Misc Reg 307 #define R_PCH_XHCI_HOST_CTRL_MISC_REG_2 0x80B4 ///< Host Controller Misc Reg 2 308 #define R_PCH_XHCI_SSPE 0x80B8 ///< Super Speed Port Enables 309 #define B_PCH_XHCI_LP_SSPE_MASK 0x3F ///< LP: Mask for 6 USB3 ports 310 #define B_PCH_XHCI_H_SSPE_MASK 0x3FF ///< H: Mask for 10 USB3 ports 311 #define R_PCH_XHCI_AUX_CTRL_REG 0x80C0 ///< AUX_CTRL_REG - AUX Reset Control 312 #define R_PCH_XHCI_DUAL_ROLE_CFG0 0x80D8 313 #define R_PCH_XHCI_DUAL_ROLE_CFG1 0x80DC 314 #define R_PCH_XHCI_AUX_CTRL_REG1 0x80E0 315 #define R_PCH_XHCI_HOST_CTRL_PORT_LINK_REG 0x80EC ///< SuperSpeed Port Link Control 316 #define R_PCH_XHCI_XECP_CMDM_CTRL_REG1 0x818C ///< Command Manager Control 1 317 #define R_PCH_XHCI_XECP_CMDM_CTRL_REG2 0x8190 ///< Command Manager Control 2 318 #define R_PCH_XHCI_XECP_CMDM_CTRL_REG3 0x8194 ///< Command Manager Control 3 319 #define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW1 0x80F0 ///< USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4 320 #define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW2 0x80F4 ///< USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4 321 #define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW3 0x80F8 ///< USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4 322 #define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW4 0x80FC ///< USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4 323 #define R_PCH_XHCI_HOST_CTRL_TRM_REG2 0x8110 ///< HOST_CTRL_TRM_REG2 - Host Controller Transfer Manager Control 2 324 #define R_PCH_XHCI_AUX_CTRL_REG2 0x8154 ///< AUX_CTRL_REG2 - Aux PM Control Register 2 325 #define R_PCH_XHCI_AUXCLKCTL 0x816C ///< xHCI Aux Clock Control Register 326 #define R_PCH_XHCI_HOST_IF_PWR_CTRL_REG0 0x8140 ///< HOST_IF_PWR_CTRL_REG0 - Power Scheduler Control 0 327 #define R_PCH_XHCI_HOST_IF_PWR_CTRL_REG1 0x8144 ///< HOST_IF_PWR_CTRL_REG1 - Power Scheduler Control 1 328 #define R_PCH_XHCI_XHCLTVCTL2 0x8174 ///< xHC Latency Tolerance Parameters - LTV Control 329 #define R_PCH_XHCI_LTVHIT 0x817C ///< xHC Latency Tolerance Parameters - High Idle Time Control 330 #define R_PCH_XHCI_LTVMIT 0x8180 ///< xHC Latency Tolerance Parameters - Medium Idle Time Control 331 #define R_PCH_XHCI_LTVLIT 0x8184 ///< xHC Latency Tolerance Parameters - Low Idle Time Control 332 #define R_PCH_XHCI_USB2PHYPM 0x8164 ///< USB2 PHY Power Management Control 333 #define R_PCH_XHCI_PDDIS 0x8198 ///< xHC Pulldown Disable Control 334 #define R_PCH_XHCI_THROTT 0x819C ///< XHCI Throttle Control 335 #define R_PCH_XHCI_LFPSPM 0x81A0 ///< LFPS PM Control 336 #define R_PCH_XHCI_THROTT2 0x81B4 ///< XHCI Throttle 337 #define R_PCH_XHCI_LFPSONCOUNT 0x81B8 ///< LFPS On Count 338 #define R_PCH_XHCI_D0I2CTRL 0x81BC ///< D0I2 Control Register 339 #define R_PCH_XHCI_USB2PMCTRL 0x81C4 ///< USB2 Power Management Control 340 341 // 342 // SKL PCH LP FUSE 343 // 344 #define R_PCH_XHCI_LP_FUSE1 0x8410 345 #define B_PCH_XHCI_LP_FUS_HSPRTCNT (BIT1) 346 #define B_PCH_XHCI_LP_FUS_USBR (BIT5) 347 #define R_PCH_XHCI_STRAP2 0x8420 ///< USB3 Mode Strap 348 #define B_PCH_XHCI_STRAP2_USB3_SSIC_MODE (BIT1 | BIT0) ///< USB3/SSIC Mode 349 #define R_PCH_XHCI_USBLEGCTLSTS 0x8470 ///< USB Legacy Support Control Status 350 #define B_PCH_XHCI_USBLEGCTLSTS_SMIBAR BIT31 ///< SMI on BAR Status 351 #define B_PCH_XHCI_USBLEGCTLSTS_SMIPCIC BIT30 ///< SMI on PCI Command Status 352 #define B_PCH_XHCI_USBLEGCTLSTS_SMIOSC BIT29 ///< SMI on OS Ownership Change Status 353 #define B_PCH_XHCI_USBLEGCTLSTS_SMIBARE BIT15 ///< SMI on BAR Enable 354 #define B_PCH_XHCI_USBLEGCTLSTS_SMIPCICE BIT14 ///< SMI on PCI Command Enable 355 #define B_PCH_XHCI_USBLEGCTLSTS_SMIOSOE BIT13 ///< SMI on OS Ownership Enable 356 #define B_PCH_XHCI_USBLEGCTLSTS_SMIHSEE BIT4 ///< SMI on Host System Error Enable 357 #define B_PCH_XHCI_USBLEGCTLSTS_USBSMIE BIT0 ///< USB SMI Enable 358 359 // 360 // Extended Capability Registers 361 // 362 #define R_PCH_XHCI_USB2PDO 0x84F8 363 #define B_PCH_XHCI_LP_USB2PDO_MASK 0x3FF ///< LP: Mask for 10 USB2 ports 364 #define B_PCH_XHCI_H_USB2PDO_MASK 0x7FFF ///< H: Mask for 14 USB2 ports 365 #define B_PCH_XHCI_USB2PDO_DIS_PORT0 BIT0 366 367 #define R_PCH_XHCI_USB3PDO 0x84FC 368 #define B_PCH_XHCI_LP_USB3PDO_MASK 0x3F ///< LP: Mask for 6 USB3 ports 369 #define B_PCH_XHCI_H_USB3PDO_MASK 0x3FF ///< H: Mask for 10 USB3 ports 370 #define B_PCH_XHCI_USB3PDO_DIS_PORT0 BIT0 371 372 // 373 // Debug Capability Descriptor Parameters 374 // 375 #define R_PCH_XHCI_DBC_DBCCTL 0x8760 ///< DBCCTL - DbC Control 376 377 // 378 // xDCI (OTG) USB Device Controller 379 // 380 #define PCI_DEVICE_NUMBER_PCH_XDCI 20 381 #define PCI_FUNCTION_NUMBER_PCH_XDCI 1 382 383 // 384 // xDCI (OTG) PCI Config Space Registers 385 // 386 #define R_PCH_XDCI_MEM_BASE 0x10 387 #define V_PCH_XDCI_MEM_LENGTH 0x200000 388 #define R_PCH_XDCI_PMCSR 0x84 ///< Power Management Control and Status Register 389 #define R_PCH_XDCI_GENERAL_PURPOSER_REG1 0xA0 ///< General Purpose PCI RW Register1 390 #define R_PCH_XDCI_CPGE 0xA2 ///< Chassis Power Gate Enable 391 #define R_PCH_XDCI_GENERAL_PURPOSER_REG4 0xAC ///< General Purpose PCI RW Register4 392 #define R_PCH_OTG_GENERAL_INPUT_REG 0xC0 ///< General Input Register 393 394 // 395 // xDCI (OTG) MMIO registers 396 // 397 #define R_PCH_XDCI_GCTL 0xC110 ///< Xdci Global Ctrl 398 #define B_PCH_XDCI_GCTL_GHIBEREN BIT1 ///< Hibernation enable 399 #define R_PCH_XDCI_GUSB2PHYCFG 0xC200 ///< Global USB2 PHY Configuration Register 400 #define B_PCH_XDCI_GUSB2PHYCFG_SUSPHY BIT6 ///< Suspend USB2.0 HS/FS/LS PHY 401 #define R_PCH_XDCI_GUSB3PIPECTL0 0xC2C0 ///< Global USB3 PIPE Control Register 0 402 #define B_PCH_XDCI_GUSB3PIPECTL0_UX_IN_PX BIT27 ///< Ux Exit in Px 403 #define R_PCH_XDCI_APBFC_U3PMU_CFG2 0x10F810 404 #define R_PCH_XDCI_APBFC_U3PMU_CFG4 0x10F818 405 #define R_PCH_XDCI_APBFC_U3PMU_CFG5 0x10F81C 406 #define R_PCH_XDCI_APBFC_U3PMU_CFG6 0x10F820 407 408 // 409 // xDCI (OTG) Private Configuration Registers 410 // (PID:OTG) 411 // 412 #define R_PCH_PCR_OTG_IOSF_A2 0xA2 413 #define R_PCH_PCR_OTG_IOSF_PMCTL 0x1D0 414 #define R_PCH_PCR_OTG_PCICFGCTRL1 0x200 415 #define B_PCH_PCR_OTG_PCICFGCTRL_PCI_IRQ 0x0FF00000 416 #define N_PCH_PCR_OTG_PCICFGCTRL_PCI_IRQ 20 417 #define B_PCH_PCR_OTG_PCICFGCTRL_ACPI_IRQ 0x000FF000 418 #define N_PCH_PCR_OTG_PCICFGCTRL_ACPI_IRQ 12 419 #define B_PCH_PCR_OTG_PCICFGCTRL_INT_PIN 0x00000F00 420 #define N_PCH_PCR_OTG_PCICFGCTRL_INT_PIN 8 421 #define B_PCH_PCR_OTG_PCICFGCTRL_BAR1_DIS 0x00000080 422 #define B_PCH_PCR_OTG_PCICFGCTRL_PME_SUP 0x0000007C 423 #define B_PCH_PCR_OTG_PCICFGCTRL_ACPI_INT_EN 0x00000002 424 #define B_PCH_PCR_OTG_PCICFGCTRL_PCI_CFG_DIS 0x00000001 425 426 // 427 // USB2 Private Configuration Registers 428 // USB2 HIP design featured 429 // (PID:USB2) 430 // 431 #define R_PCH_PCR_USB2_GLOBAL_PORT 0x4001 ///< USB2 GLOBAL PORT 432 #define R_PCH_PCR_USB2_400C 0x400C 433 #define R_PCH_PCR_USB2_PP_LANE_BASE_ADDR 0x4000 ///< PP LANE base address 434 #define V_PCH_PCR_USB2_PER_PORT 0x00 ///< USB2 PER PORT Addr[7:2] = 0x00 435 #define V_PCH_PCR_USB2_UTMI_MISC_PER_PORT 0x08 ///< UTMI MISC REG PER PORT Addr[7:2] = 0x08 436 #define V_PCH_PCR_USB2_PER_PORT_2 0x26 ///< USB2 PER PORT 2 Addr[7:2] = 0x26 437 #define R_PCH_PCR_USB2_402A 0x402A 438 #define R_PCH_PCR_USB2_GLB_ADP_VBUS_REG 0x402B ///< GLB ADP VBUS REG 439 #define R_PCH_PCR_USB2_GLOBAL_PORT_2 0x402C ///< USB2 GLOBAL PORT 2 440 #define R_PCH_PCR_USB2_7034 0x7034 441 #define R_PCH_PCR_USB2_7038 0x7038 442 #define R_PCH_PCR_USB2_703C 0x703C 443 #define R_PCH_PCR_USB2_7040 0x7040 444 #define R_PCH_PCR_USB2_7044 0x7044 445 #define R_PCH_PCR_USB2_7048 0x7048 446 #define R_PCH_PCR_USB2_704C 0x704C 447 #define R_PCH_PCR_USB2_CFG_COMPBG 0x7F04 ///< USB2 COMPBG 448 449 // 450 // xHCI SSIC registers 451 // 452 #define R_PCH_XHCI_SSIC_GLOBAL_CONF_CTRL 0x8804 ///< SSIC Global Configuration Control 453 #define R_PCH_XHCI_SSIC_CONF_REG1_PORT_1 0x8808 ///< SSIC Configuration Register 1 Port 1 454 #define R_PCH_XHCI_SSIC_CONF_REG2_PORT_1 0x880C ///< SSIC Configuration Register 2 Port 1 455 #define R_PCH_XHCI_SSIC_CONF_REG3_PORT_1 0x8810 ///< SSIC Configuration Register 3 Port 1 456 #define R_PCH_XHCI_SSIC_CONF_REG1_PORT_2 0x8838 ///< SSIC Configuration Register 1 Port 2 457 #define R_PCH_XHCI_SSIC_CONF_REG2_PORT_2 0x883C ///< SSIC Configuration Register 2 Port 2 458 #define R_PCH_XHCI_SSIC_CONF_REG3_PORT_2 0x8840 ///< SSIC Configuration Register 3 Port 2 459 #define B_PCH_XHCI_SSIC_CONF_REG2_PORT_UNUSED BIT31 460 #define B_PCH_XHCI_SSIC_CONF_REG2_PROG_DONE BIT30 461 462 #define R_PCH_XHCI_SSIC_PROF_ATTR_PORT_1 0x8900 ///< Profile Attributes: Port 1 ... N 463 #define R_PCH_XHCI_SSIC_ACCESS_CONT_PORT_1 0x8904 ///< SSIC Port N Register Access Control: Port 1 464 #define R_PCH_XHCI_SSIC_PROF_ATTR_P1_0C 0x890C 465 #define R_PCH_XHCI_SSIC_PROF_ATTR_P1_10 0x8910 466 #define R_PCH_XHCI_SSIC_PROF_ATTR_P1_14 0x8914 467 #define R_PCH_XHCI_SSIC_PROF_ATTR_P1_18 0x8918 468 #define R_PCH_XHCI_SSIC_PROF_ATTR_P1_1C 0x891C 469 #define R_PCH_XHCI_SSIC_PROF_ATTR_P1_20 0x8920 470 #define R_PCH_XHCI_SSIC_PROF_ATTR_P1_24 0x8924 471 #define R_PCH_XHCI_SSIC_PROF_ATTR_P1_28 0x8928 472 473 #define R_PCH_XHCI_SSIC_PROF_ATTR_PORT_2 0x8A10 ///< Profile Attributes: Port 2 ... N 474 #define R_PCH_XHCI_SSIC_ACCESS_CONT_PORT_2 0x8A14 ///< SSIC Port N Register Access Control: Port 2 475 #define R_PCH_XHCI_SSIC_PROF_ATTR_P2_0C 0x8A1C 476 #define R_PCH_XHCI_SSIC_PROF_ATTR_P2_10 0x8A20 477 #define R_PCH_XHCI_SSIC_PROF_ATTR_P2_14 0x8A24 478 #define R_PCH_XHCI_SSIC_PROF_ATTR_P2_18 0x8A28 479 #define R_PCH_XHCI_SSIC_PROF_ATTR_P2_1C 0x8A2C 480 #define R_PCH_XHCI_SSIC_PROF_ATTR_P2_20 0x8A30 481 #define R_PCH_XHCI_SSIC_PROF_ATTR_P2_24 0x8A34 482 #define R_PCH_XHCI_SSIC_PROF_ATTR_P2_28 0x8A38 483 484 #endif 485