1 /** @file 2 QuarkNcSocId Register Definitions 3 4 Copyright (c) 2013-2015 Intel Corporation. 5 6 SPDX-License-Identifier: BSD-2-Clause-Patent 7 8 Definitions beginning with "R_" are registers 9 Definitions beginning with "B_" are bits within registers 10 Definitions beginning with "V_" are meaningful values of bits within the registers 11 Definitions beginning with "S_" are register sizes 12 Definitions beginning with "N_" are the bit position 13 14 **/ 15 16 #ifndef _QUARK_NC_SOC_ID_H_ 17 #define _QUARK_NC_SOC_ID_H_ 18 19 // 20 // QNC GMCH Equates 21 // 22 23 // 24 // DEVICE 0 (Memroy Controller Hub) 25 // 26 #define MC_BUS PCI_BUS_NUMBER_QNC 27 #define MC_DEV 0x00 28 #define MC_FUN 0x00 29 30 #define QUARK_MC_VENDOR_ID V_INTEL_VENDOR_ID 31 #define QUARK_MC_DEVICE_ID 0x0958 32 #define QUARK2_MC_DEVICE_ID 0x12C0 33 #define QNC_MC_REV_ID_A0 0x00 34 35 36 // 37 // MCR - B0:D0:F0:RD0h (WO)- Message control register 38 // [31:24] Message opcode - D0 read; E0 write; 39 // [23:16] Message port 40 // [15:8 ] Message target register address 41 // [ 7:4 ] Message write byte enable : F is enable 42 // [ 3:0 ] Reserved 43 // 44 #define QNC_ACCESS_PORT_MCR 0xD0 // Message Control Register 45 // Always Set to 0xF0 46 47 // 48 //MDR - B0:D0:F0:RD4h (RW)- Message data register 49 // 50 #define QNC_ACCESS_PORT_MDR 0xD4 // Message Data Register 51 52 // 53 //MEA - B0:D0:F0:RD8h (RW)- Message extended address register 54 // 55 #define QNC_ACCESS_PORT_MEA 0xD8 // Message Extended Address Register 56 57 #define QNC_MCR_OP_OFFSET 24 // Offset of the opcode field in MCR 58 #define QNC_MCR_PORT_OFFSET 16 // Offset of the port field in MCR 59 #define QNC_MCR_REG_OFFSET 8 // Offset of the register field in MCR 60 61 // 62 // Misc Useful Macros 63 // 64 65 #define LShift16(value) (value << 16) 66 67 // 68 // QNC Message OpCodes and Attributes 69 // 70 #define QUARK_OPCODE_READ 0x10 // Quark message bus "read" opcode 71 #define QUARK_OPCODE_WRITE 0x11 // Quark message bus "write" opcode 72 73 // 74 // Alternative opcodes for the SCSS block 75 // 76 #define QUARK_ALT_OPCODE_READ 0x06 // Quark message bus "read" opcode 77 #define QUARK_ALT_OPCODE_WRITE 0x07 // Quark message bus "write" opcode 78 79 // 80 // QNC Message OpCodes and Attributes for IO 81 // 82 #define QUARK_OPCODE_IO_READ 0x02 // Quark message bus "IO read" opcode 83 #define QUARK_OPCODE_IO_WRITE 0x03 // Quark message bus "IO write" opcode 84 85 86 #define QUARK_DRAM_BASE_ADDR_READY 0x78 // Quark message bus "RMU Main binary shadow" opcode 87 88 #define QUARK_ECC_SCRUB_RESUME 0xC2 // Quark Remote Management Unit "scrub resume" opcode 89 #define QUARK_ECC_SCRUB_PAUSE 0xC3 // Quark Remote Management Unit "scrub pause" opcode 90 91 // 92 // QNC Message Ports and Registers 93 // 94 // Start of SB Port IDs 95 #define QUARK_NC_MEMORY_ARBITER_SB_PORT_ID 0x00 96 #define QUARK_NC_MEMORY_CONTROLLER_SB_PORT_ID 0x01 97 #define QUARK_NC_HOST_BRIDGE_SB_PORT_ID 0x03 98 #define QUARK_NC_RMU_SB_PORT_ID 0x04 99 #define QUARK_NC_MEMORY_MANAGER_SB_PORT_ID 0x05 100 #define QUARK_SC_USB_AFE_SB_PORT_ID 0x14 101 #define QUARK_SC_PCIE_AFE_SB_PORT_ID 0x16 102 #define QUARK_SCSS_SOC_UNIT_SB_PORT_ID 0x31 103 #define QUARK_SCSS_FUSE_SB_PORT_ID 0x33 104 #define QUARK_ICLK_SB_PORT_ID 0x32 105 #define QUARK_SCSS_CRU_SB_PORT_ID 0x34 106 107 // 108 // Quark Memory Arbiter Registers. 109 // 110 #define QUARK_NC_MEMORY_ARBITER_REG_ASTATUS 0x21 // Memory Arbiter PRI Status encodings register. 111 #define ASTATUS_PRI_CASUAL 0x0 // Serviced only if convenient 112 #define ASTATUS_PRI_IMPENDING 0x1 // Serviced if the DRAM is in Self-Refresh. 113 #define ASTATUS_PRI_NORMAL 0x2 // Normal request servicing. 114 #define ASTATUS_PRI_URGENT 0x3 // Urgent request servicing. 115 #define ASTATUS1_RASISED_BP (10) 116 #define ASTATUS1_RASISED_BP_MASK (0x03 << ASTATUS1_RASISED_BP) 117 #define ASTATUS0_RASISED_BP (8) 118 #define ASTATUS0_RASISED_BP_MASK (0x03 << ASTATUS1_RASISED_BP) 119 #define ASTATUS1_DEFAULT_BP (2) 120 #define ASTATUS1_DEFAULT_BP_MASK (0x03 << ASTATUS1_RASISED_BP) 121 #define ASTATUS0_DEFAULT_BP (0) 122 #define ASTATUS0_DEFAULT_BP_MASK (0x03 << ASTATUS1_RASISED_BP) 123 124 // 125 // Quark Memory Controller Registers. 126 // 127 #define QUARK_NC_MEMORY_CONTROLLER_REG_DFUSESTAT 0x70 // Fuse status register. 128 #define B_DFUSESTAT_ECC_DIS (BIT0) // Disable ECC. 129 130 // 131 // Quark Remote Management Unit Registers. 132 // 133 #define QNC_MSG_TMPM_REG_PMBA 0x70 // Power Management I/O Base Address 134 135 #define QUARK_NC_RMU_REG_CONFIG 0x71 // Remote Management Unit configuration register. 136 #define TS_LOCK_AUX_TRIP_PT_REGS_ENABLE (BIT6) 137 #define TS_LOCK_THRM_CTRL_REGS_ENABLE (BIT5) 138 139 #define QUARK_NC_RMU_REG_OPTIONS_1 0x72 // Remote Management Unit Options register 1. 140 #define OPTIONS_1_DMA_DISABLE (BIT0) 141 142 #define QUARK_NC_RMU_REG_WDT_CONTROL 0x74 // Remote Management Unit Watchdog control register. 143 #define B_WDT_CONTROL_DBL_ECC_BIT_ERR_MASK (BIT19 | BIT18) 144 #define B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP 18 145 #define V_WDT_CONTROL_DBL_ECC_BIT_ERR_NONE (0x0 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP) 146 #define V_WDT_CONTROL_DBL_ECC_BIT_ERR_CAT (0x1 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP) 147 #define V_WDT_CONTROL_DBL_ECC_BIT_ERR_WARM (0x2 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP) 148 #define V_WDT_CONTROL_DBL_ECC_BIT_ERR_SERR (0x3 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP) 149 150 #define QUARK_NC_RMU_REG_TS_MODE 0xB0 // Remote Management Unit Thermal sensor mode register. 151 #define TS_ENABLE (BIT15) 152 #define QUARK_NC_RMU_REG_TS_TRIP 0xB2 // Remote Management Unit Thermal sensor programmable trip point register. 153 #define TS_HOT_TRIP_CLEAR_THOLD_BP 24 154 #define TS_HOT_TRIP_CLEAR_THOLD_MASK (0xFF << TS_HOT_TRIP_CLEAR_THOLD_BP) 155 #define TS_CAT_TRIP_CLEAR_THOLD_BP 16 156 #define TS_CAT_TRIP_CLEAR_THOLD_MASK (0xFF << TS_CAT_TRIP_CLEAR_THOLD_BP) 157 #define TS_HOT_TRIP_SET_THOLD_BP 8 158 #define TS_HOT_TRIP_SET_THOLD_MASK (0xFF << TS_HOT_TRIP_SET_THOLD_BP) 159 #define TS_CAT_TRIP_SET_THOLD_BP 0 160 #define TS_CAT_TRIP_SET_THOLD_MASK (0xFF << TS_CAT_TRIP_SET_THOLD_BP) 161 162 #define QUARK_NC_ECC_SCRUB_CONFIG_REG 0x50 163 #define SCRUB_CFG_INTERVAL_SHIFT 0x00 164 #define SCRUB_CFG_INTERVAL_MASK 0xFF 165 #define SCRUB_CFG_BLOCKSIZE_SHIFT 0x08 166 #define SCRUB_CFG_BLOCKSIZE_MASK 0x1F 167 #define SCRUB_CFG_ACTIVE (BIT13) 168 #define SCRUB_CFG_INVALID 0x00000FFF 169 170 #define QUARK_NC_ECC_SCRUB_START_MEM_REG 0x76 171 #define QUARK_NC_ECC_SCRUB_END_MEM_REG 0x77 172 #define QUARK_NC_ECC_SCRUB_NEXT_READ_REG 0x7C 173 174 #define SCRUB_RESUME_MSG() ((UINT32)( \ 175 (QUARK_ECC_SCRUB_RESUME << QNC_MCR_OP_OFFSET) | \ 176 (QUARK_NC_RMU_SB_PORT_ID << QNC_MCR_PORT_OFFSET) | \ 177 0xF0)) 178 179 #define SCRUB_PAUSE_MSG() ((UINT32)( \ 180 (QUARK_ECC_SCRUB_PAUSE << QNC_MCR_OP_OFFSET) | \ 181 (QUARK_NC_RMU_SB_PORT_ID << QNC_MCR_PORT_OFFSET) | \ 182 0xF0)) 183 184 // 185 // Quark Memory Manager Registers 186 // 187 #define QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK 0x82 188 #define BLOCK_ENABLE_PG (1 << 28) 189 #define BLOCK_DISABLE_PG (1 << 29) 190 #define QUARK_NC_MEMORY_MANAGER_BIMRVCTL 0x19 191 #define EnableIMRInt BIT31 192 #define QUARK_NC_MEMORY_MANAGER_BSMMVCTL 0x1C 193 #define EnableSMMInt BIT31 194 #define QUARK_NC_MEMORY_MANAGER_BTHCTRL 0x20 195 #define DRAM_NON_HOST_RQ_LIMIT_BP 0 196 #define DRAM_NON_HOST_RQ_LIMIT_MASK (0x3f << DRAM_NON_HOST_RQ_LIMIT_BP) 197 198 #define QUARK_NC_TOTAL_IMR_SET 0x8 199 #define QUARK_NC_MEMORY_MANAGER_IMR0 0x40 200 #define QUARK_NC_MEMORY_MANAGER_IMR1 0x44 201 #define QUARK_NC_MEMORY_MANAGER_IMR2 0x48 202 #define QUARK_NC_MEMORY_MANAGER_IMR3 0x4C 203 #define QUARK_NC_MEMORY_MANAGER_IMR4 0x50 204 #define QUARK_NC_MEMORY_MANAGER_IMR5 0x54 205 #define QUARK_NC_MEMORY_MANAGER_IMR6 0x58 206 #define QUARK_NC_MEMORY_MANAGER_IMR7 0x5C 207 #define QUARK_NC_MEMORY_MANAGER_IMRXL 0x00 208 #define IMR_LOCK BIT31 209 #define IMR_EN BIT30 210 #define IMRL_MASK 0x00FFFFFC 211 #define IMRL_RESET 0x00000000 212 #define QUARK_NC_MEMORY_MANAGER_IMRXH 0x01 213 #define IMRH_MASK 0x00FFFFFC 214 #define IMRH_RESET 0x00000000 215 #define QUARK_NC_MEMORY_MANAGER_IMRXRM 0x02 216 #define QUARK_NC_MEMORY_MANAGER_IMRXWM 0x03 217 #define IMRX_ALL_ACCESS 0xFFFFFFFF 218 #define CPU_SNOOP BIT30 219 #define RMU BIT29 220 #define CPU0_NON_SMM BIT0 221 222 // 223 // Quark Host Bridge Registers 224 // 225 #define QNC_MSG_FSBIC_REG_HMISC 0x03 // Host Misellaneous Controls 226 #define SMI_EN (BIT19) // SMI Global Enable (from Legacy Bridge) 227 #define QNC_MSG_FSBIC_REG_HSMMC 0x04 // Host SMM Control 228 #define NON_HOST_SMM_WR_OPEN (BIT18) // SMM Writes OPEN 229 #define NON_HOST_SMM_RD_OPEN (BIT17) // SMM Writes OPEN 230 #define SMM_CODE_RD_OPEN (BIT16) // SMM Code read OPEN 231 #define SMM_CTL_EN (BIT3) // SMM enable 232 #define SMM_WRITE_OPEN (BIT2) // SMM Writes OPEN 233 #define SMM_READ_OPEN (BIT1) // SMM Reads OPEN 234 #define SMM_LOCKED (BIT0) // SMM Locked 235 #define SMM_START_MASK 0x0000FFF0 236 #define SMM_END_MASK 0xFFF00000 237 #define QUARK_NC_HOST_BRIDGE_HMBOUND_REG 0x08 238 #define HMBOUND_MASK 0x0FFFFF000 239 #define HMBOUND_LOCK BIT0 240 #define QUARK_NC_HOST_BRIDGE_HLEGACY_REG 0x0A 241 #define HLEGACY_SMI_PIN_VALUE BIT12 242 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP 0x40 243 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE 0x41 244 #define QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000 0x42 245 #define QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_80000 0x44 246 #define QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_A0000 0x46 247 #define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_C0000 0x48 248 #define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_C8000 0x4A 249 #define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_D0000 0x4C 250 #define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_D8000 0x4E 251 #define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_E0000 0x50 252 #define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_E8000 0x52 253 #define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F0000 0x54 254 #define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000 0x56 255 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSBASE 0x58 256 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK 0x59 257 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0 0x5A 258 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK0 0x5B 259 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE1 0x5C 260 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK1 0x5D 261 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE2 0x5E 262 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK2 0x5F 263 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE3 0x60 264 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK3 0x61 265 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE4 0x62 266 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK4 0x63 267 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE5 0x64 268 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK5 0x65 269 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE6 0x66 270 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK6 0x67 271 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE7 0x68 272 #define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK7 0x69 273 274 // 275 // System On Chip Unit (SOCUnit) Registers. 276 // 277 #define QUARK_SCSS_SOC_UNIT_STPDDRCFG 0x00 278 #define B_STPDDRCFG_FORCE_RECOVERY BIT0 279 #define QUARK_SCSS_SOC_UNIT_SPI_ROM_FUSE 0x25 280 #define B_ROM_FUSE_IN_SECURE_SKU BIT6 281 282 #define QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG 0x31 283 #define B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK (BIT5 | BIT4 | BIT3) 284 #define B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP 3 285 #define B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK (BIT12 | BIT11 | BIT10 | BIT9 | BIT8) 286 #define B_TSCGF1_CONFIG_ISNSCHOPSEL_BP 8 287 #define B_TSCGF1_CONFIG_IBGEN BIT17 288 #define B_TSCGF1_CONFIG_IBGEN_BP 17 289 #define B_TSCGF1_CONFIG_IBGCHOPEN BIT18 290 #define B_TSCGF1_CONFIG_IBGCHOPEN_BP 18 291 #define B_TSCGF1_CONFIG_ISNSINTERNALVREFEN BIT14 292 #define B_TSCGF1_CONFIG_ISNSINTERNALVREFEN_BP 14 293 294 #define QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG 0x32 295 #define B_TSCGF2_CONFIG_IDSCONTROL_MASK 0x0000FFFF 296 #define B_TSCGF2_CONFIG_IDSCONTROL_BP 0 297 #define B_TSCGF2_CONFIG_IDSTIMING_MASK 0xFFFF0000 298 #define B_TSCGF2_CONFIG_IDSTIMING_BP 16 299 300 #define QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2 0x33 301 #define B_TSCGF2_CONFIG2_ISPARECTRL_MASK 0xFF000000 302 #define B_TSCGF2_CONFIG2_ISPARECTRL_BP 24 303 #define B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK (BIT9 | BIT8) 304 #define B_TSCGF2_CONFIG2_ICALCONFIGSEL_BP 8 305 #define B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK 0x000000FF 306 #define B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP 0 307 308 #define QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG 0x34 309 #define B_TSCGF3_CONFIG_ITSRST BIT0 310 #define B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP 11 311 #define B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK (0xFFF << B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP) 312 313 #define QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG 0x36 314 #define SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L BIT20 315 #define SOCCLKEN_CONFIG_PHY_I_CMNRESET_L BIT19 316 #define SOCCLKEN_CONFIG_SBI_BB_RST_B BIT18 317 #define SOCCLKEN_CONFIG_SBI_RST_100_CORE_B BIT17 318 #define SOCCLKEN_CONFIG_BB_RST_B BIT16 319 320 #define QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG 0x36 321 322 #define QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW 0x51 323 #define B_CFG_STICKY_RW_SMM_VIOLATION BIT0 324 #define B_CFG_STICKY_RW_HMB_VIOLATION BIT1 325 #define B_CFG_STICKY_RW_IMR_VIOLATION BIT2 326 #define B_CFG_STICKY_RW_DECC_VIOLATION BIT3 327 #define B_CFG_STICKY_RW_WARM_RST BIT4 328 #define B_CFG_STICKY_RW_FORCE_RECOVERY BIT9 329 #define B_CFG_STICKY_RW_VIOLATION (B_CFG_STICKY_RW_SMM_VIOLATION | B_CFG_STICKY_RW_HMB_VIOLATION | B_CFG_STICKY_RW_IMR_VIOLATION | B_CFG_STICKY_RW_DECC_VIOLATION) 330 #define B_CFG_STICKY_RW_ALL (B_CFG_STICKY_RW_VIOLATION | B_CFG_STICKY_RW_WARM_RST) 331 332 // 333 // iCLK Registers. 334 // 335 #define QUARK_ICLK_MUXTOP 0x0140 336 #define B_MUXTOP_FLEX2_MASK (BIT25 | BIT24 | BIT23) 337 #define B_MUXTOP_FLEX2_BP 23 338 #define B_MUXTOP_FLEX1_MASK (BIT22 | BIT21 | BIT20) 339 #define B_MUXTOP_FLEX1_BP 20 340 341 #define QUARK_ICLK_SSC1 0x0314 342 #define QUARK_ICLK_SSC2 0x0414 343 #define QUARK_ICLK_SSC3 0x0514 344 #define QUARK_ICLK_REF2_DBUFF0 0x2000 345 346 // 347 // PCIe AFE Unit Registers (QUARK_SC_PCIE_AFE_SB_PORT_ID). 348 // 349 #define QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0 0x2080 350 #define QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1 0x2180 351 #define OCFGPIMIXLOAD_1_0 BIT6 352 #define OCFGPIMIXLOAD_1_0_MASK 0xFFFFFF3F 353 354 // 355 // QNC ICH Equates 356 // 357 #define V_INTEL_VENDOR_ID 0x8086 358 359 #define PCI_BUS_NUMBER_QNC 0x00 360 361 // 362 // PCI to LPC Bridge Registers (D31:F0) 363 // 364 #define PCI_DEVICE_NUMBER_QNC_LPC 31 365 #define PCI_FUNCTION_NUMBER_QNC_LPC 0 366 367 #define R_QNC_LPC_VENDOR_ID 0x00 368 #define V_LPC_VENDOR_ID V_INTEL_VENDOR_ID 369 #define R_QNC_LPC_DEVICE_ID 0x02 370 #define QUARK_V_LPC_DEVICE_ID_0 0x095E 371 #define R_QNC_LPC_REV_ID 0x08 372 373 #define R_QNC_LPC_SMBUS_BASE 0x40 //~0x43 374 #define B_QNC_LPC_SMBUS_BASE_EN (BIT31) 375 #define B_QNC_LPC_SMBUS_BASE_MASK 0x0000FFC0 //[15:6] 376 // 377 // SMBus register offsets from SMBA - "SMBA" (D31:F0:R40h) 378 // Suggested Value for SMBA = 0x1040 379 // 380 #define R_QNC_SMBUS_HCTL 0x00 // Host Control Register R/W 381 #define B_QNC_SMBUS_START (BIT4) // Start/Stop 382 #define V_QNC_SMBUS_HCTL_CMD_QUICK 0 383 #define V_QNC_SMBUS_HCTL_CMD_BYTE 1 384 #define V_QNC_SMBUS_HCTL_CMD_BYTE_DATA 2 385 #define V_QNC_SMBUS_HCTL_CMD_WORD_DATA 3 386 #define V_QNC_SMBUS_HCTL_CMD_PROCESS_CALL 4 387 #define V_QNC_SMBUS_HCTL_CMD_BLOCK 5 388 389 #define R_QNC_SMBUS_HSTS 0x01 // Host Status Register R/W 390 #define B_QNC_SMBUS_BERR (BIT2) // BUS Error 391 #define B_QNC_SMBUS_DERR (BIT1) // Device Error 392 #define B_QNC_SMBUS_BYTE_DONE_STS (BIT0) // Completion Status 393 #define B_QNC_SMBUS_HSTS_ALL 0x07 394 395 #define R_QNC_SMBUS_HCLK 0x02 // Host Clock Divider Register R/W 396 #define V_QNC_SMBUS_HCLK_100KHZ 0x0054 397 398 #define R_QNC_SMBUS_TSA 0x04 // Transmit Slave Address Register R/W 399 #define V_QNC_SMBUS_RW_SEL_READ 1 400 #define V_QNC_SMBUS_RW_SEL_WRITE 0 401 402 #define R_QNC_SMBUS_HCMD 0x05 // Host Command Register R/W 403 #define R_QNC_SMBUS_HD0 0x06 // Data 0 Register R/W 404 #define R_QNC_SMBUS_HD1 0x07 // Data 1 Register R/W 405 #define R_QNC_SMBUS_HBD 0x20 // Host Block Data Register R/W [255:0] ~ 3Fh 406 407 #define R_QNC_LPC_GBA_BASE 0x44 408 #define B_QNC_LPC_GPA_BASE_MASK 0x0000FFC0 409 // 410 // GPIO register offsets from GBA - "GPIO" (D31:F0:R44h) 411 // Suggested Value for GBA = 0x1080 412 // 413 #define R_QNC_GPIO_CGEN_CORE_WELL 0x00 414 #define R_QNC_GPIO_CGIO_CORE_WELL 0x04 415 #define R_QNC_GPIO_CGLVL_CORE_WELL 0x08 416 #define R_QNC_GPIO_CGTPE_CORE_WELL 0x0C // Core well GPIO Trigger Positive Edge Enable 417 #define R_QNC_GPIO_CGTNE_CORE_WELL 0x10 // Core well GPIO Trigger Negative Edge Enable 418 #define R_QNC_GPIO_CGGPE_CORE_WELL 0x14 // Core well GPIO GPE Enable 419 #define R_QNC_GPIO_CGSMI_CORE_WELL 0x18 // Core well GPIO SMI Enable 420 #define R_QNC_GPIO_CGTS_CORE_WELL 0x1C // Core well GPIO Trigger Status 421 #define R_QNC_GPIO_RGEN_RESUME_WELL 0x20 422 #define R_QNC_GPIO_RGIO_RESUME_WELL 0x24 423 #define R_QNC_GPIO_RGLVL_RESUME_WELL 0x28 424 #define R_QNC_GPIO_RGTPE_RESUME_WELL 0x2C // Resume well GPIO Trigger Positive Edge Enable 425 #define R_QNC_GPIO_RGTNE_RESUME_WELL 0x30 // Resume well GPIO Trigger Negative Edge Enable 426 #define R_QNC_GPIO_RGGPE_RESUME_WELL 0x34 // Resume well GPIO GPE Enable 427 #define R_QNC_GPIO_RGSMI_RESUME_WELL 0x38 // Resume well GPIO SMI Enable 428 #define R_QNC_GPIO_RGTS_RESUME_WELL 0x3C // Resume well GPIO Trigger Status 429 #define R_QNC_GPIO_CNMIEN_CORE_WELL 0x40 // Core well GPIO NMI Enable 430 #define R_QNC_GPIO_RNMIEN_RESUME_WELL 0x44 // Resume well GPIO NMI Enable 431 432 #define R_QNC_LPC_PM1BLK 0x48 433 #define B_QNC_LPC_PM1BLK_MASK 0x0000FFF0 434 // 435 // ACPI register offsets from PM1BLK - "ACPI PM1 Block" (D31:F0:R48h) 436 // Suggested Value for PM1BLK = 0x1000 437 // 438 #define R_QNC_PM1BLK_PM1S 0x00 439 #define S_QNC_PM1BLK_PM1S 2 440 #define B_QNC_PM1BLK_PM1S_ALL (BIT15+BIT14+BIT10+BIT5+BIT0) 441 #define B_QNC_PM1BLK_PM1S_WAKE (BIT15) 442 #define B_QNC_PM1BLK_PM1S_PCIEWSTS (BIT14) 443 #define B_QNC_PM1BLK_PM1S_RTC (BIT10) 444 #define B_QNC_PM1BLK_PM1S_GLOB (BIT5) 445 #define B_QNC_PM1BLK_PM1S_TO (BIT0) 446 #define N_QNC_PM1BLK_PM1S_RTC 10 447 448 449 #define R_QNC_PM1BLK_PM1E 0x02 450 #define S_QNC_PM1BLK_PM1E 2 451 #define B_QNC_PM1BLK_PM1E_PWAKED (BIT14) 452 #define B_QNC_PM1BLK_PM1E_RTC (BIT10) 453 #define B_QNC_PM1BLK_PM1E_GLOB (BIT5) 454 #define N_QNC_PM1BLK_PM1E_RTC 10 455 456 #define R_QNC_PM1BLK_PM1C 0x04 457 #define B_QNC_PM1BLK_PM1C_SLPEN (BIT13) 458 #define B_QNC_PM1BLK_PM1C_SLPTP (BIT12+BIT11+BIT10) 459 #define V_S0 0x00000000 460 #define V_S3 0x00001400 461 #define V_S4 0x00001800 462 #define V_S5 0x00001C00 463 #define B_QNC_PM1BLK_PM1C_SCIEN (BIT0) 464 465 #define R_QNC_PM1BLK_PM1T 0x08 466 467 #define R_QNC_LPC_GPE0BLK 0x4C 468 #define B_QNC_LPC_GPE0BLK_MASK 0x0000FFC0 469 // Suggested Value for GPE0BLK = 0x10C0 470 // 471 #define R_QNC_GPE0BLK_GPE0S 0x00 // General Purpose Event 0 Status 472 #define S_QNC_GPE0BLK_GPE0S 4 473 #define B_QNC_GPE0BLK_GPE0S_ALL 0x00003F800 // used to clear the status reg 474 #define B_QNC_GPE0BLK_GPE0S_PCIE (BIT17) // PCIE 475 #define B_QNC_GPE0BLK_GPE0S_GPIO (BIT14) // GPIO 476 #define B_QNC_GPE0BLK_GPE0S_EGPE (BIT13) // External GPE 477 #define N_QNC_GPE0BLK_GPE0S_THRM 12 478 479 #define R_QNC_GPE0BLK_GPE0E 0x04 // General Purpose Event 0 Enable 480 #define S_QNC_GPE0BLK_GPE0E 4 481 #define B_QNC_GPE0BLK_GPE0E_PCIE (BIT17) // PCIE 482 #define B_QNC_GPE0BLK_GPE0E_GPIO (BIT14) // GPIO 483 #define B_QNC_GPE0BLK_GPE0E_EGPE (BIT13) // External GPE 484 #define N_QNC_GPE0BLK_GPE0E_THRM 12 485 486 #define R_QNC_GPE0BLK_SMIE 0x10 // SMI_B Enable 487 #define S_QNC_GPE0BLK_SMIE 4 488 #define B_QNC_GPE0BLK_SMIE_ALL 0x0003871F 489 #define B_QNC_GPE0BLK_SMIE_APM (BIT4) // APM 490 #define B_QNC_GPE0BLK_SMIE_SLP (BIT2) // Sleep 491 #define B_QNC_GPE0BLK_SMIE_SWT (BIT1) // Software Timer 492 #define N_QNC_GPE0BLK_SMIE_GPIO 9 493 #define N_QNC_GPE0BLK_SMIE_ESMI 8 494 #define N_QNC_GPE0BLK_SMIE_APM 4 495 #define N_QNC_GPE0BLK_SMIE_SPI 3 496 #define N_QNC_GPE0BLK_SMIE_SLP 2 497 #define N_QNC_GPE0BLK_SMIE_SWT 1 498 499 #define R_QNC_GPE0BLK_SMIS 0x14 // SMI Status Register. 500 #define S_QNC_GPE0BLK_SMIS 4 501 #define B_QNC_GPE0BLK_SMIS_ALL 0x0003871F 502 #define B_QNC_GPE0BLK_SMIS_EOS (BIT31) // End of SMI 503 #define B_QNC_GPE0BLK_SMIS_APM (BIT4) // APM 504 #define B_QNC_GPE0BLK_SMIS_SPI (BIT3) // SPI 505 #define B_QNC_GPE0BLK_SMIS_SLP (BIT2) // Sleep 506 #define B_QNC_GPE0BLK_SMIS_SWT (BIT1) // Software Timer 507 #define B_QNC_GPE0BLK_SMIS_BIOS (BIT0) // BIOS 508 #define N_QNC_GPE0BLK_SMIS_GPIO 9 509 #define N_QNC_GPE0BLK_SMIS_APM 4 510 #define N_QNC_GPE0BLK_SMIS_SPI 3 511 #define N_QNC_GPE0BLK_SMIS_SLP 2 512 #define N_QNC_GPE0BLK_SMIS_SWT 1 513 514 #define R_QNC_GPE0BLK_PMCW 0x28 // Power Management Configuration Core Well 515 #define B_QNC_GPE0BLK_PMCW_PSE (BIT31) // Periodic SMI Enable 516 517 #define R_QNC_GPE0BLK_PMSW 0x2C // Power Management Configuration Suspend/Resume Well 518 #define B_QNC_GPE0BLK_PMSW_DRAM_INIT (BIT0) // Dram Initialization Sctrachpad 519 520 #define R_QNC_LPC_ACTL 0x58 521 #define V_QNC_LPC_ACTL_SCIS_IRQ9 0x00 522 523 // 524 // Number of PIRQs supported. PIRQA~PIRQH 525 // 526 #define QNC_NUMBER_PIRQS 8 527 #define R_QNC_LPC_PIRQA_ROUT 0x60 528 #define R_QNC_LPC_PIRQB_ROUT 0x61 529 #define R_QNC_LPC_PIRQC_ROUT 0x62 530 #define R_QNC_LPC_PIRQD_ROUT 0x63 531 #define R_QNC_LPC_PIRQE_ROUT 0x64 532 #define R_QNC_LPC_PIRQF_ROUT 0x65 533 #define R_QNC_LPC_PIRQG_ROUT 0x66 534 #define R_QNC_LPC_PIRQH_ROUT 0x67 535 536 // 537 // Bit values are the same for R_TNC_LPC_PIRQA_ROUT to 538 // R_TNC_LPC_PIRQH_ROUT 539 #define B_QNC_LPC_PIRQX_ROUT (BIT3+BIT2+BIT1+BIT0) 540 541 #define R_QNC_LPC_WDTBA 0x84 542 // Watchdog Timer register offsets from WDTBASE (in R_QNC_LPC_WDTBA)------------BEGIN 543 #define R_QNC_LPC_WDT_WDTCR 0x10 544 #define R_QNC_LPC_WDT_WDTLR 0x18 545 // Watchdog Timer register offsets from WDTBASE (in R_QNC_LPC_WDTBA)--------------END 546 547 #define R_QNC_LPC_FWH_BIOS_DEC 0xD4 548 #define B_QNC_LPC_FWH_BIOS_DEC_F8 (BIT31) 549 #define B_QNC_LPC_FWH_BIOS_DEC_F0 (BIT30) 550 #define B_QNC_LPC_FWH_BIOS_DEC_E8 (BIT29) 551 #define B_QNC_LPC_FWH_BIOS_DEC_E0 (BIT28) 552 #define B_QNC_LPC_FWH_BIOS_DEC_D8 (BIT27) 553 #define B_QNC_LPC_FWH_BIOS_DEC_D0 (BIT26) 554 #define B_QNC_LPC_FWH_BIOS_DEC_C8 (BIT25) 555 #define B_QNC_LPC_FWH_BIOS_DEC_C0 (BIT24) 556 557 #define R_QNC_LPC_BIOS_CNTL 0xD8 558 #define S_QNC_LPC_BIOS_CNTL 4 559 #define B_QNC_LPC_BIOS_CNTL_PFE (BIT8) 560 #define B_QNC_LPC_BIOS_CNTL_SMM_BWP (BIT5) 561 #define B_QNC_LPC_BIOS_CNTL_BCD (BIT2) 562 #define B_QNC_LPC_BIOS_CNTL_BLE (BIT1) 563 #define B_QNC_LPC_BIOS_CNTL_BIOSWE (BIT0) 564 #define N_QNC_LPC_BIOS_CNTL_BLE 1 565 #define N_QNC_LPC_BIOS_CNTL_BIOSWE 0 566 567 #define R_QNC_LPC_RCBA 0xF0 568 #define B_QNC_LPC_RCBA_MASK 0xFFFFC000 569 #define B_QNC_LPC_RCBA_EN (BIT0) 570 571 //--------------------------------------------------------------------------- 572 // Fixed IO Decode on QuarkNcSocId 573 // 574 // 20h(2B) 24h(2B) 28h(2B) 2Ch(2B) 30h(2B) 34h(2B) 38h(2B) 3Ch(2B) : R/W 8259 master 575 // 40h(3B): R/W 8254 576 // 43h(1B): W 8254 577 // 50h(3B): R/W 8254 578 // 53h(1B): W 8254 579 // 61h(1B): R/W NMI Controller 580 // 63h(1B): R/W NMI Controller - can be disabled 581 // 65h(1B): R/W NMI Controller - can be disabled 582 // 67h(1B): R/W NMI Controller - can be disabled 583 // 70h(1B): W NMI & RTC 584 // 71h(1B): R/W RTC 585 // 72h(1B): R RTC; W NMI&RTC 586 // 73h(1B): R/W RTC 587 // 74h(1B): R RTC; W NMI&RTC 588 // 75h(1B): R/W RTC 589 // 76h(1B): R RTC; W NMI&RTC 590 // 77h(1B): R/W RTC 591 // 84h(3B): R/W Internal/LPC 592 // 88h(1B): R/W Internal/LPC 593 // 8Ch(3B): R/W Internal/LPC 594 // A0h(2B) A4h(2B) A8h(2B) ACh(2B) B0h(2B) B4h(2B) B8h(2B) BCh(2B): R/W 8259 slave 595 // B2h(1B) B3h(1B): R/W Power management 596 // 3B0h-3BBh: R/W VGA 597 // 3C0h-3DFh: R/W VGA 598 // CF8h(4B): R/W Internal 599 // CF9h(1B): R/W LPC 600 // CFCh(4B): R/W Internal 601 //--------------------------------------------------------------------------- 602 603 #define R_APM_CNT 0xB2 604 605 // 606 // Reset Generator I/O Port 607 // 608 #define RST_CNT 0xCF9 609 #define B_RST_CNT_COLD_RST (BIT3) // Cold reset 610 #define B_RST_CNT_WARM_RST (BIT1) // Warm reset 611 612 // 613 // Processor interface registers (NMI) 614 // 615 616 #define PCI_DEVICE_NUMBER_QNC_IOSF2AHB_0 20 617 #define PCI_DEVICE_NUMBER_QNC_IOSF2AHB_1 21 618 #define PCI_FUNCTION_NUMBER_QNC_IOSF2AHB 0 619 620 // 621 // Pci Express Root Ports (D23:F0/F1) 622 // 623 #define PCI_DEVICE_NUMBER_PCIE_ROOTPORT 23 624 #define PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_0 0 625 #define PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_1 1 626 627 #define MAX_PCI_EXPRESS_ROOT_PORTS 2 628 629 #define R_QNC_PCIE_BNUM 0x18 630 #define R_QNC_PCIE_CAP_PTR 0x34 631 632 #define PCIE_CAPID 0x10 //PCIE Capability ID 633 #define PCIE_CAP_EXT_HEARDER_OFFSET 0x100 //PCIE Capability ID 634 #define PCIE_DEV_CAP_OFFSET 0x04 //PCIE Device Capability reg offset 635 #define PCIE_LINK_CAP_OFFSET 0x0C //PCIE Link Capability reg offset 636 #define PCIE_LINK_CNT_OFFSET 0x10 //PCIE Link control reg offset 637 #define PCIE_LINK_STS_OFFSET 0x12 //PCIE Link status reg offset 638 #define PCIE_SLOT_CAP_OFFSET 0x14 //PCIE Link Capability reg offset 639 640 #define R_QNC_PCIE_XCAP 0x42 //~ 43h 641 #define B_QNC_PCIE_XCAP_SI (BIT8) //slot implemented 642 #define R_QNC_PCIE_DCAP 0x44 //~ 47h 643 #define B_QNC_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9) // L1 Acceptable exit latency 644 #define B_QNC_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6) // L0 Acceptable exit latency 645 #define R_QNC_PCIE_DCTL 0x48 //~ 49h 646 #define B_QNC_PCIE_DCTL_URE (BIT3) //Unsupported Request Reporting Enable 647 #define B_QNC_PCIE_DCTL_FEE (BIT2) //Fatal error Reporting Enable 648 #define B_QNC_PCIE_DCTL_NFE (BIT1) //Non Fatal error Reporting Enable 649 #define B_QNC_PCIE_DCTL_CEE (BIT0) //Correctable error Reporting Enable 650 #define R_QNC_PCIE_LCAP 0x4C //~ 4Fh 651 #define B_QNC_PCIE_LCAP_CPM (BIT18) //clock power management supported 652 #define B_QNC_PCIE_LCAP_EL1_MASK (BIT17 | BIT16 | BIT15) //L1 Exit latency mask 653 #define B_QNC_PCIE_LCAP_EL0_MASK (BIT14 | BIT13 | BIT12) //L0 Exit latency mask 654 #define B_QNC_PCIE_LCAP_APMS_MASK (BIT11 | BIT10) //Active state link PM support mask 655 #define V_QNC_PCIE_LCAP_APMS_OFFSET 10 //Active state link PM support mask 656 #define R_QNC_PCIE_LCTL 0x50 //~ 51h 657 #define B_QNC_PCIE_LCTL_CCC (BIT6) // Clock clock configuration 658 #define B_QNC_PCIE_LCTL_RL (BIT5) // Retrain link 659 #define R_QNC_PCIE_LSTS 0x52 //~ 53h 660 #define B_QNC_PCIE_LSTS_SCC (BIT12) //Slot clock configuration 661 #define B_QNC_PCIE_LSTS_LT (BIT11) //Link training 662 #define R_QNC_PCIE_SLCAP 0x54 //~ 57h 663 #define B_QNC_PCIE_SLCAP_MASK_RSV_VALUE 0x0006007F 664 #define V_QNC_PCIE_SLCAP_SLV 0x0A //Slot power limit value [14:7] 665 #define V_QNC_PCIE_SLCAP_SLV_OFFSET 7 //Slot power limit value offset is 7 [14:7] 666 #define V_QNC_PCIE_SLCAP_PSN_OFFSET 19 //Slot number offset is 19 [31:19] 667 #define R_QNC_PCIE_SLCTL 0x58 //~ 59h 668 #define B_QNC_PCIE_SLCTL_HPE (BIT5) // Hot plug interrupt enable 669 #define B_QNC_PCIE_SLCTL_PDE (BIT3) // Presense detect change enable 670 #define B_QNC_PCIE_SLCTL_ABE (BIT0) // Attention Button Pressed Enable 671 #define R_QNC_PCIE_SLSTS 0x5A //~ 5Bh 672 #define B_QNC_PCIE_SLSTS_PDS (BIT6) // Present Detect State = 1b : has device connected 673 #define B_QNC_PCIE_SLSTS_PDC (BIT3) // Present Detect changed = 1b : PDS state has changed 674 #define B_QNC_PCIE_SLSTS_ABP (BIT0) // Attention Button Pressed 675 #define R_QNC_PCIE_RCTL 0x5C //~ 5Dh 676 #define B_QNC_PCIE_RCTL_PIE (BIT3) //Root PCI-E PME Interrupt Enable 677 #define B_QNC_PCIE_RCTL_SFE (BIT2) //Root PCI-E System Error on Fatal Error Enable 678 #define B_QNC_PCIE_RCTL_SNE (BIT1) //Root PCI-E System Error on Non-Fatal Error Enable 679 #define B_QNC_PCIE_RCTL_SCE (BIT0) //Root PCI-E System Error on Correctable Error Enable 680 #define R_QNC_PCIE_SVID 0x94 //~ 97h 681 #define R_QNC_PCIE_CCFG 0xD0 //~ D3h 682 #define B_QNC_PCIE_CCFG_UPSD (BIT24) // Upstream Posted Split Disable 683 #define B_QNC_PCIE_CCFG_UNRS (BIT15) // Upstream Non-Posted Request Size 684 #define B_QNC_PCIE_CCFG_UPRS (BIT14) // Upstream Posted Request Size 685 #define R_QNC_PCIE_MPC2 0xD4 //~ D7h 686 #define B_QNC_PCIE_MPC2_IPF (BIT11) // ISOF Packet Fast Transmit Mode 687 #define R_QNC_PCIE_MPC 0xD8 //~ DBh 688 #define B_QNC_PCIE_MPC_PMCE (BIT31) // PM SCI Enable 689 #define B_QNC_PCIE_MPC_HPCE (BIT30) // Hot plug SCI enable 690 691 #define B_QNC_PCIE_MPC_HPME (BIT1) // Hot plug SMI enable 692 #define B_QNC_PCIE_MPC_PMME (BIT0) // PM SMI Enable 693 #define R_QNC_PCIE_IOSFSBCTL 0xF6 694 #define B_QNC_PCIE_IOSFSBCTL_SBIC_MASK (BIT1 | BIT0) // IOSF Sideband ISM Idle Counter. 695 #define B_QNC_PCIE_IOSFSBCTL_SBIC_IDLE_NEVER (BIT1 | BIT0) // Never transition to IDLE. 696 697 #define V_PCIE_MAX_TRY_TIMES 200 698 699 // 700 // Misc PCI register offsets and sizes 701 // 702 #define R_EFI_PCI_SVID 0x2C 703 704 // 705 // IO_APIC 706 // 707 #define IOAPIC_BASE 0xFEC00000 708 #define IOAPIC_SIZE 0x1000 709 710 // 711 // Chipset configuration registers RCBA - "Root Complex Base Address" (D31:F0:RF0h) 712 // Suggested Value for RCBA = 0xFED1C000 713 // 714 715 #define R_QNC_RCRB_SPIBASE 0x3020 // SPI (Serial Peripheral Interface) in RCRB 716 #define R_QNC_RCRB_SPIS (R_QNC_RCRB_SPIBASE + 0x00) // SPI Status 717 #define B_QNC_RCRB_SPIS_SCL (BIT15) // SPI Configuration Lockdown 718 #define B_QNC_RCRB_SPIS_BAS (BIT3) // Blocked Access Status 719 #define B_QNC_RCRB_SPIS_CDS (BIT2) // Cycle Done Status 720 #define B_QNC_RCRB_SPIS_SCIP (BIT0) // SPI Cycle in Progress 721 722 #define R_QNC_RCRB_SPIC (R_QNC_RCRB_SPIBASE + 0x02) // SPI Control 723 #define B_QNC_RCRB_SPIC_DC (BIT14) // SPI Data Cycle Enable 724 #define B_QNC_RCRB_SPIC_DBC 0x3F00 // SPI Data Byte Count (1..8,16,24,32,40,48,56,64) 725 #define B_QNC_RCRB_SPIC_COP (BIT6+BIT5+BIT4) // SPI Cycle Opcode Pointer 726 #define B_QNC_RCRB_SPIC_SPOP (BIT3) // Sequence Prefix Opcode Pointer 727 #define B_QNC_RCRB_SPIC_ACS (BIT2) // SPI Atomic Cycle Sequence 728 #define B_QNC_RCRB_SPIC_SCGO (BIT1) // SPI Cycle Go 729 730 #define R_QNC_RCRB_SPIA (R_QNC_RCRB_SPIBASE + 0x04) // SPI Address 731 #define B_QNC_RCRB_SPIA_MASK 0x00FFFFFF // SPI Address mask 732 #define R_QNC_RCRB_SPID0 (R_QNC_RCRB_SPIBASE + 0x08) // SPI Data 0 733 #define R_QNC_RCRB_SPIPREOP (R_QNC_RCRB_SPIBASE + 0x54) // Prefix Opcode Configuration 734 #define R_QNC_RCRB_SPIOPTYPE (R_QNC_RCRB_SPIBASE + 0x56) // Opcode Type Configuration 735 #define B_QNC_RCRB_SPIOPTYPE_NOADD_READ 0 736 #define B_QNC_RCRB_SPIOPTYPE_NOADD_WRITE (BIT0) 737 #define B_QNC_RCRB_SPIOPTYPE_ADD_READ (BIT1) 738 #define B_QNC_RCRB_SPIOPTYPE_ADD_WRITE (BIT0 + BIT1) 739 #define R_QNC_RCRB_SPIOPMENU (R_QNC_RCRB_SPIBASE + 0x58) // Opcode Menu Configuration //R_OPMENU 740 741 #define R_QNC_RCRB_SPIPBR0 (R_QNC_RCRB_SPIBASE + 0x60) // Protected BIOS Range 0. 742 #define R_QNC_RCRB_SPIPBR1 (R_QNC_RCRB_SPIBASE + 0x64) // Protected BIOS Range 1. 743 #define R_QNC_RCRB_SPIPBR2 (R_QNC_RCRB_SPIBASE + 0x68) // Protected BIOS Range 2. 744 #define B_QNC_RCRB_SPIPBRn_WPE (BIT31) // Write Protection Enable for above 3 registers. 745 746 #define R_QNC_RCRB_AGENT0IR 0x3140 // AGENT0 interrupt route 747 #define R_QNC_RCRB_AGENT1IR 0x3142 // AGENT1 interrupt route 748 #define R_QNC_RCRB_AGENT2IR 0x3144 // AGENT2 interrupt route 749 #define R_QNC_RCRB_AGENT3IR 0x3146 // AGENT3 interrupt route 750 751 #endif 752