1 /** @file 2 Register names for PCH PMC device 3 4 Conventions: 5 6 - Register definition format: 7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName 8 - Prefix: 9 Definitions beginning with "R_" are registers 10 Definitions beginning with "B_" are bits within registers 11 Definitions beginning with "V_" are meaningful values within the bits 12 Definitions beginning with "S_" are register size 13 Definitions beginning with "N_" are the bit position 14 - [GenerationName]: 15 Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). 16 Register name without GenerationName applies to all generations. 17 - [ComponentName]: 18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) 19 Register name without ComponentName applies to all components. 20 Register that is specific to -LP denoted by "_PCH_LP_" in component name. push_assignment(char * var,enum ECPGdtype value)21 - SubsystemName: 22 This field indicates the subsystem name of the component that the register belongs to 23 (e.g. PCIE, USB, SATA, GPIO, PMC etc.). 24 - RegisterSpace: 25 MEM - MMIO space register of subsystem. 26 IO - IO space register of subsystem. 27 PCR - Private configuration register of subsystem. 28 CFG - PCI configuration space register of subsystem. 29 - RegisterName: 30 Full register name. 31 32 Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> 33 SPDX-License-Identifier: BSD-2-Clause-Patent 34 **/ 35 #ifndef _PCH_REGS_PMC_H_ 36 #define _PCH_REGS_PMC_H_ 37 38 // 39 // ACPI and legacy I/O register offsets from ACPIBASE 40 // 41 #define R_ACPI_IO_PM1_STS 0x00 42 #define S_ACPI_IO_PM1_STS 2 43 #define B_ACPI_IO_PM1_STS_WAK BIT15 44 #define B_ACPI_IO_PM1_STS_PCIEXP_WAKE_STS BIT14 45 #define B_ACPI_IO_PM1_STS_PRBTNOR BIT11 46 #define B_ACPI_IO_PM1_STS_RTC BIT10 47 #define B_ACPI_IO_PM1_STS_PWRBTN BIT8 48 #define B_ACPI_IO_PM1_STS_GBL BIT5 49 #define B_ACPI_IO_PM1_STS_TMROF BIT0 50 #define N_ACPI_IO_PM1_STS_RTC 10 51 #define N_ACPI_IO_PM1_STS_PWRBTN 8 52 #define N_ACPI_IO_PM1_STS_TMROF 0 53 54 #define R_ACPI_IO_PM1_EN 0x02 55 #define S_ACPI_IO_PM1_EN 2 56 #define B_ACPI_IO_PM1_EN_PWRBTN BIT8 57 #define N_ACPI_IO_PM1_EN_RTC 10 58 #define N_ACPI_IO_PM1_EN_PWRBTN 8 59 #define N_ACPI_IO_PM1_EN_TMROF 0 60 61 #define R_ACPI_IO_PM1_CNT 0x04 62 #define B_ACPI_IO_PM1_CNT_SLP_EN BIT13 63 #define B_ACPI_IO_PM1_CNT_SLP_TYP (BIT12 | BIT11 | BIT10) 64 #define V_ACPI_IO_PM1_CNT_S0 0 65 #define V_ACPI_IO_PM1_CNT_S1 BIT10 66 #define V_ACPI_IO_PM1_CNT_S3 (BIT12 | BIT10) 67 #define V_ACPI_IO_PM1_CNT_S4 (BIT12 | BIT11) 68 #define V_ACPI_IO_PM1_CNT_S5 (BIT12 | BIT11 | BIT10) 69 #define B_ACPI_IO_PM1_CNT_SCI_EN BIT0 70 71 #define R_ACPI_IO_PM1_TMR 0x08 72 #define B_ACPI_IO_PM1_TMR_VAL 0xFFFFFF 73 #define V_ACPI_IO_PM1_TMR_MAX_VAL 0x1000000 ///< The timer is 24 bit overflow 74 75 #define R_ACPI_IO_SMI_EN 0x30 76 #define S_ACPI_IO_SMI_EN 4 77 #define B_ACPI_IO_SMI_EN_LEGACY_USB2 BIT17 78 #define B_ACPI_IO_SMI_EN_TCO BIT13 79 #define B_ACPI_IO_SMI_EN_BIOS_RLS BIT7 80 #define B_ACPI_IO_SMI_EN_SWSMI_TMR BIT6 81 #define B_ACPI_IO_SMI_EN_APMC BIT5 82 #define B_ACPI_IO_SMI_EN_LEGACY_USB BIT3 83 #define B_ACPI_IO_SMI_EN_BIOS BIT2 84 #define B_ACPI_IO_SMI_EN_EOS BIT1 85 #define B_ACPI_IO_SMI_EN_GBL_SMI BIT0 86 #define N_ACPI_IO_SMI_EN_LEGACY_USB3 31 87 #define N_ACPI_IO_SMI_EN_ESPI 28 88 #define N_ACPI_IO_SMI_EN_PERIODIC 14 89 #define N_ACPI_IO_SMI_EN_TCO 13 90 #define N_ACPI_IO_SMI_EN_MCSMI 11 91 #define N_ACPI_IO_SMI_EN_SWSMI_TMR 6 92 #define N_ACPI_IO_SMI_EN_APMC 5 93 #define N_ACPI_IO_SMI_EN_ON_SLP_EN 4 94 #define N_ACPI_IO_SMI_EN_LEGACY_USB 3 95 96 #define R_ACPI_IO_SMI_STS 0x34 97 #define S_ACPI_IO_SMI_STS 4 98 #define B_ACPI_IO_SMI_STS_GPIO_UNLOCK BIT27 99 #define B_ACPI_IO_SMI_STS_SMBUS BIT16 100 #define B_ACPI_IO_SMI_STS_PERIODIC BIT14 101 #define B_ACPI_IO_SMI_STS_TCO BIT13 102 #define B_ACPI_IO_SMI_STS_MCSMI BIT11 103 #define B_ACPI_IO_SMI_STS_SWSMI_TMR BIT6 104 #define B_ACPI_IO_SMI_STS_APM BIT5 105 #define B_ACPI_IO_SMI_STS_ON_SLP_EN BIT4 106 #define B_ACPI_IO_SMI_STS_BIOS BIT2 107 #define N_ACPI_IO_SMI_STS_LEGACY_USB3 31 108 #define N_ACPI_IO_SMI_STS_ESPI 28 109 #define N_ACPI_IO_SMI_STS_SPI 26 110 #define N_ACPI_IO_SMI_STS_MONITOR 21 111 #define N_ACPI_IO_SMI_STS_PCI_EXP 20 112 #define N_ACPI_IO_SMI_STS_SMBUS 16 113 #define N_ACPI_IO_SMI_STS_SERIRQ 15 114 #define N_ACPI_IO_SMI_STS_PERIODIC 14 115 #define N_ACPI_IO_SMI_STS_TCO 13 116 #define N_ACPI_IO_SMI_STS_MCSMI 11 117 #define N_ACPI_IO_SMI_STS_GPIO_SMI 10 118 #define N_ACPI_IO_SMI_STS_GPE0 9 119 #define N_ACPI_IO_SMI_STS_PM1_STS_REG 8 120 #define N_ACPI_IO_SMI_STS_SWSMI_TMR 6 121 #define N_ACPI_IO_SMI_STS_APM 5 122 #define N_ACPI_IO_SMI_STS_ON_SLP_EN 4 123 #define N_ACPI_IO_SMI_STS_LEGACY_USB 3 124 125 #define R_ACPI_IO_DEVACT_STS 0x44 126 #define B_ACPI_IO_DEVACT_STS_KBC BIT12 127 #define B_ACPI_IO_DEVACT_STS_PIRQDH BIT9 128 #define B_ACPI_IO_DEVACT_STS_PIRQCG BIT8 129 #define B_ACPI_IO_DEVACT_STS_PIRQBF BIT7 130 #define B_ACPI_IO_DEVACT_STS_PIRQAE BIT6 131 132 #define R_ACPI_IO_GPE0_STS_127_96 0x6C 133 #define S_ACPI_IO_GPE0_STS_127_96 4 134 #define B_ACPI_IO_GPE0_STS_127_96_WADT BIT18 135 #define B_ACPI_IO_GPE0_STS_127_96_USB_CON_DSX_STS BIT17 136 #define B_ACPI_IO_GPE0_STS_127_96_LAN_WAKE BIT16 137 #define B_ACPI_IO_GPE0_STS_127_96_PME_B0 BIT13 138 #define B_ACPI_IO_GPE0_STS_127_96_PME BIT11 139 #define B_ACPI_IO_GPE0_STS_127_96_BATLOW BIT10 140 #define B_ACPI_IO_GPE0_STS_127_96_RI BIT8 141 #define B_ACPI_IO_GPE0_STS_127_96_SMB_WAK BIT7 142 #define B_ACPI_IO_GPE0_STS_127_96_SWGPE BIT2 143 #define N_ACPI_IO_GPE0_STS_127_96_PME_B0 13 144 #define N_ACPI_IO_GPE0_STS_127_96_PME 11 145 146 #define R_ACPI_IO_GPE0_EN_127_96 0x7C 147 #define S_ACPI_IO_GPE0_EN_127_96 4 148 #define B_ACPI_IO_GPE0_EN_127_96_WADT BIT18 149 #define B_ACPI_IO_GPE0_EN_127_96_LAN_WAKE BIT16 150 #define B_ACPI_IO_GPE0_EN_127_96_PME_B0 BIT13 151 #define B_ACPI_IO_GPE0_EN_127_96_ME_SCI BIT12 152 #define B_ACPI_IO_GPE0_EN_127_96_PME BIT11 153 #define B_ACPI_IO_GPE0_EN_127_96_BATLOW BIT10 154 #define B_ACPI_IO_GPE0_EN_127_96_RI BIT8 155 #define B_ACPI_IO_GPE0_EN_127_96_SWGPE BIT2 156 #define N_ACPI_IO_GPE0_EN_127_96_PME_B0 13 157 #define N_ACPI_IO_GPE0_EN_127_96_PME 11 158 159 // 160 // TCO register I/O map 161 // 162 #define R_TCO_IO_TCO1_STS 0x04 163 #define S_TCO_IO_TCO1_STS 2 164 #define B_TCO_IO_TCO1_STS_DMISERR BIT12 165 #define B_TCO_IO_TCO1_STS_DMISMI BIT10 166 #define B_TCO_IO_TCO1_STS_DMISCI BIT9 167 #define B_TCO_IO_TCO1_STS_BIOSWR BIT8 168 #define B_TCO_IO_TCO1_STS_NEWCENTURY BIT7 169 #define B_TCO_IO_TCO1_STS_TIMEOUT BIT3 170 #define B_TCO_IO_TCO1_STS_TCO_INT BIT2 171 #define B_TCO_IO_TCO1_STS_SW_TCO_SMI BIT1 172 #define N_TCO_IO_TCO1_STS_DMISMI 10 173 #define N_TCO_IO_TCO1_STS_BIOSWR 8 174 #define N_TCO_IO_TCO1_STS_NEWCENTURY 7 175 #define N_TCO_IO_TCO1_STS_TIMEOUT 3 176 #define N_TCO_IO_TCO1_STS_SW_TCO_SMI 1 177 #define N_TCO_IO_TCO1_STS_NMI2SMI 0 178 179 #define R_TCO_IO_TCO2_STS 0x06 180 #define S_TCO_IO_TCO2_STS 2 181 #define B_TCO_IO_TCO2_STS_SECOND_TO BIT1 182 #define B_TCO_IO_TCO2_STS_INTRD_DET BIT0 183 #define N_TCO_IO_TCO2_STS_INTRD_DET 0 184 185 #define R_TCO_IO_TCO1_CNT 0x08 186 #define S_TCO_IO_TCO1_CNT 2 187 #define B_TCO_IO_TCO1_CNT_LOCK BIT12 188 #define N_TCO_IO_TCO1_CNT_NMI2SMI_EN 9 189 190 #define R_TCO_IO_TCO2_CNT 0x0A 191 #define S_TCO_IO_TCO2_CNT 2 192 #define N_TCO_IO_TCO2_CNT_INTRD_SEL 2 193 194 // 195 // PWRM Registers 196 // 197 #define R_PMC_PWRM_GEN_PMCON_A 0x1020 ///< in CNL located in PWRM 198 #define B_PMC_PWRM_GEN_PMCON_A_GBL_RST_STS BIT24 199 #define B_PMC_PWRM_GEN_PMCON_A_DISB BIT23 200 #define B_PMC_PWRM_GEN_PMCON_A_ALLOW_L1LOW_C0 BIT19 201 #define B_PMC_PWRM_GEN_PMCON_A_MS4V BIT18 202 #define B_PMC_PWRM_GEN_PMCON_A_SUS_PWR_FLR BIT16 203 #define B_PMC_PWRM_GEN_PMCON_A_PWR_FLR BIT14 204 #define B_PMC_PWRM_GEN_PMCON_A_HOST_RST_STS BIT9 205 #define B_PMC_PWRM_GEN_PMCON_A_ESPI_SMI_LOCK BIT8 206 #define B_PMC_PWRM_GEN_PMCON_A_AFTERG3_EN BIT0 207 #define B_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL 0xC0 208 #define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_64MS 0xC0 209 #define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_32MS 0x80 210 #define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_16MS 0x40 211 #define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_1_5MS 0x00 212 #define B_PMC_PWRM_GEN_PMCON_A_PER_SMI_SEL 0x6 213 #define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_64S 0x0000 214 #define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_32S 0x0002 215 #define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_16S 0x0004 216 #define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_8S 0x0006 217 218 #define R_PMC_PWRM_GEN_PMCON_B 0x1024 219 #define B_PMC_PWRM_GEN_PMCON_B_SLPSX_STR_POL_LOCK BIT18 ///< Lock down SLP_S3/SLP_S4 Minimum Assertion width 220 #define B_PMC_PWRM_GEN_PMCON_B_PWRBTN_LVL BIT9 221 #define B_PMC_PWRM_GEN_PMCON_B_SMI_LOCK BIT4 222 #define B_PMC_PWRM_GEN_PMCON_B_RTC_PWR_STS BIT2 223 224 #define R_PMC_PWRM_CRID 0x1030 ///< Configured Revision ID 225 #define V_PMC_PWRM_CRID_RID_SEL_CRID0 1 226 #define B_PMC_PWRM_CRID_CRID_LK BIT31 ///< CRID Lock 227 228 #define R_PMC_PWRM_ETR3 0x1048 ///< in CNL this is PWRM register 229 #define B_PMC_PWRM_ETR3_CF9LOCK BIT31 ///< CF9h Lockdown 230 #define B_PMC_PWRM_ETR3_CF9GR BIT20 ///< CF9h Global Reset 231 #define B_PMC_PWRM_ETR3_CWORWRE BIT18 232 233 #define R_PMC_PWRM_CFG 0x1818 ///< Power Management Configuration 234 #define B_PMC_PWRM_CFG_DBG_MODE_LOCK BIT27 ///< Debug Mode Lock 235 #define B_PMC_PWRM_CFG_PMCREAD_DISABLE BIT22 ///< Disable Reads to PMC 236 #define B_PMC_PWRM_CFG_TIMING_TPCH25 (BIT1 | BIT0) ///< tPCH25 timing 237 238 #define R_PMC_PWRM_DSX_CFG 0x1834 ///< Deep SX Configuration 239 #define B_PMC_PWRM_DSX_CFG_LAN_WAKE_EN BIT0 ///< LAN_WAKE Pin DeepSx Enable 240 241 #define R_PMC_PWRM_GPIO_CFG 0x1920 242 #define B_PMC_PWRM_GPIO_CFG_GPE0_DW2 (BIT11 | BIT10 | BIT9 | BIT8) 243 #define N_PMC_PWRM_GPIO_CFG_GPE0_DW2 8 244 #define B_PMC_PWRM_GPIO_CFG_GPE0_DW1 (BIT7 | BIT6 | BIT5 | BIT4) 245 #define N_PMC_PWRM_GPIO_CFG_GPE0_DW1 4 246 #define B_PMC_PWRM_GPIO_CFG_GPE0_DW0 (BIT3 | BIT2 | BIT1 | BIT0) 247 #define N_PMC_PWRM_GPIO_CFG_GPE0_DW0 0 248 249 #define R_PMC_PWRM_HPR_CAUSE0 0x192C ///< Host partition reset causes 250 #define B_PMC_PWRM_HPR_CAUSE0_GBL_TO_HOST BIT15 ///< Global reset converted to Host reset 251 252 #define R_PMC_PWRM_ST_PG_FDIS_PMC_1 0x1E20 ///< Static PG Related Function Disable Register 1 253 #define B_PMC_PWRM_ST_PG_FDIS_PMC_1_ST_FDIS_LK BIT31 ///< Static Function Disable Lock (ST_FDIS_LK) 254 255 #define R_PMC_PWRM_FUSE_DIS_RD_2 0x1E44 ///< Fuse Disable Read 2 Register 256 #define B_PMC_PWRM_FUSE_DIS_RD_2_GBE_FUSE_SS_DIS BIT0 ///< GBE Fuse or Soft Strap Disable 257 258 #endif 259