1 /* 2 * This file is part of the flashrom project. 3 * 4 * Copyright (C) 2000 Silicon Integrated System Corporation 5 * Copyright (C) 2005-2009 coresystems GmbH 6 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de> 7 * Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger 8 * Copyright (C) 2009 Kontron Modular Computers GmbH 9 * Copyright (C) 2011, 2012 Stefan Tauner 10 * Copyright (C) 2017 secunet Security Networks AG 11 * (Written by Nico Huber <nico.huber@secunet.com> for secunet) 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; version 2 of the License. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 */ 22 23 /* 24 * Contains the chipset specific flash enables. 25 */ 26 27 #define _LARGEFILE64_SOURCE 28 29 #include <stdlib.h> 30 #include <string.h> 31 #include <unistd.h> 32 #include <inttypes.h> 33 #include <errno.h> 34 #include "flash.h" 35 #include "programmer.h" 36 #include "hwaccess.h" 37 38 #define NOT_DONE_YET 1 39 40 #if defined(__i386__) || defined(__x86_64__) 41 42 static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) 43 { 44 uint8_t tmp; 45 46 /* 47 * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and 48 * 0xFFFE0000-0xFFFFFFFF ROM select enable. 49 */ 50 tmp = pci_read_byte(dev, 0x47); 51 tmp |= 0x46; 52 rpci_write_byte(dev, 0x47, tmp); 53 54 return 0; 55 } 56 57 static int enable_flash_rdc_r8610(struct pci_dev *dev, const char *name) 58 { 59 uint8_t tmp; 60 61 /* enable ROMCS for writes */ 62 tmp = pci_read_byte(dev, 0x43); 63 tmp |= 0x80; 64 pci_write_byte(dev, 0x43, tmp); 65 66 /* read the bootstrapping register */ 67 tmp = pci_read_byte(dev, 0x40) & 0x3; 68 switch (tmp) { 69 case 3: 70 internal_buses_supported &= BUS_FWH; 71 break; 72 case 2: 73 internal_buses_supported &= BUS_LPC; 74 break; 75 default: 76 internal_buses_supported &= BUS_PARALLEL; 77 break; 78 } 79 80 return 0; 81 } 82 83 static int enable_flash_sis85c496(struct pci_dev *dev, const char *name) 84 { 85 uint8_t tmp; 86 87 tmp = pci_read_byte(dev, 0xd0); 88 tmp |= 0xf8; 89 rpci_write_byte(dev, 0xd0, tmp); 90 91 return 0; 92 } 93 94 static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name) 95 { 96 #define SIS_MAPREG 0x40 97 uint8_t new, newer; 98 99 /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */ 100 /* This is 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */ 101 new = pci_read_byte(dev, SIS_MAPREG); 102 new &= (~0x04); /* No idea why we clear bit 2. */ 103 new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */ 104 rpci_write_byte(dev, SIS_MAPREG, new); 105 newer = pci_read_byte(dev, SIS_MAPREG); 106 if (newer != new) { /* FIXME: share this with other code? */ 107 msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", 108 SIS_MAPREG, new, name); 109 msg_pinfo("Stuck at 0x%02x.\n", newer); 110 return -1; 111 } 112 return 0; 113 } 114 115 static struct pci_dev *find_southbridge(uint16_t vendor, const char *name) 116 { 117 struct pci_dev *sbdev; 118 119 sbdev = pci_dev_find_vendorclass(vendor, 0x0601); 120 if (!sbdev) 121 sbdev = pci_dev_find_vendorclass(vendor, 0x0680); 122 if (!sbdev) 123 sbdev = pci_dev_find_vendorclass(vendor, 0x0000); 124 if (!sbdev) 125 msg_perr("No southbridge found for %s!\n", name); 126 if (sbdev) 127 msg_pdbg("Found southbridge %04x:%04x at %02x:%02x:%01x\n", 128 sbdev->vendor_id, sbdev->device_id, 129 sbdev->bus, sbdev->dev, sbdev->func); 130 return sbdev; 131 } 132 133 static int enable_flash_sis501(struct pci_dev *dev, const char *name) 134 { 135 uint8_t tmp; 136 int ret = 0; 137 struct pci_dev *sbdev; 138 139 sbdev = find_southbridge(dev->vendor_id, name); 140 if (!sbdev) 141 return -1; 142 143 ret = enable_flash_sis_mapping(sbdev, name); 144 145 tmp = sio_read(0x22, 0x80); 146 tmp &= (~0x20); 147 tmp |= 0x4; 148 sio_write(0x22, 0x80, tmp); 149 150 tmp = sio_read(0x22, 0x70); 151 tmp &= (~0x20); 152 tmp |= 0x4; 153 sio_write(0x22, 0x70, tmp); 154 155 return ret; 156 } 157 158 static int enable_flash_sis5511(struct pci_dev *dev, const char *name) 159 { 160 uint8_t tmp; 161 int ret = 0; 162 struct pci_dev *sbdev; 163 164 sbdev = find_southbridge(dev->vendor_id, name); 165 if (!sbdev) 166 return -1; 167 168 ret = enable_flash_sis_mapping(sbdev, name); 169 170 tmp = sio_read(0x22, 0x50); 171 tmp &= (~0x20); 172 tmp |= 0x4; 173 sio_write(0x22, 0x50, tmp); 174 175 return ret; 176 } 177 178 static int enable_flash_sis5x0(struct pci_dev *dev, const char *name, uint8_t dis_mask, uint8_t en_mask) 179 { 180 #define SIS_REG 0x45 181 uint8_t new, newer; 182 int ret = 0; 183 struct pci_dev *sbdev; 184 185 sbdev = find_southbridge(dev->vendor_id, name); 186 if (!sbdev) 187 return -1; 188 189 ret = enable_flash_sis_mapping(sbdev, name); 190 191 new = pci_read_byte(sbdev, SIS_REG); 192 new &= (~dis_mask); 193 new |= en_mask; 194 rpci_write_byte(sbdev, SIS_REG, new); 195 newer = pci_read_byte(sbdev, SIS_REG); 196 if (newer != new) { /* FIXME: share this with other code? */ 197 msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", SIS_REG, new, name); 198 msg_pinfo("Stuck at 0x%02x\n", newer); 199 ret = -1; 200 } 201 202 return ret; 203 } 204 205 static int enable_flash_sis530(struct pci_dev *dev, const char *name) 206 { 207 return enable_flash_sis5x0(dev, name, 0x20, 0x04); 208 } 209 210 static int enable_flash_sis540(struct pci_dev *dev, const char *name) 211 { 212 return enable_flash_sis5x0(dev, name, 0x80, 0x40); 213 } 214 215 /* Datasheet: 216 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4) 217 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm 218 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf 219 * - Order Number: 290562-001 220 */ 221 static int enable_flash_piix4(struct pci_dev *dev, const char *name) 222 { 223 uint16_t old, new; 224 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */ 225 226 internal_buses_supported &= BUS_PARALLEL; 227 228 old = pci_read_word(dev, xbcs); 229 230 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to 231 * FFF00000-FFF7FFFF are forwarded to ISA). 232 * Note: This bit is reserved on PIIX/PIIX3/MPIIX. 233 * Set bit 7: Extended BIOS Enable (PCI master accesses to 234 * FFF80000-FFFDFFFF are forwarded to ISA). 235 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to 236 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top 237 * of 1 Mbyte, or the aliases at the top of 4 Gbyte 238 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#. 239 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA. 240 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable). 241 */ 242 if (dev->device_id == 0x122e || dev->device_id == 0x7000 243 || dev->device_id == 0x1234) 244 new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */ 245 else 246 new = old | 0x02c4; 247 248 if (new == old) 249 return 0; 250 251 rpci_write_word(dev, xbcs, new); 252 253 if (pci_read_word(dev, xbcs) != new) { /* FIXME: share this with other code? */ 254 msg_pinfo("Setting register 0x%04x to 0x%04x on %s failed (WARNING ONLY).\n", xbcs, new, name); 255 return -1; 256 } 257 258 return 0; 259 } 260 261 /* Handle BIOS_CNTL (aka. BCR). Disable locks and enable writes. The register can either be in PCI config space 262 * at the offset given by 'bios_cntl' or at the memory-mapped address 'addr'. 263 * 264 * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, in Poulsbo, Tunnel Creek and other Atom 265 * chipsets/SoCs it is even 32b, but just treating it as 8 bit wide seems to work fine in practice. */ 266 static int enable_flash_ich_bios_cntl_common(enum ich_chipset ich_generation, void *addr, 267 struct pci_dev *dev, uint8_t bios_cntl) 268 { 269 uint8_t old, new, wanted; 270 271 switch (ich_generation) { 272 case CHIPSET_ICH_UNKNOWN: 273 return ERROR_FATAL; 274 /* Non-SPI-capable */ 275 case CHIPSET_ICH: 276 case CHIPSET_ICH2345: 277 break; 278 /* Some Atom chipsets are special: The second byte of BIOS_CNTL (D9h) contains a prefetch bit similar to 279 * what other SPI-capable chipsets have at DCh. Others like Bay Trail use a memmapped register. 280 * The Tunnel Creek datasheet contains a lot of details about the SPI controller, among other things it 281 * mentions that the prefetching and caching does only happen for direct memory reads. 282 * Therefore - at least for Tunnel Creek - it should not matter to flashrom because we use the 283 * programmed access only and not memory mapping. */ 284 case CHIPSET_TUNNEL_CREEK: 285 case CHIPSET_POULSBO: 286 case CHIPSET_CENTERTON: 287 old = pci_read_byte(dev, bios_cntl + 1); 288 msg_pdbg("BIOS Prefetch Enable: %sabled, ", (old & 1) ? "en" : "dis"); 289 break; 290 case CHIPSET_BAYTRAIL: 291 case CHIPSET_ICH7: 292 default: /* Future version might behave the same */ 293 if (ich_generation == CHIPSET_BAYTRAIL) 294 old = (mmio_readl(addr) >> 2) & 0x3; 295 else 296 old = (pci_read_byte(dev, bios_cntl) >> 2) & 0x3; 297 msg_pdbg("SPI Read Configuration: "); 298 if (old == 3) 299 msg_pdbg("invalid prefetching/caching settings, "); 300 else 301 msg_pdbg("prefetching %sabled, caching %sabled, ", 302 (old & 0x2) ? "en" : "dis", 303 (old & 0x1) ? "dis" : "en"); 304 } 305 306 if (ich_generation == CHIPSET_BAYTRAIL) 307 wanted = old = mmio_readl(addr); 308 else 309 wanted = old = pci_read_byte(dev, bios_cntl); 310 311 /* 312 * Quote from the 6 Series datasheet (Document Number: 324645-004): 313 * "Bit 5: SMM BIOS Write Protect Disable (SMM_BWP) 314 * 1 = BIOS region SMM protection is enabled. 315 * The BIOS Region is not writable unless all processors are in SMM." 316 * In earlier chipsets this bit is reserved. 317 * 318 * Try to unset it in any case. 319 * It won't hurt and makes sense in some cases according to Stefan Reinauer. 320 * 321 * At least in Centerton aforementioned bit is located at bit 7. It is unspecified in all other Atom 322 * and Desktop chipsets before Ibex Peak/5 Series, but we reset bit 5 anyway. 323 */ 324 int smm_bwp_bit; 325 if (ich_generation == CHIPSET_CENTERTON) 326 smm_bwp_bit = 7; 327 else 328 smm_bwp_bit = 5; 329 wanted &= ~(1 << smm_bwp_bit); 330 331 /* Tunnel Creek has a cache disable at bit 2 of the lowest BIOS_CNTL byte. */ 332 if (ich_generation == CHIPSET_TUNNEL_CREEK) 333 wanted |= (1 << 2); 334 335 wanted |= (1 << 0); /* Set BIOS Write Enable */ 336 wanted &= ~(1 << 1); /* Disable lock (futile) */ 337 338 /* Only write the register if it's necessary */ 339 if (wanted != old) { 340 if (ich_generation == CHIPSET_BAYTRAIL) { 341 rmmio_writel(wanted, addr); 342 new = mmio_readl(addr); 343 } else { 344 rpci_write_byte(dev, bios_cntl, wanted); 345 new = pci_read_byte(dev, bios_cntl); 346 } 347 } else 348 new = old; 349 350 msg_pdbg("\nBIOS_CNTL = 0x%02x: ", new); 351 msg_pdbg("BIOS Lock Enable: %sabled, ", (new & (1 << 1)) ? "en" : "dis"); 352 msg_pdbg("BIOS Write Enable: %sabled\n", (new & (1 << 0)) ? "en" : "dis"); 353 if (new & (1 << smm_bwp_bit)) 354 msg_pwarn("Warning: BIOS region SMM protection is enabled!\n"); 355 356 if (new != wanted) 357 msg_pwarn("Warning: Setting Bios Control at 0x%x from 0x%02x to 0x%02x failed.\n" 358 "New value is 0x%02x.\n", bios_cntl, old, wanted, new); 359 360 /* Return an error if we could not set the write enable only. */ 361 if (!(new & (1 << 0))) 362 return -1; 363 364 return 0; 365 } 366 367 static int enable_flash_ich_bios_cntl_config_space(struct pci_dev *dev, enum ich_chipset ich_generation, 368 uint8_t bios_cntl) 369 { 370 return enable_flash_ich_bios_cntl_common(ich_generation, NULL, dev, bios_cntl); 371 } 372 373 static int enable_flash_ich_bios_cntl_memmapped(enum ich_chipset ich_generation, void *addr) 374 { 375 return enable_flash_ich_bios_cntl_common(ich_generation, addr, NULL, 0); 376 } 377 378 static int enable_flash_ich_fwh_decode(struct pci_dev *dev, enum ich_chipset ich_generation) 379 { 380 uint8_t fwh_sel1 = 0, fwh_sel2 = 0, fwh_dec_en_lo = 0, fwh_dec_en_hi = 0; /* silence compilers */ 381 bool implemented = 0; 382 void *ilb = NULL; /* Only for Baytrail */ 383 switch (ich_generation) { 384 case CHIPSET_ICH: 385 /* FIXME: Unlike later chipsets, ICH and ICH-0 do only support mapping of the top-most 4MB 386 * and therefore do only feature FWH_DEC_EN (E3h, different default too) and FWH_SEL (E8h). */ 387 break; 388 case CHIPSET_ICH2345: 389 fwh_sel1 = 0xe8; 390 fwh_sel2 = 0xee; 391 fwh_dec_en_lo = 0xf0; 392 fwh_dec_en_hi = 0xe3; 393 implemented = 1; 394 break; 395 case CHIPSET_POULSBO: 396 case CHIPSET_TUNNEL_CREEK: 397 /* FIXME: Similar to ICH and ICH-0, Tunnel Creek and Poulsbo do only feature one register each, 398 * FWH_DEC_EN (D7h) and FWH_SEL (D0h). */ 399 break; 400 case CHIPSET_CENTERTON: 401 /* FIXME: Similar to above FWH_DEC_EN (D4h) and FWH_SEL (D0h). */ 402 break; 403 case CHIPSET_BAYTRAIL: { 404 uint32_t ilb_base = pci_read_long(dev, 0x50) & 0xfffffe00; /* bits 31:9 */ 405 if (ilb_base == 0) { 406 msg_perr("Error: Invalid ILB_BASE_ADDRESS\n"); 407 return ERROR_FATAL; 408 } 409 ilb = rphysmap("BYT IBASE", ilb_base, 512); 410 fwh_sel1 = 0x18; 411 fwh_dec_en_lo = 0xd8; 412 fwh_dec_en_hi = 0xd9; 413 implemented = 1; 414 break; 415 } 416 case CHIPSET_ICH6: 417 case CHIPSET_ICH7: 418 default: /* Future version might behave the same */ 419 fwh_sel1 = 0xd0; 420 fwh_sel2 = 0xd4; 421 fwh_dec_en_lo = 0xd8; 422 fwh_dec_en_hi = 0xd9; 423 implemented = 1; 424 break; 425 } 426 427 char *idsel = extract_programmer_param("fwh_idsel"); 428 if (idsel && strlen(idsel)) { 429 if (!implemented) { 430 msg_perr("Error: fwh_idsel= specified, but (yet) unsupported on this chipset.\n"); 431 goto idsel_garbage_out; 432 } 433 errno = 0; 434 /* Base 16, nothing else makes sense. */ 435 uint64_t fwh_idsel = (uint64_t)strtoull(idsel, NULL, 16); 436 if (errno) { 437 msg_perr("Error: fwh_idsel= specified, but value could not be converted.\n"); 438 goto idsel_garbage_out; 439 } 440 uint64_t fwh_mask = 0xffffffff; 441 if (fwh_sel2 > 0) 442 fwh_mask |= (0xffffULL << 32); 443 if (fwh_idsel & ~fwh_mask) { 444 msg_perr("Error: fwh_idsel= specified, but value had unused bits set.\n"); 445 goto idsel_garbage_out; 446 } 447 uint64_t fwh_idsel_old; 448 if (ich_generation == CHIPSET_BAYTRAIL) { 449 fwh_idsel_old = mmio_readl(ilb + fwh_sel1); 450 rmmio_writel(fwh_idsel, ilb + fwh_sel1); 451 } else { 452 fwh_idsel_old = (uint64_t)pci_read_long(dev, fwh_sel1) << 16; 453 rpci_write_long(dev, fwh_sel1, (fwh_idsel >> 16) & 0xffffffff); 454 if (fwh_sel2 > 0) { 455 fwh_idsel_old |= pci_read_word(dev, fwh_sel2); 456 rpci_write_word(dev, fwh_sel2, fwh_idsel & 0xffff); 457 } 458 } 459 msg_pdbg("Setting IDSEL from 0x%012" PRIx64 " to 0x%012" PRIx64 " for top 16 MB.\n", 460 fwh_idsel_old, fwh_idsel); 461 /* FIXME: Decode settings are not changed. */ 462 } else if (idsel) { 463 msg_perr("Error: fwh_idsel= specified, but no value given.\n"); 464 idsel_garbage_out: 465 free(idsel); 466 return ERROR_FATAL; 467 } 468 free(idsel); 469 470 if (!implemented) { 471 msg_pdbg2("FWH IDSEL handling is not implemented on this chipset.\n"); 472 return 0; 473 } 474 475 /* Ignore all legacy ranges below 1 MB. 476 * We currently only support flashing the chip which responds to 477 * IDSEL=0. To support IDSEL!=0, flashbase and decode size calculations 478 * have to be adjusted. 479 */ 480 int max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0; 481 bool contiguous = 1; 482 uint32_t fwh_conf; 483 if (ich_generation == CHIPSET_BAYTRAIL) 484 fwh_conf = mmio_readl(ilb + fwh_sel1); 485 else 486 fwh_conf = pci_read_long(dev, fwh_sel1); 487 488 int i; 489 /* FWH_SEL1 */ 490 for (i = 7; i >= 0; i--) { 491 int tmp = (fwh_conf >> (i * 4)) & 0xf; 492 msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n", 493 (0x1ff8 + i) * 0x80000, 494 (0x1ff0 + i) * 0x80000, 495 tmp); 496 if ((tmp == 0) && contiguous) { 497 max_decode_fwh_idsel = (8 - i) * 0x80000; 498 } else { 499 contiguous = 0; 500 } 501 } 502 if (fwh_sel2 > 0) { 503 /* FWH_SEL2 */ 504 fwh_conf = pci_read_word(dev, fwh_sel2); 505 for (i = 3; i >= 0; i--) { 506 int tmp = (fwh_conf >> (i * 4)) & 0xf; 507 msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n", 508 (0xff4 + i) * 0x100000, 509 (0xff0 + i) * 0x100000, 510 tmp); 511 if ((tmp == 0) && contiguous) { 512 max_decode_fwh_idsel = (8 - i) * 0x100000; 513 } else { 514 contiguous = 0; 515 } 516 } 517 } 518 contiguous = 1; 519 /* FWH_DEC_EN1 */ 520 fwh_conf = pci_read_byte(dev, fwh_dec_en_hi); 521 fwh_conf <<= 8; 522 fwh_conf |= pci_read_byte(dev, fwh_dec_en_lo); 523 for (i = 7; i >= 0; i--) { 524 int tmp = (fwh_conf >> (i + 0x8)) & 0x1; 525 msg_pdbg("0x%08x/0x%08x FWH decode %sabled\n", 526 (0x1ff8 + i) * 0x80000, 527 (0x1ff0 + i) * 0x80000, 528 tmp ? "en" : "dis"); 529 if ((tmp == 1) && contiguous) { 530 max_decode_fwh_decode = (8 - i) * 0x80000; 531 } else { 532 contiguous = 0; 533 } 534 } 535 for (i = 3; i >= 0; i--) { 536 int tmp = (fwh_conf >> i) & 0x1; 537 msg_pdbg("0x%08x/0x%08x FWH decode %sabled\n", 538 (0xff4 + i) * 0x100000, 539 (0xff0 + i) * 0x100000, 540 tmp ? "en" : "dis"); 541 if ((tmp == 1) && contiguous) { 542 max_decode_fwh_decode = (8 - i) * 0x100000; 543 } else { 544 contiguous = 0; 545 } 546 } 547 max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode); 548 msg_pdbg("Maximum FWH chip size: 0x%x bytes\n", max_rom_decode.fwh); 549 550 return 0; 551 } 552 553 static int enable_flash_ich_fwh(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl) 554 { 555 int err; 556 557 /* Configure FWH IDSEL decoder maps. */ 558 if ((err = enable_flash_ich_fwh_decode(dev, ich_generation)) != 0) 559 return err; 560 561 internal_buses_supported &= BUS_FWH; 562 return enable_flash_ich_bios_cntl_config_space(dev, ich_generation, bios_cntl); 563 } 564 565 static int enable_flash_ich0(struct pci_dev *dev, const char *name) 566 { 567 return enable_flash_ich_fwh(dev, CHIPSET_ICH, 0x4e); 568 } 569 570 static int enable_flash_ich2345(struct pci_dev *dev, const char *name) 571 { 572 return enable_flash_ich_fwh(dev, CHIPSET_ICH2345, 0x4e); 573 } 574 575 static int enable_flash_ich6(struct pci_dev *dev, const char *name) 576 { 577 return enable_flash_ich_fwh(dev, CHIPSET_ICH6, 0xdc); 578 } 579 580 static int enable_flash_poulsbo(struct pci_dev *dev, const char *name) 581 { 582 return enable_flash_ich_fwh(dev, CHIPSET_POULSBO, 0xd8); 583 } 584 585 static enum chipbustype enable_flash_ich_report_gcs( 586 struct pci_dev *const dev, const enum ich_chipset ich_generation, const uint8_t *const rcrb) 587 { 588 uint32_t gcs; 589 const char *reg_name; 590 bool bild, top_swap; 591 592 switch (ich_generation) { 593 case CHIPSET_BAYTRAIL: 594 reg_name = "GCS"; 595 gcs = mmio_readl(rcrb + 0); 596 bild = gcs & 1; 597 top_swap = (gcs & 2) >> 1; 598 break; 599 case CHIPSET_100_SERIES_SUNRISE_POINT: 600 case CHIPSET_C620_SERIES_LEWISBURG: 601 case CHIPSET_300_SERIES_CANNON_POINT: 602 case CHIPSET_APOLLO_LAKE: 603 reg_name = "BIOS_SPI_BC"; 604 gcs = pci_read_long(dev, 0xdc); 605 bild = (gcs >> 7) & 1; 606 top_swap = (gcs >> 4) & 1; 607 break; 608 default: 609 reg_name = "GCS"; 610 gcs = mmio_readl(rcrb + 0x3410); 611 bild = gcs & 1; 612 top_swap = mmio_readb(rcrb + 0x3414) & 1; 613 break; 614 } 615 616 msg_pdbg("%s = 0x%x: ", reg_name, gcs); 617 msg_pdbg("BIOS Interface Lock-Down: %sabled, ", bild ? "en" : "dis"); 618 619 struct boot_straps { 620 const char *name; 621 enum chipbustype bus; 622 }; 623 static const struct boot_straps boot_straps_EP80579[] = 624 { { "SPI", BUS_SPI }, 625 { "reserved", BUS_NONE }, 626 { "reserved", BUS_NONE }, 627 { "LPC", BUS_LPC | BUS_FWH } }; 628 static const struct boot_straps boot_straps_ich7_nm10[] = 629 { { "reserved", BUS_NONE }, 630 { "SPI", BUS_SPI }, 631 { "PCI", BUS_NONE }, 632 { "LPC", BUS_LPC | BUS_FWH } }; 633 static const struct boot_straps boot_straps_tunnel_creek[] = 634 { { "SPI", BUS_SPI }, 635 { "LPC", BUS_LPC | BUS_FWH } }; 636 static const struct boot_straps boot_straps_ich8910[] = 637 { { "SPI", BUS_SPI }, 638 { "SPI", BUS_SPI }, 639 { "PCI", BUS_NONE }, 640 { "LPC", BUS_LPC | BUS_FWH } }; 641 static const struct boot_straps boot_straps_pch567[] = 642 { { "LPC", BUS_LPC | BUS_FWH }, 643 { "reserved", BUS_NONE }, 644 { "PCI", BUS_NONE }, 645 { "SPI", BUS_SPI } }; 646 static const struct boot_straps boot_straps_pch89_baytrail[] = 647 { { "LPC", BUS_LPC | BUS_FWH }, 648 { "reserved", BUS_NONE }, 649 { "reserved", BUS_NONE }, 650 { "SPI", BUS_SPI } }; 651 static const struct boot_straps boot_straps_pch8_lp[] = 652 { { "SPI", BUS_SPI }, 653 { "LPC", BUS_LPC | BUS_FWH } }; 654 static const struct boot_straps boot_straps_apl[] = 655 { { "SPI", BUS_SPI }, 656 { "reserved", BUS_NONE } }; 657 static const struct boot_straps boot_straps_unknown[] = 658 { { "unknown", BUS_NONE }, 659 { "unknown", BUS_NONE }, 660 { "unknown", BUS_NONE }, 661 { "unknown", BUS_NONE } }; 662 663 const struct boot_straps *boot_straps; 664 switch (ich_generation) { 665 case CHIPSET_ICH7: 666 /* EP80579 may need further changes, but this is the least 667 * intrusive way to get correct BOOT Strap printing without 668 * changing the rest of its code path). */ 669 if (dev->device_id == 0x5031) 670 boot_straps = boot_straps_EP80579; 671 else 672 boot_straps = boot_straps_ich7_nm10; 673 break; 674 case CHIPSET_ICH8: 675 case CHIPSET_ICH9: 676 case CHIPSET_ICH10: 677 boot_straps = boot_straps_ich8910; 678 break; 679 case CHIPSET_TUNNEL_CREEK: 680 boot_straps = boot_straps_tunnel_creek; 681 break; 682 case CHIPSET_5_SERIES_IBEX_PEAK: 683 case CHIPSET_6_SERIES_COUGAR_POINT: 684 case CHIPSET_7_SERIES_PANTHER_POINT: 685 boot_straps = boot_straps_pch567; 686 break; 687 case CHIPSET_8_SERIES_LYNX_POINT: 688 case CHIPSET_9_SERIES_WILDCAT_POINT: 689 case CHIPSET_BAYTRAIL: 690 boot_straps = boot_straps_pch89_baytrail; 691 break; 692 case CHIPSET_8_SERIES_LYNX_POINT_LP: 693 case CHIPSET_9_SERIES_WILDCAT_POINT_LP: 694 case CHIPSET_100_SERIES_SUNRISE_POINT: 695 case CHIPSET_C620_SERIES_LEWISBURG: 696 case CHIPSET_300_SERIES_CANNON_POINT: 697 boot_straps = boot_straps_pch8_lp; 698 break; 699 case CHIPSET_APOLLO_LAKE: 700 boot_straps = boot_straps_apl; 701 break; 702 case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet 703 case CHIPSET_CENTERTON: // FIXME: Datasheet does not mention GCS at all 704 boot_straps = boot_straps_unknown; 705 break; 706 default: 707 msg_gerr("%s: unknown ICH generation. Please report!\n", __func__); 708 boot_straps = boot_straps_unknown; 709 break; 710 } 711 712 uint8_t bbs; 713 switch (ich_generation) { 714 case CHIPSET_TUNNEL_CREEK: 715 bbs = (gcs >> 1) & 0x1; 716 break; 717 case CHIPSET_8_SERIES_LYNX_POINT_LP: 718 case CHIPSET_9_SERIES_WILDCAT_POINT_LP: 719 /* LP PCHs use a single bit for BBS */ 720 bbs = (gcs >> 10) & 0x1; 721 break; 722 case CHIPSET_100_SERIES_SUNRISE_POINT: 723 case CHIPSET_C620_SERIES_LEWISBURG: 724 case CHIPSET_300_SERIES_CANNON_POINT: 725 case CHIPSET_APOLLO_LAKE: 726 bbs = (gcs >> 6) & 0x1; 727 break; 728 default: 729 /* Other chipsets use two bits for BBS */ 730 bbs = (gcs >> 10) & 0x3; 731 break; 732 } 733 msg_pdbg("Boot BIOS Straps: 0x%x (%s)\n", bbs, boot_straps[bbs].name); 734 735 /* Centerton has its TS bit in [GPE0BLK] + 0x30 while the exact location for Tunnel Creek is unknown. */ 736 if (ich_generation != CHIPSET_TUNNEL_CREEK && ich_generation != CHIPSET_CENTERTON) 737 msg_pdbg("Top Swap: %s\n", (top_swap) ? "enabled (A16(+) inverted)" : "not enabled"); 738 739 return boot_straps[bbs].bus; 740 } 741 742 static int enable_flash_ich_spi(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl) 743 { 744 /* Get physical address of Root Complex Register Block */ 745 uint32_t rcra = pci_read_long(dev, 0xf0) & 0xffffc000; 746 msg_pdbg("Root Complex Register Block address = 0x%x\n", rcra); 747 748 /* Map RCBA to virtual memory */ 749 void *rcrb = rphysmap("ICH RCRB", rcra, 0x4000); 750 if (rcrb == ERROR_PTR) 751 return ERROR_FATAL; 752 753 const enum chipbustype boot_buses = enable_flash_ich_report_gcs(dev, ich_generation, rcrb); 754 755 /* Handle FWH-related parameters and initialization */ 756 int ret_fwh = enable_flash_ich_fwh(dev, ich_generation, bios_cntl); 757 if (ret_fwh == ERROR_FATAL) 758 return ret_fwh; 759 760 /* SPIBAR is at RCRB+0x3020 for ICH[78], Tunnel Creek and Centerton, and RCRB+0x3800 for ICH9. */ 761 uint16_t spibar_offset; 762 switch (ich_generation) { 763 case CHIPSET_BAYTRAIL: 764 case CHIPSET_ICH_UNKNOWN: 765 return ERROR_FATAL; 766 case CHIPSET_ICH7: 767 case CHIPSET_ICH8: 768 case CHIPSET_TUNNEL_CREEK: 769 case CHIPSET_CENTERTON: 770 spibar_offset = 0x3020; 771 break; 772 case CHIPSET_ICH9: 773 default: /* Future version might behave the same */ 774 spibar_offset = 0x3800; 775 break; 776 } 777 msg_pdbg("SPIBAR = 0x%0*" PRIxPTR " + 0x%04x\n", PRIxPTR_WIDTH, (uintptr_t)rcrb, spibar_offset); 778 void *spibar = rcrb + spibar_offset; 779 780 /* This adds BUS_SPI */ 781 int ret_spi = ich_init_spi(spibar, ich_generation); 782 if (ret_spi == ERROR_FATAL) 783 return ret_spi; 784 785 if (((boot_buses & BUS_FWH) && ret_fwh) || ((boot_buses & BUS_SPI) && ret_spi)) 786 return ERROR_NONFATAL; 787 788 /* Suppress unknown laptop warning if we booted from SPI. */ 789 if (boot_buses & BUS_SPI) 790 laptop_ok = 1; 791 792 return 0; 793 } 794 795 static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name) 796 { 797 return enable_flash_ich_spi(dev, CHIPSET_TUNNEL_CREEK, 0xd8); 798 } 799 800 static int enable_flash_s12x0(struct pci_dev *dev, const char *name) 801 { 802 return enable_flash_ich_spi(dev, CHIPSET_CENTERTON, 0xd8); 803 } 804 805 static int enable_flash_ich7(struct pci_dev *dev, const char *name) 806 { 807 return enable_flash_ich_spi(dev, CHIPSET_ICH7, 0xdc); 808 } 809 810 static int enable_flash_ich8(struct pci_dev *dev, const char *name) 811 { 812 return enable_flash_ich_spi(dev, CHIPSET_ICH8, 0xdc); 813 } 814 815 static int enable_flash_ich9(struct pci_dev *dev, const char *name) 816 { 817 return enable_flash_ich_spi(dev, CHIPSET_ICH9, 0xdc); 818 } 819 820 static int enable_flash_ich10(struct pci_dev *dev, const char *name) 821 { 822 return enable_flash_ich_spi(dev, CHIPSET_ICH10, 0xdc); 823 } 824 825 /* Ibex Peak aka. 5 series & 3400 series */ 826 static int enable_flash_pch5(struct pci_dev *dev, const char *name) 827 { 828 return enable_flash_ich_spi(dev, CHIPSET_5_SERIES_IBEX_PEAK, 0xdc); 829 } 830 831 /* Cougar Point aka. 6 series & c200 series */ 832 static int enable_flash_pch6(struct pci_dev *dev, const char *name) 833 { 834 return enable_flash_ich_spi(dev, CHIPSET_6_SERIES_COUGAR_POINT, 0xdc); 835 } 836 837 /* Panther Point aka. 7 series */ 838 static int enable_flash_pch7(struct pci_dev *dev, const char *name) 839 { 840 return enable_flash_ich_spi(dev, CHIPSET_7_SERIES_PANTHER_POINT, 0xdc); 841 } 842 843 /* Lynx Point aka. 8 series */ 844 static int enable_flash_pch8(struct pci_dev *dev, const char *name) 845 { 846 return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT, 0xdc); 847 } 848 849 /* Lynx Point LP aka. 8 series low-power */ 850 static int enable_flash_pch8_lp(struct pci_dev *dev, const char *name) 851 { 852 return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT_LP, 0xdc); 853 } 854 855 /* Wellsburg (for Haswell-EP Xeons) */ 856 static int enable_flash_pch8_wb(struct pci_dev *dev, const char *name) 857 { 858 return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_WELLSBURG, 0xdc); 859 } 860 861 /* Wildcat Point */ 862 static int enable_flash_pch9(struct pci_dev *dev, const char *name) 863 { 864 return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT, 0xdc); 865 } 866 867 /* Wildcat Point LP */ 868 static int enable_flash_pch9_lp(struct pci_dev *dev, const char *name) 869 { 870 return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT_LP, 0xdc); 871 } 872 873 /* Sunrise Point */ 874 static int enable_flash_pch100_shutdown(void *const pci_acc) 875 { 876 pci_cleanup(pci_acc); 877 return 0; 878 } 879 880 static int enable_flash_pch100_or_c620( 881 struct pci_dev *const dev, const char *const name, 882 const int slot, const int func, const enum ich_chipset pch_generation) 883 { 884 int ret = ERROR_FATAL; 885 886 /* 887 * The SPI PCI device is usually hidden (by hiding PCI vendor 888 * and device IDs). So we need a PCI access method that works 889 * even when the OS doesn't know the PCI device. We can't use 890 * this method globally since it would bring along other con- 891 * straints (e.g. on PCI domains, extended PCIe config space). 892 */ 893 struct pci_access *const pci_acc = pci_alloc(); 894 struct pci_access *const saved_pacc = pacc; 895 if (!pci_acc) { 896 msg_perr("Can't allocate PCI accessor.\n"); 897 return ret; 898 } 899 pci_acc->method = PCI_ACCESS_I386_TYPE1; 900 pci_init(pci_acc); 901 register_shutdown(enable_flash_pch100_shutdown, pci_acc); 902 903 struct pci_dev *const spi_dev = pci_get_dev(pci_acc, dev->domain, dev->bus, slot, func); 904 if (!spi_dev) { 905 msg_perr("Can't allocate PCI device.\n"); 906 return ret; 907 } 908 909 /* Modify pacc so the rpci_write can register the undo callback with a 910 * device using the correct pci_access */ 911 pacc = pci_acc; 912 const enum chipbustype boot_buses = enable_flash_ich_report_gcs(spi_dev, pch_generation, NULL); 913 914 const int ret_bc = enable_flash_ich_bios_cntl_config_space(spi_dev, pch_generation, 0xdc); 915 if (ret_bc == ERROR_FATAL) 916 goto _freepci_ret; 917 918 const uint32_t phys_spibar = pci_read_long(spi_dev, PCI_BASE_ADDRESS_0) & 0xfffff000; 919 void *const spibar = rphysmap("SPIBAR", phys_spibar, 0x1000); 920 if (spibar == ERROR_PTR) 921 goto _freepci_ret; 922 msg_pdbg("SPIBAR = 0x%0*" PRIxPTR " (phys = 0x%08x)\n", PRIxPTR_WIDTH, (uintptr_t)spibar, phys_spibar); 923 924 /* This adds BUS_SPI */ 925 const int ret_spi = ich_init_spi(spibar, pch_generation); 926 if (ret_spi != ERROR_FATAL) { 927 if (ret_bc || ret_spi) 928 ret = ERROR_NONFATAL; 929 else 930 ret = 0; 931 } 932 933 /* Suppress unknown laptop warning if we booted from SPI. */ 934 if (!ret && (boot_buses & BUS_SPI)) 935 laptop_ok = 1; 936 937 _freepci_ret: 938 pci_free_dev(spi_dev); 939 pacc = saved_pacc; 940 return ret; 941 } 942 943 static int enable_flash_pch100(struct pci_dev *const dev, const char *const name) 944 { 945 return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_100_SERIES_SUNRISE_POINT); 946 } 947 948 static int enable_flash_c620(struct pci_dev *const dev, const char *const name) 949 { 950 return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_C620_SERIES_LEWISBURG); 951 } 952 953 static int enable_flash_pch300(struct pci_dev *const dev, const char *const name) 954 { 955 return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_300_SERIES_CANNON_POINT); 956 } 957 958 static int enable_flash_apl(struct pci_dev *const dev, const char *const name) 959 { 960 return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE); 961 } 962 963 /* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley. 964 * These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately. 965 * 966 * Differences include: 967 * - RCBA at LPC config 0xF0 too but mapped range is only 4 B long instead of 16 kB. 968 * - GCS at [RCRB] + 0 (instead of [RCRB] + 0x3410). 969 * - TS (Top Swap) in GCS (instead of [RCRB] + 0x3414). 970 * - SPIBAR (coined SBASE) at LPC config 0x54 (instead of [RCRB] + 0x3800). 971 * - BIOS_CNTL (coined BCR) at [SPIBAR] + 0xFC (instead of LPC config 0xDC). 972 */ 973 static int enable_flash_silvermont(struct pci_dev *dev, const char *name) 974 { 975 enum ich_chipset ich_generation = CHIPSET_BAYTRAIL; 976 977 /* Get physical address of Root Complex Register Block */ 978 uint32_t rcba = pci_read_long(dev, 0xf0) & 0xfffffc00; 979 msg_pdbg("Root Complex Register Block address = 0x%x\n", rcba); 980 981 /* Handle GCS (in RCRB) */ 982 void *rcrb = physmap("BYT RCRB", rcba, 4); 983 const enum chipbustype boot_buses = enable_flash_ich_report_gcs(dev, ich_generation, rcrb); 984 physunmap(rcrb, 4); 985 986 /* Handle fwh_idsel parameter */ 987 int ret_fwh = enable_flash_ich_fwh_decode(dev, ich_generation); 988 if (ret_fwh == ERROR_FATAL) 989 return ret_fwh; 990 991 internal_buses_supported &= BUS_FWH; 992 993 /* Get physical address of SPI Base Address and map it */ 994 uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00; 995 msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase); 996 void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */ 997 998 /* Enable Flash Writes. 999 * Silvermont-based: BCR at SBASE + 0xFC (some bits of BCR are also accessible via BC at IBASE + 0x1C). 1000 */ 1001 enable_flash_ich_bios_cntl_memmapped(ich_generation, spibar + 0xFC); 1002 1003 int ret_spi = ich_init_spi(spibar, ich_generation); 1004 if (ret_spi == ERROR_FATAL) 1005 return ret_spi; 1006 1007 if (((boot_buses & BUS_FWH) && ret_fwh) || ((boot_buses & BUS_SPI) && ret_spi)) 1008 return ERROR_NONFATAL; 1009 1010 /* Suppress unknown laptop warning if we booted from SPI. */ 1011 if (boot_buses & BUS_SPI) 1012 laptop_ok = 1; 1013 1014 return 0; 1015 } 1016 1017 static int via_no_byte_merge(struct pci_dev *dev, const char *name) 1018 { 1019 uint8_t val; 1020 1021 val = pci_read_byte(dev, 0x71); 1022 if (val & 0x40) { 1023 msg_pdbg("Disabling byte merging\n"); 1024 val &= ~0x40; 1025 rpci_write_byte(dev, 0x71, val); 1026 } 1027 return NOT_DONE_YET; /* need to find south bridge, too */ 1028 } 1029 1030 static int enable_flash_vt823x(struct pci_dev *dev, const char *name) 1031 { 1032 uint8_t val; 1033 1034 /* Enable ROM decode range (1MB) FFC00000 - FFFFFFFF. */ 1035 rpci_write_byte(dev, 0x41, 0x7f); 1036 1037 /* ROM write enable */ 1038 val = pci_read_byte(dev, 0x40); 1039 val |= 0x10; 1040 rpci_write_byte(dev, 0x40, val); 1041 1042 if (pci_read_byte(dev, 0x40) != val) { 1043 msg_pwarn("\nWarning: Failed to enable flash write on \"%s\"\n", name); 1044 return -1; 1045 } 1046 1047 if (dev->device_id == 0x3227) { /* VT8237/VT8237R */ 1048 /* All memory cycles, not just ROM ones, go to LPC. */ 1049 val = pci_read_byte(dev, 0x59); 1050 val &= ~0x80; 1051 rpci_write_byte(dev, 0x59, val); 1052 } 1053 1054 return 0; 1055 } 1056 1057 static int enable_flash_vt_vx(struct pci_dev *dev, const char *name) 1058 { 1059 struct pci_dev *south_north = pci_dev_find(0x1106, 0xa353); 1060 if (south_north == NULL) { 1061 msg_perr("Could not find South-North Module Interface Control device!\n"); 1062 return ERROR_FATAL; 1063 } 1064 1065 msg_pdbg("Strapped to "); 1066 if ((pci_read_byte(south_north, 0x56) & 0x01) == 0) { 1067 msg_pdbg("LPC.\n"); 1068 return enable_flash_vt823x(dev, name); 1069 } 1070 msg_pdbg("SPI.\n"); 1071 1072 uint32_t mmio_base; 1073 void *mmio_base_physmapped; 1074 uint32_t spi_cntl; 1075 #define SPI_CNTL_LEN 0x08 1076 uint32_t spi0_mm_base = 0; 1077 switch(dev->device_id) { 1078 case 0x8353: /* VX800/VX820 */ 1079 spi0_mm_base = pci_read_long(dev, 0xbc) << 8; 1080 if (spi0_mm_base == 0x0) { 1081 msg_pdbg ("MMIO not enabled!\n"); 1082 return ERROR_FATAL; 1083 } 1084 break; 1085 case 0x8409: /* VX855/VX875 */ 1086 case 0x8410: /* VX900 */ 1087 mmio_base = pci_read_long(dev, 0xbc) << 8; 1088 if (mmio_base == 0x0) { 1089 msg_pdbg ("MMIO not enabled!\n"); 1090 return ERROR_FATAL; 1091 } 1092 mmio_base_physmapped = physmap("VIA VX MMIO register", mmio_base, SPI_CNTL_LEN); 1093 if (mmio_base_physmapped == ERROR_PTR) 1094 return ERROR_FATAL; 1095 1096 /* Offset 0 - Bit 0 holds SPI Bus0 Enable Bit. */ 1097 spi_cntl = mmio_readl(mmio_base_physmapped) + 0x00; 1098 if ((spi_cntl & 0x01) == 0) { 1099 msg_pdbg ("SPI Bus0 disabled!\n"); 1100 physunmap(mmio_base_physmapped, SPI_CNTL_LEN); 1101 return ERROR_FATAL; 1102 } 1103 /* Offset 1-3 has SPI Bus Memory Map Base Address: */ 1104 spi0_mm_base = spi_cntl & 0xFFFFFF00; 1105 1106 /* Offset 4 - Bit 0 holds SPI Bus1 Enable Bit. */ 1107 spi_cntl = mmio_readl(mmio_base_physmapped) + 0x04; 1108 if ((spi_cntl & 0x01) == 1) 1109 msg_pdbg2("SPI Bus1 is enabled too.\n"); 1110 1111 physunmap(mmio_base_physmapped, SPI_CNTL_LEN); 1112 break; 1113 default: 1114 msg_perr("%s: Unsupported chipset %x:%x!\n", __func__, dev->vendor_id, dev->device_id); 1115 return ERROR_FATAL; 1116 } 1117 1118 return via_init_spi(spi0_mm_base); 1119 } 1120 1121 static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name) 1122 { 1123 return via_init_spi(pci_read_long(dev, 0xbc) << 8); 1124 } 1125 1126 static int enable_flash_cs5530(struct pci_dev *dev, const char *name) 1127 { 1128 uint8_t reg8; 1129 1130 #define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */ 1131 #define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */ 1132 #define CS5530_RESET_CONTROL_REG 0x44 /* F0 index 0x44 */ 1133 #define CS5530_USB_SHADOW_REG 0x43 /* F0 index 0x43 */ 1134 1135 #define LOWER_ROM_ADDRESS_RANGE (1 << 0) 1136 #define ROM_WRITE_ENABLE (1 << 1) 1137 #define UPPER_ROM_ADDRESS_RANGE (1 << 2) 1138 #define BIOS_ROM_POSITIVE_DECODE (1 << 5) 1139 #define CS5530_ISA_MASTER (1 << 7) 1140 #define CS5530_ENABLE_SA2320 (1 << 2) 1141 #define CS5530_ENABLE_SA20 (1 << 6) 1142 1143 internal_buses_supported &= BUS_PARALLEL; 1144 /* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and 1145 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB. 1146 * FIXME: Should we really touch the low mapping below 1 MB? Flashrom 1147 * ignores that region completely. 1148 * Make the configured ROM areas writable. 1149 */ 1150 reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG); 1151 reg8 |= LOWER_ROM_ADDRESS_RANGE; 1152 reg8 |= UPPER_ROM_ADDRESS_RANGE; 1153 reg8 |= ROM_WRITE_ENABLE; 1154 rpci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8); 1155 1156 /* Set positive decode on ROM. */ 1157 reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2); 1158 reg8 |= BIOS_ROM_POSITIVE_DECODE; 1159 rpci_write_byte(dev, DECODE_CONTROL_REG2, reg8); 1160 1161 reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG); 1162 if (reg8 & CS5530_ISA_MASTER) { 1163 /* We have A0-A23 available. */ 1164 max_rom_decode.parallel = 16 * 1024 * 1024; 1165 } else { 1166 reg8 = pci_read_byte(dev, CS5530_USB_SHADOW_REG); 1167 if (reg8 & CS5530_ENABLE_SA2320) { 1168 /* We have A0-19, A20-A23 available. */ 1169 max_rom_decode.parallel = 16 * 1024 * 1024; 1170 } else if (reg8 & CS5530_ENABLE_SA20) { 1171 /* We have A0-19, A20 available. */ 1172 max_rom_decode.parallel = 2 * 1024 * 1024; 1173 } else { 1174 /* A20 and above are not active. */ 1175 max_rom_decode.parallel = 1024 * 1024; 1176 } 1177 } 1178 1179 return 0; 1180 } 1181 1182 /* 1183 * Geode systems write protect the BIOS via RCONFs (cache settings similar 1184 * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22. 1185 * 1186 * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL. 1187 * To enable write to NOR Boot flash for the benefit of systems that have such 1188 * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select). 1189 */ 1190 static int enable_flash_cs5536(struct pci_dev *dev, const char *name) 1191 { 1192 #define MSR_RCONF_DEFAULT 0x1808 1193 #define MSR_NORF_CTL 0x51400018 1194 1195 msr_t msr; 1196 1197 /* Geode only has a single core */ 1198 if (setup_cpu_msr(0)) 1199 return -1; 1200 1201 msr = rdmsr(MSR_RCONF_DEFAULT); 1202 if ((msr.hi >> 24) != 0x22) { 1203 msr.hi &= 0xfbffffff; 1204 wrmsr(MSR_RCONF_DEFAULT, msr); 1205 } 1206 1207 msr = rdmsr(MSR_NORF_CTL); 1208 /* Raise WE_CS3 bit. */ 1209 msr.lo |= 0x08; 1210 wrmsr(MSR_NORF_CTL, msr); 1211 1212 cleanup_cpu_msr(); 1213 1214 #undef MSR_RCONF_DEFAULT 1215 #undef MSR_NORF_CTL 1216 return 0; 1217 } 1218 1219 static int enable_flash_sc1100(struct pci_dev *dev, const char *name) 1220 { 1221 #define SC_REG 0x52 1222 uint8_t new; 1223 1224 rpci_write_byte(dev, SC_REG, 0xee); 1225 1226 new = pci_read_byte(dev, SC_REG); 1227 1228 if (new != 0xee) { /* FIXME: share this with other code? */ 1229 msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", SC_REG, new, name); 1230 return -1; 1231 } 1232 1233 return 0; 1234 } 1235 1236 /* Works for AMD-768, AMD-8111, VIA VT82C586A/B, VIA VT82C596, VIA VT82C686A/B. 1237 * 1238 * ROM decode control register matrix 1239 * AMD-768 AMD-8111 VT82C586A/B VT82C596 VT82C686A/B 1240 * 7 FFC0_0000h–FFFF_FFFFh <- FFFE0000h-FFFEFFFFh <- <- 1241 * 6 FFB0_0000h–FFBF_FFFFh <- FFF80000h-FFFDFFFFh <- <- 1242 * 5 00E8... <- <- FFF00000h-FFF7FFFFh <- 1243 */ 1244 static int enable_flash_amd_via(struct pci_dev *dev, const char *name, uint8_t decode_val) 1245 { 1246 #define AMD_MAPREG 0x43 1247 #define AMD_ENREG 0x40 1248 uint8_t old, new; 1249 1250 old = pci_read_byte(dev, AMD_MAPREG); 1251 new = old | decode_val; 1252 if (new != old) { 1253 rpci_write_byte(dev, AMD_MAPREG, new); 1254 if (pci_read_byte(dev, AMD_MAPREG) != new) { 1255 msg_pwarn("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", 1256 AMD_MAPREG, new, name); 1257 } else 1258 msg_pdbg("Changed ROM decode range to 0x%02x successfully.\n", new); 1259 } 1260 1261 /* Enable 'ROM write' bit. */ 1262 old = pci_read_byte(dev, AMD_ENREG); 1263 new = old | 0x01; 1264 if (new == old) 1265 return 0; 1266 rpci_write_byte(dev, AMD_ENREG, new); 1267 1268 if (pci_read_byte(dev, AMD_ENREG) != new) { 1269 msg_pwarn("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", 1270 AMD_ENREG, new, name); 1271 return ERROR_NONFATAL; 1272 } 1273 msg_pdbg2("Set ROM enable bit successfully.\n"); 1274 1275 return 0; 1276 } 1277 1278 static int enable_flash_amd_768_8111(struct pci_dev *dev, const char *name) 1279 { 1280 /* Enable decoding of 0xFFB00000 to 0xFFFFFFFF (5 MB). */ 1281 max_rom_decode.lpc = 5 * 1024 * 1024; 1282 return enable_flash_amd_via(dev, name, 0xC0); 1283 } 1284 1285 static int enable_flash_vt82c586(struct pci_dev *dev, const char *name) 1286 { 1287 /* Enable decoding of 0xFFF80000 to 0xFFFFFFFF. (512 kB) */ 1288 max_rom_decode.parallel = 512 * 1024; 1289 return enable_flash_amd_via(dev, name, 0xC0); 1290 } 1291 1292 /* Works for VT82C686A/B too. */ 1293 static int enable_flash_vt82c596(struct pci_dev *dev, const char *name) 1294 { 1295 /* Enable decoding of 0xFFF00000 to 0xFFFFFFFF. (1 MB) */ 1296 max_rom_decode.parallel = 1024 * 1024; 1297 return enable_flash_amd_via(dev, name, 0xE0); 1298 } 1299 1300 static int enable_flash_sb600(struct pci_dev *dev, const char *name) 1301 { 1302 uint32_t prot; 1303 uint8_t reg; 1304 int ret; 1305 1306 /* Clear ROM protect 0-3. */ 1307 for (reg = 0x50; reg < 0x60; reg += 4) { 1308 prot = pci_read_long(dev, reg); 1309 /* No protection flags for this region?*/ 1310 if ((prot & 0x3) == 0) 1311 continue; 1312 msg_pdbg("Chipset %s%sprotected flash from 0x%08x to 0x%08x, unlocking...", 1313 (prot & 0x2) ? "read " : "", 1314 (prot & 0x1) ? "write " : "", 1315 (prot & 0xfffff800), 1316 (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff)); 1317 prot &= 0xfffffffc; 1318 rpci_write_byte(dev, reg, prot); 1319 prot = pci_read_long(dev, reg); 1320 if ((prot & 0x3) != 0) { 1321 msg_perr("Disabling %s%sprotection of flash addresses from 0x%08x to 0x%08x failed.\n", 1322 (prot & 0x2) ? "read " : "", 1323 (prot & 0x1) ? "write " : "", 1324 (prot & 0xfffff800), 1325 (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff)); 1326 continue; 1327 } 1328 msg_pdbg("done.\n"); 1329 } 1330 1331 internal_buses_supported &= BUS_LPC | BUS_FWH; 1332 1333 ret = sb600_probe_spi(dev); 1334 1335 /* Read ROM strap override register. */ 1336 OUTB(0x8f, 0xcd6); 1337 reg = INB(0xcd7); 1338 reg &= 0x0e; 1339 msg_pdbg("ROM strap override is %sactive", (reg & 0x02) ? "" : "not "); 1340 if (reg & 0x02) { 1341 switch ((reg & 0x0c) >> 2) { 1342 case 0x00: 1343 msg_pdbg(": LPC"); 1344 break; 1345 case 0x01: 1346 msg_pdbg(": PCI"); 1347 break; 1348 case 0x02: 1349 msg_pdbg(": FWH"); 1350 break; 1351 case 0x03: 1352 msg_pdbg(": SPI"); 1353 break; 1354 } 1355 } 1356 msg_pdbg("\n"); 1357 1358 /* Force enable SPI ROM in SB600 PM register. 1359 * If we enable SPI ROM here, we have to disable it after we leave. 1360 * But how can we know which ROM we are going to handle? So we have 1361 * to trade off. We only access LPC ROM if we boot via LPC ROM. And 1362 * only SPI ROM if we boot via SPI ROM. If you want to access SPI on 1363 * boards with LPC straps, you have to use the code below. 1364 */ 1365 /* 1366 OUTB(0x8f, 0xcd6); 1367 OUTB(0x0e, 0xcd7); 1368 */ 1369 1370 return ret; 1371 } 1372 1373 /* sets bit 0 in 0x6d */ 1374 static int enable_flash_nvidia_common(struct pci_dev *dev, const char *name) 1375 { 1376 uint8_t old, new; 1377 1378 old = pci_read_byte(dev, 0x6d); 1379 new = old | 0x01; 1380 if (new == old) 1381 return 0; 1382 1383 rpci_write_byte(dev, 0x6d, new); 1384 if (pci_read_byte(dev, 0x6d) != new) { 1385 msg_pinfo("Setting register 0x6d to 0x%02x on %s failed.\n", new, name); 1386 return 1; 1387 } 1388 return 0; 1389 } 1390 1391 static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name) 1392 { 1393 rpci_write_byte(dev, 0x92, 0); 1394 if (enable_flash_nvidia_common(dev, name)) 1395 return ERROR_NONFATAL; 1396 else 1397 return 0; 1398 } 1399 1400 static int enable_flash_ck804(struct pci_dev *dev, const char *name) 1401 { 1402 uint32_t segctrl; 1403 uint8_t reg, old, new; 1404 unsigned int err = 0; 1405 1406 /* 0x8A is special: it is a single byte and only one nibble is touched. */ 1407 reg = 0x8A; 1408 segctrl = pci_read_byte(dev, reg); 1409 if ((segctrl & 0x3) != 0x0) { 1410 if ((segctrl & 0xC) != 0x0) { 1411 msg_pinfo("Can not unlock existing protection in register 0x%02x.\n", reg); 1412 err++; 1413 } else { 1414 msg_pdbg("Unlocking protection in register 0x%02x... ", reg); 1415 rpci_write_byte(dev, reg, segctrl & 0xF0); 1416 1417 segctrl = pci_read_byte(dev, reg); 1418 if ((segctrl & 0x3) != 0x0) { 1419 msg_pinfo("Could not unlock protection in register 0x%02x (new value: 0x%x).\n", 1420 reg, segctrl); 1421 err++; 1422 } else 1423 msg_pdbg("OK\n"); 1424 } 1425 } 1426 1427 for (reg = 0x8C; reg <= 0x94; reg += 4) { 1428 segctrl = pci_read_long(dev, reg); 1429 if ((segctrl & 0x33333333) == 0x00000000) { 1430 /* reads and writes are unlocked */ 1431 continue; 1432 } 1433 if ((segctrl & 0xCCCCCCCC) != 0x00000000) { 1434 msg_pinfo("Can not unlock existing protection in register 0x%02x.\n", reg); 1435 err++; 1436 continue; 1437 } 1438 msg_pdbg("Unlocking protection in register 0x%02x... ", reg); 1439 rpci_write_long(dev, reg, 0x00000000); 1440 1441 segctrl = pci_read_long(dev, reg); 1442 if ((segctrl & 0x33333333) != 0x00000000) { 1443 msg_pinfo("Could not unlock protection in register 0x%02x (new value: 0x%08x).\n", 1444 reg, segctrl); 1445 err++; 1446 } else 1447 msg_pdbg("OK\n"); 1448 } 1449 1450 if (err > 0) { 1451 msg_pinfo("%d locks could not be disabled, disabling writes (reads may also fail).\n", err); 1452 programmer_may_write = 0; 1453 } 1454 1455 reg = 0x88; 1456 old = pci_read_byte(dev, reg); 1457 new = old | 0xC0; 1458 if (new != old) { 1459 rpci_write_byte(dev, reg, new); 1460 if (pci_read_byte(dev, reg) != new) { /* FIXME: share this with other code? */ 1461 msg_pinfo("Setting register 0x%02x to 0x%02x on %s failed.\n", reg, new, name); 1462 err++; 1463 } 1464 } 1465 1466 if (enable_flash_nvidia_common(dev, name)) 1467 err++; 1468 1469 if (err > 0) 1470 return ERROR_NONFATAL; 1471 else 1472 return 0; 1473 } 1474 1475 static int enable_flash_osb4(struct pci_dev *dev, const char *name) 1476 { 1477 uint8_t tmp; 1478 1479 internal_buses_supported &= BUS_PARALLEL; 1480 1481 tmp = INB(0xc06); 1482 tmp |= 0x1; 1483 OUTB(tmp, 0xc06); 1484 1485 tmp = INB(0xc6f); 1486 tmp |= 0x40; 1487 OUTB(tmp, 0xc6f); 1488 1489 return 0; 1490 } 1491 1492 /* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */ 1493 static int enable_flash_sb400(struct pci_dev *dev, const char *name) 1494 { 1495 uint8_t tmp; 1496 struct pci_dev *smbusdev; 1497 1498 /* Look for the SMBus device. */ 1499 smbusdev = pci_dev_find(0x1002, 0x4372); 1500 1501 if (!smbusdev) { 1502 msg_perr("ERROR: SMBus device not found. Aborting.\n"); 1503 return ERROR_FATAL; 1504 } 1505 1506 /* Enable some SMBus stuff. */ 1507 tmp = pci_read_byte(smbusdev, 0x79); 1508 tmp |= 0x01; 1509 rpci_write_byte(smbusdev, 0x79, tmp); 1510 1511 /* Change southbridge. */ 1512 tmp = pci_read_byte(dev, 0x48); 1513 tmp |= 0x21; 1514 rpci_write_byte(dev, 0x48, tmp); 1515 1516 /* Now become a bit silly. */ 1517 tmp = INB(0xc6f); 1518 OUTB(tmp, 0xeb); 1519 OUTB(tmp, 0xeb); 1520 tmp |= 0x40; 1521 OUTB(tmp, 0xc6f); 1522 OUTB(tmp, 0xeb); 1523 OUTB(tmp, 0xeb); 1524 1525 return 0; 1526 } 1527 1528 static int enable_flash_mcp55(struct pci_dev *dev, const char *name) 1529 { 1530 uint8_t val; 1531 uint16_t wordval; 1532 1533 /* Set the 0-16 MB enable bits. */ 1534 val = pci_read_byte(dev, 0x88); 1535 val |= 0xff; /* 256K */ 1536 rpci_write_byte(dev, 0x88, val); 1537 val = pci_read_byte(dev, 0x8c); 1538 val |= 0xff; /* 1M */ 1539 rpci_write_byte(dev, 0x8c, val); 1540 wordval = pci_read_word(dev, 0x90); 1541 wordval |= 0x7fff; /* 16M */ 1542 rpci_write_word(dev, 0x90, wordval); 1543 1544 if (enable_flash_nvidia_common(dev, name)) 1545 return ERROR_NONFATAL; 1546 else 1547 return 0; 1548 } 1549 1550 /* 1551 * The MCP6x/MCP7x code is based on cleanroom reverse engineering. 1552 * It is assumed that LPC chips need the MCP55 code and SPI chips need the 1553 * code provided in enable_flash_mcp6x_7x_common. 1554 */ 1555 static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name) 1556 { 1557 int ret = 0, want_spi = 0; 1558 uint8_t val; 1559 1560 /* dev is the ISA bridge. No idea what the stuff below does. */ 1561 val = pci_read_byte(dev, 0x8a); 1562 msg_pdbg("ISA/LPC bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 " 1563 "is %i\n", val, (val >> 6) & 0x1, (val >> 5) & 0x1); 1564 1565 switch ((val >> 5) & 0x3) { 1566 case 0x0: 1567 ret = enable_flash_mcp55(dev, name); 1568 internal_buses_supported &= BUS_LPC; 1569 msg_pdbg("Flash bus type is LPC\n"); 1570 break; 1571 case 0x2: 1572 want_spi = 1; 1573 /* SPI is added in mcp6x_spi_init if it works. 1574 * Do we really want to disable LPC in this case? 1575 */ 1576 internal_buses_supported = BUS_NONE; 1577 msg_pdbg("Flash bus type is SPI\n"); 1578 break; 1579 default: 1580 /* Should not happen. */ 1581 internal_buses_supported = BUS_NONE; 1582 msg_pwarn("Flash bus type is unknown (none)\n"); 1583 msg_pinfo("Please send the log files created by \"flashrom -p internal -o logfile\" to\n" 1584 "flashrom@flashrom.org with \"your board name: flashrom -V\" as the subject to\n" 1585 "help us finish support for your chipset. Thanks.\n"); 1586 return ERROR_NONFATAL; 1587 } 1588 1589 /* Force enable SPI and disable LPC? Not a good idea. */ 1590 #if 0 1591 val |= (1 << 6); 1592 val &= ~(1 << 5); 1593 rpci_write_byte(dev, 0x8a, val); 1594 #endif 1595 1596 if (mcp6x_spi_init(want_spi)) 1597 ret = 1; 1598 1599 /* Suppress unknown laptop warning if we booted from SPI. */ 1600 if (!ret && want_spi) 1601 laptop_ok = 1; 1602 1603 return ret; 1604 } 1605 1606 static int enable_flash_ht1000(struct pci_dev *dev, const char *name) 1607 { 1608 uint8_t val; 1609 1610 /* Set the 4MB enable bit. */ 1611 val = pci_read_byte(dev, 0x41); 1612 val |= 0x0e; 1613 rpci_write_byte(dev, 0x41, val); 1614 1615 val = pci_read_byte(dev, 0x43); 1616 val |= (1 << 4); 1617 rpci_write_byte(dev, 0x43, val); 1618 1619 return 0; 1620 } 1621 1622 /* 1623 * Usually on the x86 architectures (and on other PC-like platforms like some 1624 * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD 1625 * Elan SC520 only a small piece of the system flash is mapped there, but the 1626 * complete flash is mapped somewhere below 1G. The position can be determined 1627 * by the BOOTCS PAR register. 1628 */ 1629 static int get_flashbase_sc520(struct pci_dev *dev, const char *name) 1630 { 1631 int i, bootcs_found = 0; 1632 uint32_t parx = 0; 1633 void *mmcr; 1634 1635 /* 1. Map MMCR */ 1636 mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize()); 1637 if (mmcr == ERROR_PTR) 1638 return ERROR_FATAL; 1639 1640 /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for 1641 * BOOTCS region (PARx[31:29] = 100b)e 1642 */ 1643 for (i = 0x88; i <= 0xc4; i += 4) { 1644 parx = mmio_readl(mmcr + i); 1645 if ((parx >> 29) == 4) { 1646 bootcs_found = 1; 1647 break; /* BOOTCS found */ 1648 } 1649 } 1650 1651 /* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0] 1652 * PARx[25] = 0b --> flashbase[29:12] = PARx[17:0] 1653 */ 1654 if (bootcs_found) { 1655 if (parx & (1 << 25)) { 1656 parx &= (1 << 14) - 1; /* Mask [13:0] */ 1657 flashbase = parx << 16; 1658 } else { 1659 parx &= (1 << 18) - 1; /* Mask [17:0] */ 1660 flashbase = parx << 12; 1661 } 1662 } else { 1663 msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. " 1664 "Assuming flash at 4G.\n"); 1665 } 1666 1667 /* 4. Clean up */ 1668 physunmap(mmcr, getpagesize()); 1669 return 0; 1670 } 1671 1672 #endif 1673 1674 #define B_P (BUS_PARALLEL) 1675 #define B_PFL (BUS_NONSPI) 1676 #define B_PFLS (BUS_NONSPI | BUS_SPI) 1677 #define B_FL (BUS_FWH | BUS_LPC) 1678 #define B_FLS (BUS_FWH | BUS_LPC | BUS_SPI) 1679 #define B_FS (BUS_FWH | BUS_SPI) 1680 #define B_L (BUS_LPC) 1681 #define B_LS (BUS_LPC | BUS_SPI) 1682 #define B_S (BUS_SPI) 1683 1684 /* Please keep this list numerically sorted by vendor/device ID. */ 1685 const struct penable chipset_enables[] = { 1686 #if defined(__i386__) || defined(__x86_64__) 1687 {0x1002, 0x4377, B_PFL, OK, "ATI", "SB400", enable_flash_sb400}, 1688 {0x1002, 0x438d, B_FLS, OK, "AMD", "SB600", enable_flash_sb600}, 1689 {0x1002, 0x439d, B_FLS, OK, "AMD", "SB7x0/SB8x0/SB9x0", enable_flash_sb600}, 1690 {0x100b, 0x0510, B_PFL, NT, "AMD", "SC1100", enable_flash_sc1100}, 1691 {0x1022, 0x2080, B_PFL, OK, "AMD", "CS5536", enable_flash_cs5536}, 1692 {0x1022, 0x2090, B_PFL, OK, "AMD", "CS5536", enable_flash_cs5536}, 1693 {0x1022, 0x3000, B_PFL, OK, "AMD", "Elan SC520", get_flashbase_sc520}, 1694 {0x1022, 0x7440, B_PFL, OK, "AMD", "AMD-768", enable_flash_amd_768_8111}, 1695 {0x1022, 0x7468, B_PFL, OK, "AMD", "AMD-8111", enable_flash_amd_768_8111}, 1696 {0x1022, 0x780e, B_FLS, OK, "AMD", "FCH", enable_flash_sb600}, 1697 {0x1022, 0x790e, B_FLS, OK, "AMD", "FP4", enable_flash_sb600}, 1698 {0x1039, 0x0406, B_PFL, NT, "SiS", "501/5101/5501", enable_flash_sis501}, 1699 {0x1039, 0x0496, B_PFL, NT, "SiS", "85C496+497", enable_flash_sis85c496}, 1700 {0x1039, 0x0530, B_PFL, OK, "SiS", "530", enable_flash_sis530}, 1701 {0x1039, 0x0540, B_PFL, NT, "SiS", "540", enable_flash_sis540}, 1702 {0x1039, 0x0620, B_PFL, NT, "SiS", "620", enable_flash_sis530}, 1703 {0x1039, 0x0630, B_PFL, OK, "SiS", "630", enable_flash_sis540}, 1704 {0x1039, 0x0635, B_PFL, NT, "SiS", "635", enable_flash_sis540}, 1705 {0x1039, 0x0640, B_PFL, NT, "SiS", "640", enable_flash_sis540}, 1706 {0x1039, 0x0645, B_PFL, NT, "SiS", "645", enable_flash_sis540}, 1707 {0x1039, 0x0646, B_PFL, OK, "SiS", "645DX", enable_flash_sis540}, 1708 {0x1039, 0x0648, B_PFL, OK, "SiS", "648", enable_flash_sis540}, 1709 {0x1039, 0x0650, B_PFL, OK, "SiS", "650", enable_flash_sis540}, 1710 {0x1039, 0x0651, B_PFL, OK, "SiS", "651", enable_flash_sis540}, 1711 {0x1039, 0x0655, B_PFL, NT, "SiS", "655", enable_flash_sis540}, 1712 {0x1039, 0x0661, B_PFL, OK, "SiS", "661", enable_flash_sis540}, 1713 {0x1039, 0x0730, B_PFL, OK, "SiS", "730", enable_flash_sis540}, 1714 {0x1039, 0x0733, B_PFL, NT, "SiS", "733", enable_flash_sis540}, 1715 {0x1039, 0x0735, B_PFL, OK, "SiS", "735", enable_flash_sis540}, 1716 {0x1039, 0x0740, B_PFL, NT, "SiS", "740", enable_flash_sis540}, 1717 {0x1039, 0x0741, B_PFL, OK, "SiS", "741", enable_flash_sis540}, 1718 {0x1039, 0x0745, B_PFL, OK, "SiS", "745", enable_flash_sis540}, 1719 {0x1039, 0x0746, B_PFL, NT, "SiS", "746", enable_flash_sis540}, 1720 {0x1039, 0x0748, B_PFL, NT, "SiS", "748", enable_flash_sis540}, 1721 {0x1039, 0x0755, B_PFL, OK, "SiS", "755", enable_flash_sis540}, 1722 {0x1039, 0x5511, B_PFL, NT, "SiS", "5511", enable_flash_sis5511}, 1723 {0x1039, 0x5571, B_PFL, NT, "SiS", "5571", enable_flash_sis530}, 1724 {0x1039, 0x5591, B_PFL, NT, "SiS", "5591/5592", enable_flash_sis530}, 1725 {0x1039, 0x5596, B_PFL, NT, "SiS", "5596", enable_flash_sis5511}, 1726 {0x1039, 0x5597, B_PFL, NT, "SiS", "5597/5598/5581/5120", enable_flash_sis530}, 1727 {0x1039, 0x5600, B_PFL, NT, "SiS", "600", enable_flash_sis530}, 1728 {0x1078, 0x0100, B_P, OK, "AMD", "CS5530(A)", enable_flash_cs5530}, 1729 {0x10b9, 0x1533, B_PFL, OK, "ALi", "M1533", enable_flash_ali_m1533}, 1730 {0x10de, 0x0030, B_PFL, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2}, 1731 {0x10de, 0x0050, B_PFL, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */ 1732 {0x10de, 0x0051, B_PFL, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */ 1733 {0x10de, 0x0060, B_PFL, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2}, 1734 {0x10de, 0x00e0, B_PFL, OK, "NVIDIA", "NForce3", enable_flash_nvidia_nforce2}, 1735 /* Slave, should not be here, to fix known bug for A01. */ 1736 {0x10de, 0x00d3, B_PFL, OK, "NVIDIA", "CK804", enable_flash_ck804}, 1737 {0x10de, 0x0260, B_PFL, OK, "NVIDIA", "MCP51", enable_flash_ck804}, 1738 {0x10de, 0x0261, B_PFL, OK, "NVIDIA", "MCP51", enable_flash_ck804}, 1739 {0x10de, 0x0262, B_PFL, NT, "NVIDIA", "MCP51", enable_flash_ck804}, 1740 {0x10de, 0x0263, B_PFL, NT, "NVIDIA", "MCP51", enable_flash_ck804}, 1741 {0x10de, 0x0360, B_L, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/ 1742 /* 10de:0361 is present in Tyan S2915 OEM systems, but not connected to 1743 * the flash chip. Instead, 10de:0364 is connected to the flash chip. 1744 * Until we have PCI device class matching or some fallback mechanism, 1745 * this is needed to get flashrom working on Tyan S2915 and maybe other 1746 * dual-MCP55 boards. 1747 */ 1748 #if 0 1749 {0x10de, 0x0361, B_L, NT, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ 1750 #endif 1751 {0x10de, 0x0362, B_L, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ 1752 {0x10de, 0x0363, B_L, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ 1753 {0x10de, 0x0364, B_L, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ 1754 {0x10de, 0x0365, B_L, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ 1755 {0x10de, 0x0366, B_L, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ 1756 {0x10de, 0x0367, B_L, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */ 1757 {0x10de, 0x03e0, B_LS, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, 1758 {0x10de, 0x03e1, B_LS, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, 1759 {0x10de, 0x03e3, B_LS, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, 1760 {0x10de, 0x0440, B_LS, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, 1761 {0x10de, 0x0441, B_LS, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, 1762 {0x10de, 0x0442, B_LS, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, 1763 {0x10de, 0x0443, B_LS, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, 1764 {0x10de, 0x0548, B_LS, OK, "NVIDIA", "MCP67", enable_flash_mcp6x_7x}, 1765 {0x10de, 0x075c, B_LS, OK, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x}, 1766 {0x10de, 0x075d, B_LS, OK, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x}, 1767 {0x10de, 0x07d7, B_LS, OK, "NVIDIA", "MCP73", enable_flash_mcp6x_7x}, 1768 {0x10de, 0x0aac, B_LS, OK, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, 1769 {0x10de, 0x0aad, B_LS, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, 1770 {0x10de, 0x0aae, B_LS, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, 1771 {0x10de, 0x0aaf, B_LS, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, 1772 {0x10de, 0x0d80, B_LS, NT, "NVIDIA", "MCP89", enable_flash_mcp6x_7x}, 1773 /* VIA northbridges */ 1774 {0x1106, 0x0585, B_PFLS, NT, "VIA", "VT82C585VPX", via_no_byte_merge}, 1775 {0x1106, 0x0595, B_PFLS, NT, "VIA", "VT82C595", via_no_byte_merge}, 1776 {0x1106, 0x0597, B_PFLS, NT, "VIA", "VT82C597", via_no_byte_merge}, 1777 {0x1106, 0x0601, B_PFLS, NT, "VIA", "VT8601/VT8601A", via_no_byte_merge}, 1778 {0x1106, 0x0691, B_PFLS, OK, "VIA", "VT82C69x", via_no_byte_merge}, 1779 {0x1106, 0x8601, B_PFLS, NT, "VIA", "VT8601T", via_no_byte_merge}, 1780 /* VIA southbridges */ 1781 {0x1106, 0x0586, B_PFL, OK, "VIA", "VT82C586A/B", enable_flash_vt82c586}, 1782 {0x1106, 0x0596, B_PFL, OK, "VIA", "VT82C596", enable_flash_vt82c596}, 1783 {0x1106, 0x0686, B_PFL, OK, "VIA", "VT82C686A/B", enable_flash_vt82c596}, 1784 {0x1106, 0x3074, B_FL, OK, "VIA", "VT8233", enable_flash_vt823x}, 1785 {0x1106, 0x3147, B_FL, OK, "VIA", "VT8233A", enable_flash_vt823x}, 1786 {0x1106, 0x3177, B_FL, OK, "VIA", "VT8235", enable_flash_vt823x}, 1787 {0x1106, 0x3227, B_FL, OK, "VIA", "VT8237(R)", enable_flash_vt823x}, 1788 {0x1106, 0x3287, B_FL, OK, "VIA", "VT8251", enable_flash_vt823x}, 1789 {0x1106, 0x3337, B_FL, OK, "VIA", "VT8237A", enable_flash_vt823x}, 1790 {0x1106, 0x3372, B_LS, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi}, 1791 {0x1106, 0x8231, B_FL, NT, "VIA", "VT8231", enable_flash_vt823x}, 1792 {0x1106, 0x8324, B_FL, OK, "VIA", "CX700", enable_flash_vt823x}, 1793 {0x1106, 0x8353, B_FLS, NT, "VIA", "VX800/VX820", enable_flash_vt_vx}, 1794 {0x1106, 0x8409, B_FLS, OK, "VIA", "VX855/VX875", enable_flash_vt_vx}, 1795 {0x1106, 0x8410, B_FLS, OK, "VIA", "VX900", enable_flash_vt_vx}, 1796 {0x1166, 0x0200, B_P, OK, "Broadcom", "OSB4", enable_flash_osb4}, 1797 {0x1166, 0x0205, B_PFL, OK, "Broadcom", "HT-1000", enable_flash_ht1000}, 1798 {0x17f3, 0x6030, B_PFL, OK, "RDC", "R8610/R3210", enable_flash_rdc_r8610}, 1799 {0x8086, 0x0c60, B_FS, NT, "Intel", "S12x0", enable_flash_s12x0}, 1800 {0x8086, 0x0f1c, B_FS, OK, "Intel", "Bay Trail", enable_flash_silvermont}, 1801 {0x8086, 0x0f1d, B_FS, NT, "Intel", "Bay Trail", enable_flash_silvermont}, 1802 {0x8086, 0x0f1e, B_FS, NT, "Intel", "Bay Trail", enable_flash_silvermont}, 1803 {0x8086, 0x0f1f, B_FS, NT, "Intel", "Bay Trail", enable_flash_silvermont}, 1804 {0x8086, 0x122e, B_P, OK, "Intel", "PIIX", enable_flash_piix4}, 1805 {0x8086, 0x1234, B_P, NT, "Intel", "MPIIX", enable_flash_piix4}, 1806 {0x8086, 0x1c44, B_FS, DEP, "Intel", "Z68", enable_flash_pch6}, 1807 {0x8086, 0x1c46, B_FS, DEP, "Intel", "P67", enable_flash_pch6}, 1808 {0x8086, 0x1c47, B_FS, NT, "Intel", "UM67", enable_flash_pch6}, 1809 {0x8086, 0x1c49, B_FS, DEP, "Intel", "HM65", enable_flash_pch6}, 1810 {0x8086, 0x1c4a, B_FS, DEP, "Intel", "H67", enable_flash_pch6}, 1811 {0x8086, 0x1c4b, B_FS, NT, "Intel", "HM67", enable_flash_pch6}, 1812 {0x8086, 0x1c4c, B_FS, NT, "Intel", "Q65", enable_flash_pch6}, 1813 {0x8086, 0x1c4d, B_FS, NT, "Intel", "QS67", enable_flash_pch6}, 1814 {0x8086, 0x1c4e, B_FS, NT, "Intel", "Q67", enable_flash_pch6}, 1815 {0x8086, 0x1c4f, B_FS, DEP, "Intel", "QM67", enable_flash_pch6}, 1816 {0x8086, 0x1c50, B_FS, NT, "Intel", "B65", enable_flash_pch6}, 1817 {0x8086, 0x1c52, B_FS, NT, "Intel", "C202", enable_flash_pch6}, 1818 {0x8086, 0x1c54, B_FS, DEP, "Intel", "C204", enable_flash_pch6}, 1819 {0x8086, 0x1c56, B_FS, NT, "Intel", "C206", enable_flash_pch6}, 1820 {0x8086, 0x1c5c, B_FS, DEP, "Intel", "H61", enable_flash_pch6}, 1821 {0x8086, 0x1d40, B_FS, DEP, "Intel", "C60x/X79", enable_flash_pch6}, 1822 {0x8086, 0x1d41, B_FS, DEP, "Intel", "C60x/X79", enable_flash_pch6}, 1823 {0x8086, 0x1e44, B_FS, DEP, "Intel", "Z77", enable_flash_pch7}, 1824 {0x8086, 0x1e46, B_FS, NT, "Intel", "Z75", enable_flash_pch7}, 1825 {0x8086, 0x1e47, B_FS, NT, "Intel", "Q77", enable_flash_pch7}, 1826 {0x8086, 0x1e48, B_FS, DEP, "Intel", "Q75", enable_flash_pch7}, 1827 {0x8086, 0x1e49, B_FS, DEP, "Intel", "B75", enable_flash_pch7}, 1828 {0x8086, 0x1e4a, B_FS, DEP, "Intel", "H77", enable_flash_pch7}, 1829 {0x8086, 0x1e53, B_FS, NT, "Intel", "C216", enable_flash_pch7}, 1830 {0x8086, 0x1e55, B_FS, DEP, "Intel", "QM77", enable_flash_pch7}, 1831 {0x8086, 0x1e56, B_FS, DEP, "Intel", "QS77", enable_flash_pch7}, 1832 {0x8086, 0x1e57, B_FS, DEP, "Intel", "HM77", enable_flash_pch7}, 1833 {0x8086, 0x1e58, B_FS, NT, "Intel", "UM77", enable_flash_pch7}, 1834 {0x8086, 0x1e59, B_FS, DEP, "Intel", "HM76", enable_flash_pch7}, 1835 {0x8086, 0x1e5d, B_FS, NT, "Intel", "HM75", enable_flash_pch7}, 1836 {0x8086, 0x1e5e, B_FS, NT, "Intel", "HM70", enable_flash_pch7}, 1837 {0x8086, 0x1e5f, B_FS, DEP, "Intel", "NM70", enable_flash_pch7}, 1838 {0x8086, 0x1f38, B_FS, DEP, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, 1839 {0x8086, 0x1f39, B_FS, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, 1840 {0x8086, 0x1f3a, B_FS, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, 1841 {0x8086, 0x1f3b, B_FS, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, 1842 {0x8086, 0x229c, B_FS, OK, "Intel", "Braswell", enable_flash_silvermont}, 1843 {0x8086, 0x2310, B_FS, NT, "Intel", "DH89xxCC (Cave Creek)", enable_flash_pch7}, 1844 {0x8086, 0x2390, B_FS, NT, "Intel", "Coleto Creek", enable_flash_pch7}, 1845 {0x8086, 0x2410, B_FL, OK, "Intel", "ICH", enable_flash_ich0}, 1846 {0x8086, 0x2420, B_FL, OK, "Intel", "ICH0", enable_flash_ich0}, 1847 {0x8086, 0x2440, B_FL, OK, "Intel", "ICH2", enable_flash_ich2345}, 1848 {0x8086, 0x244c, B_FL, OK, "Intel", "ICH2-M", enable_flash_ich2345}, 1849 {0x8086, 0x2450, B_FL, NT, "Intel", "C-ICH", enable_flash_ich2345}, 1850 {0x8086, 0x2480, B_FL, OK, "Intel", "ICH3-S", enable_flash_ich2345}, 1851 {0x8086, 0x248c, B_FL, OK, "Intel", "ICH3-M", enable_flash_ich2345}, 1852 {0x8086, 0x24c0, B_FL, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich2345}, 1853 {0x8086, 0x24cc, B_FL, OK, "Intel", "ICH4-M", enable_flash_ich2345}, 1854 {0x8086, 0x24d0, B_FL, OK, "Intel", "ICH5/ICH5R", enable_flash_ich2345}, 1855 {0x8086, 0x25a1, B_FL, OK, "Intel", "6300ESB", enable_flash_ich2345}, 1856 {0x8086, 0x2640, B_FL, OK, "Intel", "ICH6/ICH6R", enable_flash_ich6}, 1857 {0x8086, 0x2641, B_FL, OK, "Intel", "ICH6-M", enable_flash_ich6}, 1858 {0x8086, 0x2642, B_FL, NT, "Intel", "ICH6W/ICH6RW", enable_flash_ich6}, 1859 {0x8086, 0x2670, B_FL, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich6}, 1860 {0x8086, 0x27b0, B_FS, OK, "Intel", "ICH7DH", enable_flash_ich7}, 1861 {0x8086, 0x27b8, B_FS, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7}, 1862 {0x8086, 0x27b9, B_FS, OK, "Intel", "ICH7M", enable_flash_ich7}, 1863 {0x8086, 0x27bc, B_FS, OK, "Intel", "NM10", enable_flash_ich7}, 1864 {0x8086, 0x27bd, B_FS, OK, "Intel", "ICH7MDH", enable_flash_ich7}, 1865 {0x8086, 0x2810, B_FS, DEP, "Intel", "ICH8/ICH8R", enable_flash_ich8}, 1866 {0x8086, 0x2811, B_FS, DEP, "Intel", "ICH8M-E", enable_flash_ich8}, 1867 {0x8086, 0x2812, B_FS, DEP, "Intel", "ICH8DH", enable_flash_ich8}, 1868 {0x8086, 0x2814, B_FS, DEP, "Intel", "ICH8DO", enable_flash_ich8}, 1869 {0x8086, 0x2815, B_FS, DEP, "Intel", "ICH8M", enable_flash_ich8}, 1870 {0x8086, 0x2910, B_FS, DEP, "Intel", "ICH9 Eng. Sample", enable_flash_ich9}, 1871 {0x8086, 0x2912, B_FS, DEP, "Intel", "ICH9DH", enable_flash_ich9}, 1872 {0x8086, 0x2914, B_FS, DEP, "Intel", "ICH9DO", enable_flash_ich9}, 1873 {0x8086, 0x2916, B_FS, DEP, "Intel", "ICH9R", enable_flash_ich9}, 1874 {0x8086, 0x2917, B_FS, DEP, "Intel", "ICH9M-E", enable_flash_ich9}, 1875 {0x8086, 0x2918, B_FS, DEP, "Intel", "ICH9", enable_flash_ich9}, 1876 {0x8086, 0x2919, B_FS, DEP, "Intel", "ICH9M", enable_flash_ich9}, 1877 {0x8086, 0x3a10, B_FS, NT, "Intel", "ICH10R Eng. Sample", enable_flash_ich10}, 1878 {0x8086, 0x3a14, B_FS, DEP, "Intel", "ICH10DO", enable_flash_ich10}, 1879 {0x8086, 0x3a16, B_FS, DEP, "Intel", "ICH10R", enable_flash_ich10}, 1880 {0x8086, 0x3a18, B_FS, DEP, "Intel", "ICH10", enable_flash_ich10}, 1881 {0x8086, 0x3a1a, B_FS, DEP, "Intel", "ICH10D", enable_flash_ich10}, 1882 {0x8086, 0x3a1e, B_FS, NT, "Intel", "ICH10 Eng. Sample", enable_flash_ich10}, 1883 {0x8086, 0x3b00, B_FS, NT, "Intel", "3400 Desktop", enable_flash_pch5}, 1884 {0x8086, 0x3b01, B_FS, NT, "Intel", "3400 Mobile", enable_flash_pch5}, 1885 {0x8086, 0x3b02, B_FS, NT, "Intel", "P55", enable_flash_pch5}, 1886 {0x8086, 0x3b03, B_FS, DEP, "Intel", "PM55", enable_flash_pch5}, 1887 {0x8086, 0x3b06, B_FS, DEP, "Intel", "H55", enable_flash_pch5}, 1888 {0x8086, 0x3b07, B_FS, DEP, "Intel", "QM57", enable_flash_pch5}, 1889 {0x8086, 0x3b08, B_FS, NT, "Intel", "H57", enable_flash_pch5}, 1890 {0x8086, 0x3b09, B_FS, DEP, "Intel", "HM55", enable_flash_pch5}, 1891 {0x8086, 0x3b0a, B_FS, NT, "Intel", "Q57", enable_flash_pch5}, 1892 {0x8086, 0x3b0b, B_FS, NT, "Intel", "HM57", enable_flash_pch5}, 1893 {0x8086, 0x3b0d, B_FS, NT, "Intel", "3400 Mobile SFF", enable_flash_pch5}, 1894 {0x8086, 0x3b0e, B_FS, NT, "Intel", "B55", enable_flash_pch5}, 1895 {0x8086, 0x3b0f, B_FS, DEP, "Intel", "QS57", enable_flash_pch5}, 1896 {0x8086, 0x3b12, B_FS, NT, "Intel", "3400", enable_flash_pch5}, 1897 {0x8086, 0x3b14, B_FS, DEP, "Intel", "3420", enable_flash_pch5}, 1898 {0x8086, 0x3b16, B_FS, NT, "Intel", "3450", enable_flash_pch5}, 1899 {0x8086, 0x3b1e, B_FS, NT, "Intel", "B55", enable_flash_pch5}, 1900 {0x8086, 0x5031, B_FS, OK, "Intel", "EP80579", enable_flash_ich7}, 1901 {0x8086, 0x7000, B_P, OK, "Intel", "PIIX3", enable_flash_piix4}, 1902 {0x8086, 0x7110, B_P, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4}, 1903 {0x8086, 0x7198, B_P, OK, "Intel", "440MX", enable_flash_piix4}, 1904 {0x8086, 0x8119, B_FL, OK, "Intel", "SCH Poulsbo", enable_flash_poulsbo}, 1905 {0x8086, 0x8186, B_FS, OK, "Intel", "Atom E6xx(T) (Tunnel Creek)", enable_flash_tunnelcreek}, 1906 {0x8086, 0x8c40, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8}, 1907 {0x8086, 0x8c41, B_FS, NT, "Intel", "Lynx Point Mobile Eng. Sample", enable_flash_pch8}, 1908 {0x8086, 0x8c42, B_FS, NT, "Intel", "Lynx Point Desktop Eng. Sample",enable_flash_pch8}, 1909 {0x8086, 0x8c43, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8}, 1910 {0x8086, 0x8c44, B_FS, DEP, "Intel", "Z87", enable_flash_pch8}, 1911 {0x8086, 0x8c45, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8}, 1912 {0x8086, 0x8c46, B_FS, NT, "Intel", "Z85", enable_flash_pch8}, 1913 {0x8086, 0x8c47, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8}, 1914 {0x8086, 0x8c48, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8}, 1915 {0x8086, 0x8c49, B_FS, NT, "Intel", "HM86", enable_flash_pch8}, 1916 {0x8086, 0x8c4a, B_FS, DEP, "Intel", "H87", enable_flash_pch8}, 1917 {0x8086, 0x8c4b, B_FS, DEP, "Intel", "HM87", enable_flash_pch8}, 1918 {0x8086, 0x8c4c, B_FS, NT, "Intel", "Q85", enable_flash_pch8}, 1919 {0x8086, 0x8c4d, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8}, 1920 {0x8086, 0x8c4e, B_FS, NT, "Intel", "Q87", enable_flash_pch8}, 1921 {0x8086, 0x8c4f, B_FS, NT, "Intel", "QM87", enable_flash_pch8}, 1922 {0x8086, 0x8c50, B_FS, DEP, "Intel", "B85", enable_flash_pch8}, 1923 {0x8086, 0x8c51, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8}, 1924 {0x8086, 0x8c52, B_FS, NT, "Intel", "C222", enable_flash_pch8}, 1925 {0x8086, 0x8c53, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8}, 1926 {0x8086, 0x8c54, B_FS, DEP, "Intel", "C224", enable_flash_pch8}, 1927 {0x8086, 0x8c55, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8}, 1928 {0x8086, 0x8c56, B_FS, NT, "Intel", "C226", enable_flash_pch8}, 1929 {0x8086, 0x8c57, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8}, 1930 {0x8086, 0x8c58, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8}, 1931 {0x8086, 0x8c59, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8}, 1932 {0x8086, 0x8c5a, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8}, 1933 {0x8086, 0x8c5b, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8}, 1934 {0x8086, 0x8c5c, B_FS, DEP, "Intel", "H81", enable_flash_pch8}, 1935 {0x8086, 0x8c5d, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8}, 1936 {0x8086, 0x8c5e, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8}, 1937 {0x8086, 0x8c5f, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8}, 1938 {0x8086, 0x8cc1, B_FS, NT, "Intel", "9 Series", enable_flash_pch9}, 1939 {0x8086, 0x8cc2, B_FS, NT, "Intel", "9 Series Engineering Sample", enable_flash_pch9}, 1940 {0x8086, 0x8cc3, B_FS, NT, "Intel", "9 Series", enable_flash_pch9}, 1941 {0x8086, 0x8cc4, B_FS, NT, "Intel", "Z97", enable_flash_pch9}, 1942 {0x8086, 0x8cc6, B_FS, NT, "Intel", "H97", enable_flash_pch9}, 1943 {0x8086, 0x8d40, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1944 {0x8086, 0x8d41, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1945 {0x8086, 0x8d42, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1946 {0x8086, 0x8d43, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1947 {0x8086, 0x8d44, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1948 {0x8086, 0x8d45, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1949 {0x8086, 0x8d46, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1950 {0x8086, 0x8d47, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1951 {0x8086, 0x8d48, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1952 {0x8086, 0x8d49, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1953 {0x8086, 0x8d4a, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1954 {0x8086, 0x8d4b, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1955 {0x8086, 0x8d4c, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1956 {0x8086, 0x8d4d, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1957 {0x8086, 0x8d4e, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1958 {0x8086, 0x8d4f, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1959 {0x8086, 0x8d50, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1960 {0x8086, 0x8d51, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1961 {0x8086, 0x8d52, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1962 {0x8086, 0x8d53, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1963 {0x8086, 0x8d54, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1964 {0x8086, 0x8d55, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1965 {0x8086, 0x8d56, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1966 {0x8086, 0x8d57, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1967 {0x8086, 0x8d58, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1968 {0x8086, 0x8d59, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1969 {0x8086, 0x8d5a, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1970 {0x8086, 0x8d5b, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1971 {0x8086, 0x8d5c, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1972 {0x8086, 0x8d5d, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1973 {0x8086, 0x8d5e, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1974 {0x8086, 0x8d5f, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, 1975 {0x8086, 0x9c41, B_FS, NT, "Intel", "Lynx Point LP Eng. Sample", enable_flash_pch8_lp}, 1976 {0x8086, 0x9c43, B_FS, NT, "Intel", "Lynx Point LP Premium", enable_flash_pch8_lp}, 1977 {0x8086, 0x9c45, B_FS, NT, "Intel", "Lynx Point LP Mainstream", enable_flash_pch8_lp}, 1978 {0x8086, 0x9c47, B_FS, NT, "Intel", "Lynx Point LP Value", enable_flash_pch8_lp}, 1979 {0x8086, 0x9cc1, B_FS, NT, "Intel", "Haswell U Sample", enable_flash_pch9_lp}, 1980 {0x8086, 0x9cc2, B_FS, NT, "Intel", "Broadwell U Sample", enable_flash_pch9_lp}, 1981 {0x8086, 0x9cc3, B_FS, DEP, "Intel", "Broadwell U Premium", enable_flash_pch9_lp}, 1982 {0x8086, 0x9cc5, B_FS, NT, "Intel", "Broadwell U Base", enable_flash_pch9_lp}, 1983 {0x8086, 0x9cc6, B_FS, NT, "Intel", "Broadwell Y Sample", enable_flash_pch9_lp}, 1984 {0x8086, 0x9cc7, B_FS, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9_lp}, 1985 {0x8086, 0x9cc9, B_FS, NT, "Intel", "Broadwell Y Base", enable_flash_pch9_lp}, 1986 {0x8086, 0x9ccb, B_FS, NT, "Intel", "Broadwell H", enable_flash_pch9}, 1987 {0x8086, 0x9d41, B_S, NT, "Intel", "Skylake / Kaby Lake Sample", enable_flash_pch100}, 1988 {0x8086, 0x9d43, B_S, NT, "Intel", "Skylake U Base", enable_flash_pch100}, 1989 {0x8086, 0x9d46, B_S, NT, "Intel", "Skylake Y Premium", enable_flash_pch100}, 1990 {0x8086, 0x9d48, B_S, NT, "Intel", "Skylake U Premium", enable_flash_pch100}, 1991 {0x8086, 0x9d4b, B_S, NT, "Intel", "Kaby Lake Y w/ iHDCP2.2 Prem.", enable_flash_pch100}, 1992 {0x8086, 0x9d4e, B_S, DEP, "Intel", "Kaby Lake U w/ iHDCP2.2 Prem.", enable_flash_pch100}, 1993 {0x8086, 0x9d50, B_S, NT, "Intel", "Kaby Lake U w/ iHDCP2.2 Base", enable_flash_pch100}, 1994 {0x8086, 0x9d51, B_S, NT, "Intel", "Kabe Lake w/ iHDCP2.2 Sample", enable_flash_pch100}, 1995 {0x8086, 0x9d53, B_S, NT, "Intel", "Kaby Lake U Base", enable_flash_pch100}, 1996 {0x8086, 0x9d56, B_S, NT, "Intel", "Kaby Lake Y Premium", enable_flash_pch100}, 1997 {0x8086, 0x9d58, B_S, NT, "Intel", "Kaby Lake U Premium", enable_flash_pch100}, 1998 {0x8086, 0x9d84, B_S, DEP, "Intel", "Cannon Lake U Premium", enable_flash_pch300}, 1999 {0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100}, 2000 {0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100}, 2001 {0x8086, 0xa143, B_S, NT, "Intel", "H110", enable_flash_pch100}, 2002 {0x8086, 0xa144, B_S, NT, "Intel", "H170", enable_flash_pch100}, 2003 {0x8086, 0xa145, B_S, NT, "Intel", "Z170", enable_flash_pch100}, 2004 {0x8086, 0xa146, B_S, NT, "Intel", "Q170", enable_flash_pch100}, 2005 {0x8086, 0xa147, B_S, NT, "Intel", "Q150", enable_flash_pch100}, 2006 {0x8086, 0xa148, B_S, NT, "Intel", "B150", enable_flash_pch100}, 2007 {0x8086, 0xa149, B_S, NT, "Intel", "C236", enable_flash_pch100}, 2008 {0x8086, 0xa14a, B_S, NT, "Intel", "C232", enable_flash_pch100}, 2009 {0x8086, 0xa14b, B_S, NT, "Intel", "Sunrise Point Server Sample", enable_flash_pch100}, 2010 {0x8086, 0xa14d, B_S, NT, "Intel", "QM170", enable_flash_pch100}, 2011 {0x8086, 0xa14e, B_S, NT, "Intel", "HM170", enable_flash_pch100}, 2012 {0x8086, 0xa150, B_S, DEP, "Intel", "CM236", enable_flash_pch100}, 2013 {0x8086, 0xa151, B_S, NT, "Intel", "QMS180", enable_flash_pch100}, 2014 {0x8086, 0xa152, B_S, NT, "Intel", "HM175", enable_flash_pch100}, 2015 {0x8086, 0xa153, B_S, NT, "Intel", "QM175", enable_flash_pch100}, 2016 {0x8086, 0xa154, B_S, NT, "Intel", "CM238", enable_flash_pch100}, 2017 {0x8086, 0xa155, B_S, NT, "Intel", "QMU185", enable_flash_pch100}, 2018 {0x8086, 0xa1c1, B_S, NT, "Intel", "C621 Series Chipset (QS/PRQ)", enable_flash_c620}, 2019 {0x8086, 0xa1c2, B_S, NT, "Intel", "C622 Series Chipset (QS/PRQ)", enable_flash_c620}, 2020 {0x8086, 0xa1c3, B_S, NT, "Intel", "C624 Series Chipset (QS/PRQ)", enable_flash_c620}, 2021 {0x8086, 0xa1c4, B_S, NT, "Intel", "C625 Series Chipset (QS/PRQ)", enable_flash_c620}, 2022 {0x8086, 0xa1c5, B_S, NT, "Intel", "C626 Series Chipset (QS/PRQ)", enable_flash_c620}, 2023 {0x8086, 0xa1c6, B_S, NT, "Intel", "C627 Series Chipset (QS/PRQ)", enable_flash_c620}, 2024 {0x8086, 0xa1c7, B_S, NT, "Intel", "C628 Series Chipset (QS/PRQ)", enable_flash_c620}, 2025 {0x8086, 0xa242, B_S, NT, "Intel", "C624 Series Chipset Supersku", enable_flash_c620}, 2026 {0x8086, 0xa243, B_S, NT, "Intel", "C627 Series Chipset Supersku", enable_flash_c620}, 2027 {0x8086, 0xa244, B_S, NT, "Intel", "C621 Series Chipset Supersku", enable_flash_c620}, 2028 {0x8086, 0xa245, B_S, NT, "Intel", "C627 Series Chipset Supersku", enable_flash_c620}, 2029 {0x8086, 0xa246, B_S, NT, "Intel", "C628 Series Chipset Supersku", enable_flash_c620}, 2030 {0x8086, 0xa247, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620}, 2031 {0x8086, 0xa2c4, B_S, NT, "Intel", "H270", enable_flash_pch100}, 2032 {0x8086, 0xa2c5, B_S, NT, "Intel", "Z270", enable_flash_pch100}, 2033 {0x8086, 0xa2c6, B_S, NT, "Intel", "Q270", enable_flash_pch100}, 2034 {0x8086, 0xa2c7, B_S, NT, "Intel", "Q250", enable_flash_pch100}, 2035 {0x8086, 0xa2c8, B_S, NT, "Intel", "B250", enable_flash_pch100}, 2036 {0x8086, 0xa2c9, B_S, NT, "Intel", "Z370", enable_flash_pch100}, 2037 {0x8086, 0xa2d2, B_S, NT, "Intel", "X299", enable_flash_pch100}, 2038 {0x8086, 0x5ae8, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl}, 2039 {0x8086, 0xa303, B_S, NT, "Intel", "H310", enable_flash_pch300}, 2040 {0x8086, 0xa304, B_S, NT, "Intel", "H370", enable_flash_pch300}, 2041 {0x8086, 0xa305, B_S, NT, "Intel", "Z390", enable_flash_pch300}, 2042 {0x8086, 0xa306, B_S, NT, "Intel", "Q370", enable_flash_pch300}, 2043 {0x8086, 0xa308, B_S, NT, "Intel", "B360", enable_flash_pch300}, 2044 {0x8086, 0xa309, B_S, NT, "Intel", "C246", enable_flash_pch300}, 2045 {0x8086, 0xa30a, B_S, NT, "Intel", "C242", enable_flash_pch300}, 2046 {0x8086, 0xa30c, B_S, NT, "Intel", "QM370", enable_flash_pch300}, 2047 {0x8086, 0xa30d, B_S, NT, "Intel", "HM370", enable_flash_pch300}, 2048 {0x8086, 0xa30e, B_S, DEP, "Intel", "CM246", enable_flash_pch300}, 2049 {0x8086, 0x3482, B_S, DEP, "Intel", "Ice Lake U Premium", enable_flash_pch300}, 2050 #endif 2051 {0}, 2052 }; 2053 2054 int chipset_flash_enable(void) 2055 { 2056 struct pci_dev *dev = NULL; 2057 int ret = -2; /* Nothing! */ 2058 int i; 2059 2060 /* Now let's try to find the chipset we have... */ 2061 for (i = 0; chipset_enables[i].vendor_name != NULL; i++) { 2062 dev = pci_dev_find(chipset_enables[i].vendor_id, 2063 chipset_enables[i].device_id); 2064 if (!dev) 2065 continue; 2066 if (ret != -2) { 2067 msg_pwarn("Warning: unexpected second chipset match: " 2068 "\"%s %s\"\n" 2069 "ignoring, please report lspci and board URL " 2070 "to flashrom@flashrom.org\n" 2071 "with \'CHIPSET: your board name\' in the " 2072 "subject line.\n", 2073 chipset_enables[i].vendor_name, 2074 chipset_enables[i].device_name); 2075 continue; 2076 } 2077 msg_pinfo("Found chipset \"%s %s\"", 2078 chipset_enables[i].vendor_name, 2079 chipset_enables[i].device_name); 2080 msg_pdbg(" with PCI ID %04x:%04x", 2081 chipset_enables[i].vendor_id, 2082 chipset_enables[i].device_id); 2083 msg_pinfo(".\n"); 2084 2085 if (chipset_enables[i].status == BAD) { 2086 msg_perr("ERROR: This chipset is not supported yet.\n"); 2087 return ERROR_FATAL; 2088 } 2089 if (chipset_enables[i].status == NT) { 2090 msg_pinfo("This chipset is marked as untested. If " 2091 "you are using an up-to-date version\nof " 2092 "flashrom *and* were (not) able to " 2093 "successfully update your firmware with it,\n" 2094 "then please email a report to " 2095 "flashrom@flashrom.org including a verbose " 2096 "(-V) log.\nThank you!\n"); 2097 } 2098 if (!(chipset_enables[i].buses & (internal_buses_supported | BUS_SPI))) { 2099 msg_pdbg("Skipping chipset enable: No supported buses enabled.\n"); 2100 continue; 2101 } 2102 msg_pinfo("Enabling flash write... "); 2103 ret = chipset_enables[i].doit(dev, chipset_enables[i].device_name); 2104 if (ret == NOT_DONE_YET) { 2105 ret = -2; 2106 msg_pinfo("OK - searching further chips.\n"); 2107 } else if (ret < 0) 2108 msg_pinfo("FAILED!\n"); 2109 else if (ret == 0) 2110 msg_pinfo("OK.\n"); 2111 else if (ret == ERROR_NONFATAL) 2112 msg_pinfo("PROBLEMS, continuing anyway\n"); 2113 if (ret == ERROR_FATAL) { 2114 msg_perr("FATAL ERROR!\n"); 2115 return ret; 2116 } 2117 } 2118 2119 return ret; 2120 } 2121