1 /*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #if defined(__i386__) || defined(__x86_64__)
18
19 #include <stdlib.h>
20 #include "flash.h"
21 #include "programmer.h"
22 #include "hwaccess.h"
23
24 #define BIOS_ROM_ADDR 0x04
25 #define BIOS_ROM_DATA 0x08
26 #define INT_STATUS 0x0e
27 #define INTERNAL_CONFIG 0x00
28 #define SELECT_REG_WINDOW 0x800
29
30 #define PCI_VENDOR_ID_3COM 0x10b7
31
32 static uint32_t io_base_addr = 0;
33 static uint32_t internal_conf;
34 static uint16_t id;
35
36 const struct dev_entry nics_3com[] = {
37 /* 3C90xB */
38 {0x10b7, 0x9055, OK, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX"},
39 {0x10b7, 0x9001, NT, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4" },
40 {0x10b7, 0x9004, OK, "3COM", "3C90xB: PCI 10BASE-T (TPO)" },
41 {0x10b7, 0x9005, NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2/AUI (COMBO)" },
42 {0x10b7, 0x9006, NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2 (TPC)" },
43 {0x10b7, 0x900a, NT, "3COM", "3C90xB: PCI 10BASE-FL" },
44 {0x10b7, 0x905a, NT, "3COM", "3C90xB: PCI 10BASE-FX" },
45 {0x10b7, 0x9058, OK, "3COM", "3C905B: Cyclone 10/100/BNC" },
46
47 /* 3C905C */
48 {0x10b7, 0x9200, OK, "3COM", "3C905C: EtherLink 10/100 PCI (TX)" },
49
50 /* 3C980C */
51 {0x10b7, 0x9805, NT, "3COM", "3C980C: EtherLink Server 10/100 PCI (TX)" },
52
53 {0},
54 };
55
56 static void nic3com_chip_writeb(const struct flashctx *flash, uint8_t val,
57 chipaddr addr);
58 static uint8_t nic3com_chip_readb(const struct flashctx *flash,
59 const chipaddr addr);
60 static const struct par_master par_master_nic3com = {
61 .chip_readb = nic3com_chip_readb,
62 .chip_readw = fallback_chip_readw,
63 .chip_readl = fallback_chip_readl,
64 .chip_readn = fallback_chip_readn,
65 .chip_writeb = nic3com_chip_writeb,
66 .chip_writew = fallback_chip_writew,
67 .chip_writel = fallback_chip_writel,
68 .chip_writen = fallback_chip_writen,
69 };
70
nic3com_shutdown(void * data)71 static int nic3com_shutdown(void *data)
72 {
73 /* 3COM 3C90xB cards need a special fixup. */
74 if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005
75 || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {
76 /* Select register window 3 and restore the receiver status. */
77 OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS);
78 OUTL(internal_conf, io_base_addr + INTERNAL_CONFIG);
79 }
80
81 return 0;
82 }
83
nic3com_init(void)84 int nic3com_init(void)
85 {
86 struct pci_dev *dev = NULL;
87
88 if (rget_io_perms())
89 return 1;
90
91 dev = pcidev_init(nics_3com, PCI_BASE_ADDRESS_0);
92 if (!dev)
93 return 1;
94
95 io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
96 if (!io_base_addr)
97 return 1;
98
99 id = dev->device_id;
100
101 /* 3COM 3C90xB cards need a special fixup. */
102 if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005
103 || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {
104 /* Select register window 3 and save the receiver status. */
105 OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS);
106 internal_conf = INL(io_base_addr + INTERNAL_CONFIG);
107
108 /* Set receiver type to MII for full BIOS ROM access. */
109 OUTL((internal_conf & 0xf00fffff) | 0x00600000, io_base_addr);
110 }
111
112 /*
113 * The lowest 16 bytes of the I/O mapped register space of (most) 3COM
114 * cards form a 'register window' into one of multiple (usually 8)
115 * register banks. For 3C90xB/3C90xC we need register window/bank 0.
116 */
117 OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS);
118
119 if (register_shutdown(nic3com_shutdown, NULL))
120 return 1;
121
122 max_rom_decode.parallel = 128 * 1024;
123 register_par_master(&par_master_nic3com, BUS_PARALLEL);
124
125 return 0;
126 }
127
nic3com_chip_writeb(const struct flashctx * flash,uint8_t val,chipaddr addr)128 static void nic3com_chip_writeb(const struct flashctx *flash, uint8_t val,
129 chipaddr addr)
130 {
131 OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
132 OUTB(val, io_base_addr + BIOS_ROM_DATA);
133 }
134
nic3com_chip_readb(const struct flashctx * flash,const chipaddr addr)135 static uint8_t nic3com_chip_readb(const struct flashctx *flash,
136 const chipaddr addr)
137 {
138 OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
139 return INB(io_base_addr + BIOS_ROM_DATA);
140 }
141
142 #else
143 #error PCI port I/O access is not supported on this architecture yet.
144 #endif
145