1 /* @(#)scsireg.h 1.35 12/03/16 Copyright 1987-2011 J. Schilling */ 2 /* 3 * usefull definitions for dealing with CCS SCSI - devices 4 * 5 * Copyright (c) 1987-2012 J. Schilling 6 */ 7 /* 8 * The contents of this file are subject to the terms of the 9 * Common Development and Distribution License, Version 1.0 only 10 * (the "License"). You may not use this file except in compliance 11 * with the License. 12 * 13 * See the file CDDL.Schily.txt in this distribution for details. 14 * A copy of the CDDL is also available via the Internet at 15 * http://www.opensource.org/licenses/cddl1.txt 16 * 17 * The following exceptions apply: 18 * CDDL �3.6 needs to be replaced by: "You may create a Larger Work by 19 * combining Covered Software with other code if all other code is governed by 20 * the terms of a license that is OSI approved (see www.opensource.org) and 21 * you may distribute the Larger Work as a single product. In such a case, 22 * You must make sure the requirements of this License are fulfilled for 23 * the Covered Software." 24 * 25 * When distributing Covered Code, include this CDDL HEADER in each 26 * file and include the License file CDDL.Schily.txt from this distribution. 27 */ 28 29 #ifndef _SCG_SCSIREG_H 30 #define _SCG_SCSIREG_H 31 32 #include <schily/utypes.h> 33 #include <schily/btorder.h> 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */ 40 41 struct scsi_inquiry { 42 Ucbit type : 5; /* 0 */ 43 Ucbit qualifier : 3; /* 0 */ 44 45 Ucbit type_modifier : 7; /* 1 */ 46 Ucbit removable : 1; /* 1 */ 47 48 Ucbit ansi_version : 3; /* 2 */ 49 Ucbit ecma_version : 3; /* 2 */ 50 Ucbit iso_version : 2; /* 2 */ 51 52 Ucbit data_format : 4; /* 3 */ 53 Ucbit res3_54 : 2; /* 3 */ 54 Ucbit termiop : 1; /* 3 */ 55 Ucbit aenc : 1; /* 3 */ 56 57 Ucbit add_len : 8; /* 4 */ 58 Ucbit sense_len : 8; /* 5 */ /* only Emulex ??? */ 59 Ucbit res2 : 8; /* 6 */ 60 61 Ucbit softreset : 1; /* 7 */ 62 Ucbit cmdque : 1; 63 Ucbit res7_2 : 1; 64 Ucbit linked : 1; 65 Ucbit sync : 1; 66 Ucbit wbus16 : 1; 67 Ucbit wbus32 : 1; 68 Ucbit reladr : 1; /* 7 */ 69 70 union { 71 72 struct { 73 char vendor_info[8]; /* 8 */ 74 char prod_ident[16]; /* 16 */ 75 char prod_revision[4]; /* 32 */ 76 #ifdef comment 77 char vendor_uniq[20]; /* 36 */ 78 char reserved[40]; /* 56 */ 79 #endif 80 } vi; 81 char vi_space[8+16+4]; 82 } vu; 83 }; /* 96 */ 84 85 #else /* Motorola byteorder */ 86 87 struct scsi_inquiry { 88 Ucbit qualifier : 3; /* 0 */ 89 Ucbit type : 5; /* 0 */ 90 91 Ucbit removable : 1; /* 1 */ 92 Ucbit type_modifier : 7; /* 1 */ 93 94 Ucbit iso_version : 2; /* 2 */ 95 Ucbit ecma_version : 3; 96 Ucbit ansi_version : 3; /* 2 */ 97 98 Ucbit aenc : 1; /* 3 */ 99 Ucbit termiop : 1; 100 Ucbit res3_54 : 2; 101 Ucbit data_format : 4; /* 3 */ 102 103 Ucbit add_len : 8; /* 4 */ 104 Ucbit sense_len : 8; /* 5 */ /* only Emulex ??? */ 105 Ucbit res2 : 8; /* 6 */ 106 Ucbit reladr : 1; /* 7 */ 107 Ucbit wbus32 : 1; 108 Ucbit wbus16 : 1; 109 Ucbit sync : 1; 110 Ucbit linked : 1; 111 Ucbit res7_2 : 1; 112 Ucbit cmdque : 1; 113 Ucbit softreset : 1; 114 115 union { 116 117 struct { 118 char vendor_info[8]; /* 8 */ 119 char prod_ident[16]; /* 16 */ 120 char prod_revision[4]; /* 32 */ 121 #ifdef comment 122 char vendor_uniq[20]; /* 36 */ 123 char reserved[40]; /* 56 */ 124 #endif 125 } vi; 126 char vi_space[8+16+4]; 127 } vu; 128 }; /* 96 */ 129 #endif 130 131 #ifdef __SCG_COMPAT__ 132 #define info inq_vendor_info 133 #define ident inq_prod_ident 134 #define revision inq_prod_revision 135 #endif 136 137 #define inq_vendor_info vu.vi.vendor_info 138 #define inq_prod_ident vu.vi.prod_ident 139 #define inq_prod_revision vu.vi.prod_revision 140 141 #define inq_info_space vu.vi_space 142 143 /* Peripheral Device Qualifier */ 144 145 #define INQ_DEV_PRESENT 0x00 /* Physical device present */ 146 #define INQ_DEV_NOTPR 0x01 /* Physical device not present */ 147 #define INQ_DEV_RES 0x02 /* Reserved */ 148 #define INQ_DEV_NOTSUP 0x03 /* Logical unit not supported */ 149 150 /* Peripheral Device Type */ 151 152 #define INQ_DASD 0x00 /* Direct-access device (disk) */ 153 #define INQ_SEQD 0x01 /* Sequential-access device (tape) */ 154 #define INQ_PRTD 0x02 /* Printer device */ 155 #define INQ_PROCD 0x03 /* Processor device */ 156 #define INQ_OPTD 0x04 /* Write once device (optical disk) */ 157 #define INQ_WORM 0x04 /* Write once device (optical disk) */ 158 #define INQ_ROMD 0x05 /* CD-ROM device */ 159 #define INQ_SCAN 0x06 /* Scanner device */ 160 #define INQ_OMEM 0x07 /* Optical Memory device */ 161 #define INQ_JUKE 0x08 /* Medium Changer device (jukebox) */ 162 #define INQ_COMM 0x09 /* Communications device */ 163 #define INQ_IT8_1 0x0A /* IT8 */ 164 #define INQ_IT8_2 0x0B /* IT8 */ 165 #define INQ_STARR 0x0C /* Storage array device */ 166 #define INQ_ENCL 0x0D /* Enclosure services device */ 167 #define INQ_SDAD 0x0E /* Simplyfied direct-access device */ 168 #define INQ_OCRW 0x0F /* Optical card reader/writer device */ 169 #define INQ_BRIDGE 0x10 /* Bridging expander device */ 170 #define INQ_OSD 0x11 /* Object based storage device */ 171 #define INQ_ADC 0x12 /* Automation/Drive interface */ 172 #define INQ_WELLKNOWN 0x1E /* Well known logical unit */ 173 #define INQ_NODEV 0x1F /* Unknown or no device */ 174 #define INQ_NOTPR 0x1F /* Logical unit not present (SCSI-1) */ 175 176 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */ 177 178 struct scsi_mode_header { 179 Ucbit sense_data_len : 8; 180 Uchar medium_type; 181 Ucbit res2 : 4; 182 Ucbit cache : 1; 183 Ucbit res : 2; 184 Ucbit write_prot : 1; 185 Uchar blockdesc_len; 186 }; 187 188 #else /* Motorola byteorder */ 189 190 struct scsi_mode_header { 191 Ucbit sense_data_len : 8; 192 Uchar medium_type; 193 Ucbit write_prot : 1; 194 Ucbit res : 2; 195 Ucbit cache : 1; 196 Ucbit res2 : 4; 197 Uchar blockdesc_len; 198 }; 199 #endif 200 201 struct scsi_modesel_header { 202 Ucbit sense_data_len : 8; 203 Uchar medium_type; 204 Ucbit res2 : 8; 205 Uchar blockdesc_len; 206 }; 207 208 struct scsi_mode_blockdesc { 209 Uchar density; 210 Uchar nlblock[3]; 211 Ucbit res : 8; 212 Uchar lblen[3]; 213 }; 214 215 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */ 216 217 struct acb_mode_data { 218 Uchar listformat; 219 Uchar ncyl[2]; 220 Uchar nhead; 221 Uchar start_red_wcurrent[2]; 222 Uchar start_precomp[2]; 223 Uchar landing_zone; 224 Uchar step_rate; 225 Ucbit : 2; 226 Ucbit hard_sec : 1; 227 Ucbit fixed_media : 1; 228 Ucbit : 4; 229 Uchar sect_per_trk; 230 }; 231 232 #else /* Motorola byteorder */ 233 234 struct acb_mode_data { 235 Uchar listformat; 236 Uchar ncyl[2]; 237 Uchar nhead; 238 Uchar start_red_wcurrent[2]; 239 Uchar start_precomp[2]; 240 Uchar landing_zone; 241 Uchar step_rate; 242 Ucbit : 4; 243 Ucbit fixed_media : 1; 244 Ucbit hard_sec : 1; 245 Ucbit : 2; 246 Uchar sect_per_trk; 247 }; 248 #endif 249 250 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */ 251 252 struct scsi_mode_page_header { 253 Ucbit p_code : 6; 254 Ucbit res : 1; 255 Ucbit parsave : 1; 256 Uchar p_len; 257 }; 258 259 /* 260 * This is a hack that allows mode pages without 261 * any further bitfileds to be defined bitorder independent. 262 */ 263 #define MP_P_CODE \ 264 Ucbit p_code : 6; \ 265 Ucbit p_res : 1; \ 266 Ucbit parsave : 1 267 268 #else /* Motorola byteorder */ 269 270 struct scsi_mode_page_header { 271 Ucbit parsave : 1; 272 Ucbit res : 1; 273 Ucbit p_code : 6; 274 Uchar p_len; 275 }; 276 277 /* 278 * This is a hack that allows mode pages without 279 * any further bitfileds to be defined bitorder independent. 280 */ 281 #define MP_P_CODE \ 282 Ucbit parsave : 1; \ 283 Ucbit p_res : 1; \ 284 Ucbit p_code : 6 285 286 #endif 287 288 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */ 289 290 struct scsi_mode_page_01 { /* Error recovery Parameters */ 291 MP_P_CODE; /* parsave & pagecode */ 292 Uchar p_len; /* 0x0A = 12 Bytes */ 293 Ucbit disa_correction : 1; /* Byte 2 */ 294 Ucbit term_on_rec_err : 1; 295 Ucbit report_rec_err : 1; 296 Ucbit en_early_corr : 1; 297 Ucbit read_continuous : 1; 298 Ucbit tranfer_block : 1; 299 Ucbit en_auto_reall_r : 1; 300 Ucbit en_auto_reall_w : 1; /* Byte 2 */ 301 Uchar rd_retry_count; /* Byte 3 */ 302 Uchar correction_span; 303 char head_offset_count; 304 char data_strobe_offset; 305 Uchar res; 306 Uchar wr_retry_count; 307 Uchar res_tape[2]; 308 Uchar recov_timelim[2]; 309 }; 310 311 #else /* Motorola byteorder */ 312 313 struct scsi_mode_page_01 { /* Error recovery Parameters */ 314 MP_P_CODE; /* parsave & pagecode */ 315 Uchar p_len; /* 0x0A = 12 Bytes */ 316 Ucbit en_auto_reall_w : 1; /* Byte 2 */ 317 Ucbit en_auto_reall_r : 1; 318 Ucbit tranfer_block : 1; 319 Ucbit read_continuous : 1; 320 Ucbit en_early_corr : 1; 321 Ucbit report_rec_err : 1; 322 Ucbit term_on_rec_err : 1; 323 Ucbit disa_correction : 1; /* Byte 2 */ 324 Uchar rd_retry_count; /* Byte 3 */ 325 Uchar correction_span; 326 char head_offset_count; 327 char data_strobe_offset; 328 Uchar res; 329 Uchar wr_retry_count; 330 Uchar res_tape[2]; 331 Uchar recov_timelim[2]; 332 }; 333 #endif 334 335 336 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */ 337 338 struct scsi_mode_page_02 { /* Device dis/re connect Parameters */ 339 MP_P_CODE; /* parsave & pagecode */ 340 Uchar p_len; /* 0x0E = 16 Bytes */ 341 Uchar buf_full_ratio; 342 Uchar buf_empt_ratio; 343 Uchar bus_inact_limit[2]; 344 Uchar disc_time_limit[2]; 345 Uchar conn_time_limit[2]; 346 Uchar max_burst_size[2]; /* Start SCSI-2 */ 347 Ucbit data_tr_dis_ctl : 2; 348 Ucbit : 6; 349 Uchar res[3]; 350 }; 351 352 #else /* Motorola byteorder */ 353 354 struct scsi_mode_page_02 { /* Device dis/re connect Parameters */ 355 MP_P_CODE; /* parsave & pagecode */ 356 Uchar p_len; /* 0x0E = 16 Bytes */ 357 Uchar buf_full_ratio; 358 Uchar buf_empt_ratio; 359 Uchar bus_inact_limit[2]; 360 Uchar disc_time_limit[2]; 361 Uchar conn_time_limit[2]; 362 Uchar max_burst_size[2]; /* Start SCSI-2 */ 363 Ucbit : 6; 364 Ucbit data_tr_dis_ctl : 2; 365 Uchar res[3]; 366 }; 367 #endif 368 369 #define DTDC_DATADONE 0x01 /* 370 * Target may not disconnect once 371 * data transfer is started until 372 * all data successfully transferred. 373 */ 374 375 #define DTDC_CMDDONE 0x03 /* 376 * Target may not disconnect once 377 * data transfer is started until 378 * command completed. 379 */ 380 381 382 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */ 383 384 struct scsi_mode_page_03 { /* Direct access format Paramters */ 385 MP_P_CODE; /* parsave & pagecode */ 386 Uchar p_len; /* 0x16 = 24 Bytes */ 387 Uchar trk_per_zone[2]; 388 Uchar alt_sec_per_zone[2]; 389 Uchar alt_trk_per_zone[2]; 390 Uchar alt_trk_per_vol[2]; 391 Uchar sect_per_trk[2]; 392 Uchar bytes_per_phys_sect[2]; 393 Uchar interleave[2]; 394 Uchar trk_skew[2]; 395 Uchar cyl_skew[2]; 396 Ucbit : 3; 397 Ucbit inhibit_save : 1; 398 Ucbit fmt_by_surface : 1; 399 Ucbit removable : 1; 400 Ucbit hard_sec : 1; 401 Ucbit soft_sec : 1; 402 Uchar res[3]; 403 }; 404 405 #else /* Motorola byteorder */ 406 407 struct scsi_mode_page_03 { /* Direct access format Paramters */ 408 MP_P_CODE; /* parsave & pagecode */ 409 Uchar p_len; /* 0x16 = 24 Bytes */ 410 Uchar trk_per_zone[2]; 411 Uchar alt_sec_per_zone[2]; 412 Uchar alt_trk_per_zone[2]; 413 Uchar alt_trk_per_vol[2]; 414 Uchar sect_per_trk[2]; 415 Uchar bytes_per_phys_sect[2]; 416 Uchar interleave[2]; 417 Uchar trk_skew[2]; 418 Uchar cyl_skew[2]; 419 Ucbit soft_sec : 1; 420 Ucbit hard_sec : 1; 421 Ucbit removable : 1; 422 Ucbit fmt_by_surface : 1; 423 Ucbit inhibit_save : 1; 424 Ucbit : 3; 425 Uchar res[3]; 426 }; 427 #endif 428 429 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */ 430 431 struct scsi_mode_page_04 { /* Rigid disk Geometry Parameters */ 432 MP_P_CODE; /* parsave & pagecode */ 433 Uchar p_len; /* 0x16 = 24 Bytes */ 434 Uchar ncyl[3]; 435 Uchar nhead; 436 Uchar start_precomp[3]; 437 Uchar start_red_wcurrent[3]; 438 Uchar step_rate[2]; 439 Uchar landing_zone[3]; 440 Ucbit rot_pos_locking : 2; /* Start SCSI-2 */ 441 Ucbit : 6; /* Start SCSI-2 */ 442 Uchar rotational_off; 443 Uchar res1; 444 Uchar rotation_rate[2]; 445 Uchar res2[2]; 446 }; 447 448 #else /* Motorola byteorder */ 449 450 struct scsi_mode_page_04 { /* Rigid disk Geometry Parameters */ 451 MP_P_CODE; /* parsave & pagecode */ 452 Uchar p_len; /* 0x16 = 24 Bytes */ 453 Uchar ncyl[3]; 454 Uchar nhead; 455 Uchar start_precomp[3]; 456 Uchar start_red_wcurrent[3]; 457 Uchar step_rate[2]; 458 Uchar landing_zone[3]; 459 Ucbit : 6; /* Start SCSI-2 */ 460 Ucbit rot_pos_locking : 2; /* Start SCSI-2 */ 461 Uchar rotational_off; 462 Uchar res1; 463 Uchar rotation_rate[2]; 464 Uchar res2[2]; 465 }; 466 #endif 467 468 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */ 469 470 struct scsi_mode_page_05 { /* Flexible disk Parameters */ 471 MP_P_CODE; /* parsave & pagecode */ 472 Uchar p_len; /* 0x1E = 32 Bytes */ 473 Uchar transfer_rate[2]; 474 Uchar nhead; 475 Uchar sect_per_trk; 476 Uchar bytes_per_phys_sect[2]; 477 Uchar ncyl[2]; 478 Uchar start_precomp[2]; 479 Uchar start_red_wcurrent[2]; 480 Uchar step_rate[2]; 481 Uchar step_pulse_width; 482 Uchar head_settle_delay[2]; 483 Uchar motor_on_delay; 484 Uchar motor_off_delay; 485 Ucbit spc : 4; 486 Ucbit : 4; 487 Ucbit : 5; 488 Ucbit mo : 1; 489 Ucbit ssn : 1; 490 Ucbit trdy : 1; 491 Uchar write_compensation; 492 Uchar head_load_delay; 493 Uchar head_unload_delay; 494 Ucbit pin_2_use : 4; 495 Ucbit pin_34_use : 4; 496 Ucbit pin_1_use : 4; 497 Ucbit pin_4_use : 4; 498 Uchar rotation_rate[2]; 499 Uchar res[2]; 500 }; 501 502 #else /* Motorola byteorder */ 503 504 struct scsi_mode_page_05 { /* Flexible disk Parameters */ 505 MP_P_CODE; /* parsave & pagecode */ 506 Uchar p_len; /* 0x1E = 32 Bytes */ 507 Uchar transfer_rate[2]; 508 Uchar nhead; 509 Uchar sect_per_trk; 510 Uchar bytes_per_phys_sect[2]; 511 Uchar ncyl[2]; 512 Uchar start_precomp[2]; 513 Uchar start_red_wcurrent[2]; 514 Uchar step_rate[2]; 515 Uchar step_pulse_width; 516 Uchar head_settle_delay[2]; 517 Uchar motor_on_delay; 518 Uchar motor_off_delay; 519 Ucbit trdy : 1; 520 Ucbit ssn : 1; 521 Ucbit mo : 1; 522 Ucbit : 5; 523 Ucbit : 4; 524 Ucbit spc : 4; 525 Uchar write_compensation; 526 Uchar head_load_delay; 527 Uchar head_unload_delay; 528 Ucbit pin_34_use : 4; 529 Ucbit pin_2_use : 4; 530 Ucbit pin_4_use : 4; 531 Ucbit pin_1_use : 4; 532 Uchar rotation_rate[2]; 533 Uchar res[2]; 534 }; 535 #endif 536 537 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */ 538 539 struct scsi_mode_page_07 { /* Verify Error recovery */ 540 MP_P_CODE; /* parsave & pagecode */ 541 Uchar p_len; /* 0x0A = 12 Bytes */ 542 Ucbit disa_correction : 1; /* Byte 2 */ 543 Ucbit term_on_rec_err : 1; 544 Ucbit report_rec_err : 1; 545 Ucbit en_early_corr : 1; 546 Ucbit res : 4; /* Byte 2 */ 547 Uchar ve_retry_count; /* Byte 3 */ 548 Uchar ve_correction_span; 549 char res2[5]; /* Byte 5 */ 550 Uchar ve_recov_timelim[2]; /* Byte 10 */ 551 }; 552 553 #else /* Motorola byteorder */ 554 555 struct scsi_mode_page_07 { /* Verify Error recovery */ 556 MP_P_CODE; /* parsave & pagecode */ 557 Uchar p_len; /* 0x0A = 12 Bytes */ 558 Ucbit res : 4; /* Byte 2 */ 559 Ucbit en_early_corr : 1; 560 Ucbit report_rec_err : 1; 561 Ucbit term_on_rec_err : 1; 562 Ucbit disa_correction : 1; /* Byte 2 */ 563 Uchar ve_retry_count; /* Byte 3 */ 564 Uchar ve_correction_span; 565 char res2[5]; /* Byte 5 */ 566 Uchar ve_recov_timelim[2]; /* Byte 10 */ 567 }; 568 #endif 569 570 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */ 571 572 struct scsi_mode_page_08 { /* Caching Parameters */ 573 MP_P_CODE; /* parsave & pagecode */ 574 Uchar p_len; /* 0x0A = 12 Bytes */ 575 Ucbit disa_rd_cache : 1; /* Byte 2 */ 576 Ucbit muliple_fact : 1; 577 Ucbit en_wt_cache : 1; 578 Ucbit res : 5; /* Byte 2 */ 579 Ucbit wt_ret_pri : 4; /* Byte 3 */ 580 Ucbit demand_rd_ret_pri: 4; /* Byte 3 */ 581 Uchar disa_pref_tr_len[2]; /* Byte 4 */ 582 Uchar min_pref[2]; /* Byte 6 */ 583 Uchar max_pref[2]; /* Byte 8 */ 584 Uchar max_pref_ceiling[2]; /* Byte 10 */ 585 }; 586 587 #else /* Motorola byteorder */ 588 589 struct scsi_mode_page_08 { /* Caching Parameters */ 590 MP_P_CODE; /* parsave & pagecode */ 591 Uchar p_len; /* 0x0A = 12 Bytes */ 592 Ucbit res : 5; /* Byte 2 */ 593 Ucbit en_wt_cache : 1; 594 Ucbit muliple_fact : 1; 595 Ucbit disa_rd_cache : 1; /* Byte 2 */ 596 Ucbit demand_rd_ret_pri: 4; /* Byte 3 */ 597 Ucbit wt_ret_pri : 4; 598 Uchar disa_pref_tr_len[2]; /* Byte 4 */ 599 Uchar min_pref[2]; /* Byte 6 */ 600 Uchar max_pref[2]; /* Byte 8 */ 601 Uchar max_pref_ceiling[2]; /* Byte 10 */ 602 }; 603 #endif 604 605 struct scsi_mode_page_09 { /* Peripheral device Parameters */ 606 MP_P_CODE; /* parsave & pagecode */ 607 Uchar p_len; /* >= 0x06 = 8 Bytes */ 608 Uchar interface_id[2]; /* Byte 2 */ 609 Uchar res[4]; /* Byte 4 */ 610 Uchar vendor_specific[1]; /* Byte 8 */ 611 }; 612 613 #define PDEV_SCSI 0x0000 /* scsi interface */ 614 #define PDEV_SMD 0x0001 /* SMD interface */ 615 #define PDEV_ESDI 0x0002 /* ESDI interface */ 616 #define PDEV_IPI2 0x0003 /* IPI-2 interface */ 617 #define PDEV_IPI3 0x0004 /* IPI-3 interface */ 618 619 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */ 620 621 struct scsi_mode_page_0A { /* Common device Control Parameters */ 622 MP_P_CODE; /* parsave & pagecode */ 623 Uchar p_len; /* 0x06 = 8 Bytes */ 624 Ucbit rep_log_exeption: 1; /* Byte 2 */ 625 Ucbit res : 7; /* Byte 2 */ 626 Ucbit dis_queuing : 1; /* Byte 3 */ 627 Ucbit queuing_err_man : 1; 628 Ucbit res2 : 2; 629 Ucbit queue_alg_mod : 4; /* Byte 3 */ 630 Ucbit EAENP : 1; /* Byte 4 */ 631 Ucbit UAENP : 1; 632 Ucbit RAENP : 1; 633 Ucbit res3 : 4; 634 Ucbit en_ext_cont_all : 1; /* Byte 4 */ 635 Ucbit res4 : 8; 636 Uchar ready_aen_hold_per[2]; /* Byte 6 */ 637 }; 638 639 #else /* Motorola byteorder */ 640 641 struct scsi_mode_page_0A { /* Common device Control Parameters */ 642 MP_P_CODE; /* parsave & pagecode */ 643 Uchar p_len; /* 0x06 = 8 Bytes */ 644 Ucbit res : 7; /* Byte 2 */ 645 Ucbit rep_log_exeption: 1; /* Byte 2 */ 646 Ucbit queue_alg_mod : 4; /* Byte 3 */ 647 Ucbit res2 : 2; 648 Ucbit queuing_err_man : 1; 649 Ucbit dis_queuing : 1; /* Byte 3 */ 650 Ucbit en_ext_cont_all : 1; /* Byte 4 */ 651 Ucbit res3 : 4; 652 Ucbit RAENP : 1; 653 Ucbit UAENP : 1; 654 Ucbit EAENP : 1; /* Byte 4 */ 655 Ucbit res4 : 8; 656 Uchar ready_aen_hold_per[2]; /* Byte 6 */ 657 }; 658 #endif 659 660 #define CTRL_QMOD_RESTRICT 0x0 661 #define CTRL_QMOD_UNRESTRICT 0x1 662 663 664 struct scsi_mode_page_0B { /* Medium Types Supported Parameters */ 665 MP_P_CODE; /* parsave & pagecode */ 666 Uchar p_len; /* 0x06 = 8 Bytes */ 667 Uchar res[2]; /* Byte 2 */ 668 Uchar medium_one_supp; /* Byte 4 */ 669 Uchar medium_two_supp; /* Byte 5 */ 670 Uchar medium_three_supp; /* Byte 6 */ 671 Uchar medium_four_supp; /* Byte 7 */ 672 }; 673 674 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */ 675 676 struct scsi_mode_page_0C { /* Notch & Partition Parameters */ 677 MP_P_CODE; /* parsave & pagecode */ 678 Uchar p_len; /* 0x16 = 24 Bytes */ 679 Ucbit res : 6; /* Byte 2 */ 680 Ucbit logical_notch : 1; 681 Ucbit notched_drive : 1; /* Byte 2 */ 682 Uchar res2; /* Byte 3 */ 683 Uchar max_notches[2]; /* Byte 4 */ 684 Uchar active_notch[2]; /* Byte 6 */ 685 Uchar starting_boundary[4]; /* Byte 8 */ 686 Uchar ending_boundary[4]; /* Byte 12 */ 687 Uchar pages_notched[8]; /* Byte 16 */ 688 }; 689 690 #else /* Motorola byteorder */ 691 692 struct scsi_mode_page_0C { /* Notch & Partition Parameters */ 693 MP_P_CODE; /* parsave & pagecode */ 694 Uchar p_len; /* 0x16 = 24 Bytes */ 695 Ucbit notched_drive : 1; /* Byte 2 */ 696 Ucbit logical_notch : 1; 697 Ucbit res : 6; /* Byte 2 */ 698 Uchar res2; /* Byte 3 */ 699 Uchar max_notches[2]; /* Byte 4 */ 700 Uchar active_notch[2]; /* Byte 6 */ 701 Uchar starting_boundary[4]; /* Byte 8 */ 702 Uchar ending_boundary[4]; /* Byte 12 */ 703 Uchar pages_notched[8]; /* Byte 16 */ 704 }; 705 #endif 706 707 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */ 708 709 struct scsi_mode_page_0D { /* CD-ROM Parameters */ 710 MP_P_CODE; /* parsave & pagecode */ 711 Uchar p_len; /* 0x06 = 8 Bytes */ 712 Uchar res; /* Byte 2 */ 713 Ucbit inact_timer_mult: 4; /* Byte 3 */ 714 Ucbit res2 : 4; /* Byte 3 */ 715 Uchar s_un_per_m_un[2]; /* Byte 4 */ 716 Uchar f_un_per_s_un[2]; /* Byte 6 */ 717 }; 718 719 #else /* Motorola byteorder */ 720 721 struct scsi_mode_page_0D { /* CD-ROM Parameters */ 722 MP_P_CODE; /* parsave & pagecode */ 723 Uchar p_len; /* 0x06 = 8 Bytes */ 724 Uchar res; /* Byte 2 */ 725 Ucbit res2 : 4; /* Byte 3 */ 726 Ucbit inact_timer_mult: 4; /* Byte 3 */ 727 Uchar s_un_per_m_un[2]; /* Byte 4 */ 728 Uchar f_un_per_s_un[2]; /* Byte 6 */ 729 }; 730 #endif 731 732 struct sony_mode_page_20 { /* Sony Format Mode Parameters */ 733 MP_P_CODE; /* parsave & pagecode */ 734 Uchar p_len; /* 0x0A = 12 Bytes */ 735 Uchar format_mode; 736 Uchar format_type; 737 #define num_bands user_band_size /* Gilt bei Type 1 */ 738 Uchar user_band_size[4]; /* Gilt bei Type 0 */ 739 Uchar spare_band_size[2]; 740 Uchar res[2]; 741 }; 742 743 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */ 744 745 struct toshiba_mode_page_20 { /* Toshiba Speed Control Parameters */ 746 MP_P_CODE; /* parsave & pagecode */ 747 Uchar p_len; /* 0x01 = 3 Bytes */ 748 Ucbit speed : 1; 749 Ucbit res : 7; 750 }; 751 752 #else /* Motorola byteorder */ 753 754 struct toshiba_mode_page_20 { /* Toshiba Speed Control Parameters */ 755 MP_P_CODE; /* parsave & pagecode */ 756 Uchar p_len; /* 0x01 = 3 Bytes */ 757 Ucbit res : 7; 758 Ucbit speed : 1; 759 }; 760 #endif 761 762 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */ 763 764 struct ccs_mode_page_38 { /* CCS Caching Parameters */ 765 MP_P_CODE; /* parsave & pagecode */ 766 Uchar p_len; /* 0x0E = 14 Bytes */ 767 768 Ucbit cache_table_size: 4; /* Byte 3 */ 769 Ucbit cache_en : 1; 770 Ucbit res2 : 1; 771 Ucbit wr_index_en : 1; 772 Ucbit res : 1; /* Byte 3 */ 773 Uchar threshold; /* Byte 4 Prefetch threshold */ 774 Uchar max_prefetch; /* Byte 5 Max. prefetch */ 775 Uchar max_multiplier; /* Byte 6 Max. prefetch multiplier */ 776 Uchar min_prefetch; /* Byte 7 Min. prefetch */ 777 Uchar min_multiplier; /* Byte 8 Min. prefetch multiplier */ 778 Uchar res3[8]; /* Byte 9 */ 779 }; 780 781 #else /* Motorola byteorder */ 782 783 struct ccs_mode_page_38 { /* CCS Caching Parameters */ 784 MP_P_CODE; /* parsave & pagecode */ 785 Uchar p_len; /* 0x0E = 14 Bytes */ 786 787 Ucbit res : 1; /* Byte 3 */ 788 Ucbit wr_index_en : 1; 789 Ucbit res2 : 1; 790 Ucbit cache_en : 1; 791 Ucbit cache_table_size: 4; /* Byte 3 */ 792 Uchar threshold; /* Byte 4 Prefetch threshold */ 793 Uchar max_prefetch; /* Byte 5 Max. prefetch */ 794 Uchar max_multiplier; /* Byte 6 Max. prefetch multiplier */ 795 Uchar min_prefetch; /* Byte 7 Min. prefetch */ 796 Uchar min_multiplier; /* Byte 8 Min. prefetch multiplier */ 797 Uchar res3[8]; /* Byte 9 */ 798 }; 799 #endif 800 801 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */ 802 803 struct cd_mode_page_05 { /* write parameters */ 804 MP_P_CODE; /* parsave & pagecode */ 805 Uchar p_len; /* 0x32 = 50 Bytes */ 806 Ucbit write_type : 4; /* Session write type (PACKET/TAO...)*/ 807 Ucbit test_write : 1; /* Do not actually write data */ 808 Ucbit LS_V : 1; /* Link size valid */ 809 Ucbit BUFE : 1; /* Enable Bufunderrun free rec. */ 810 Ucbit res_2_7 : 1; 811 Ucbit track_mode : 4; /* Track mode (Q-sub control nibble) */ 812 Ucbit copy : 1; /* 1st higher gen of copy prot track ~*/ 813 Ucbit fp : 1; /* Fixed packed (if in packet mode) */ 814 Ucbit multi_session : 2; /* Multi session write type */ 815 Ucbit dbtype : 4; /* Data block type */ 816 Ucbit res_4 : 4; /* Reserved */ 817 Uchar link_size; /* Link Size (default is 7) */ 818 Uchar res_6; /* Reserved */ 819 Ucbit host_appl_code : 6; /* Host application code of disk */ 820 Ucbit res_7 : 2; /* Reserved */ 821 Uchar session_format; /* Session format (DA/CDI/XA) */ 822 Uchar res_9; /* Reserved */ 823 Uchar packet_size[4]; /* # of user datablocks/fixed packet */ 824 Uchar audio_pause_len[2]; /* # of blocks where index is zero */ 825 Uchar media_cat_number[16]; /* Media catalog Number (MCN) */ 826 Uchar ISRC[14]; /* ISRC for this track */ 827 Uchar sub_header[4]; 828 Uchar vendor_uniq[4]; 829 }; 830 831 #else /* Motorola byteorder */ 832 833 struct cd_mode_page_05 { /* write parameters */ 834 MP_P_CODE; /* parsave & pagecode */ 835 Uchar p_len; /* 0x32 = 50 Bytes */ 836 Ucbit res_2_7 : 1; 837 Ucbit BUFE : 1; /* Enable Bufunderrun free rec. */ 838 Ucbit LS_V : 1; /* Link size valid */ 839 Ucbit test_write : 1; /* Do not actually write data */ 840 Ucbit write_type : 4; /* Session write type (PACKET/TAO...)*/ 841 Ucbit multi_session : 2; /* Multi session write type */ 842 Ucbit fp : 1; /* Fixed packed (if in packet mode) */ 843 Ucbit copy : 1; /* 1st higher gen of copy prot track */ 844 Ucbit track_mode : 4; /* Track mode (Q-sub control nibble) */ 845 Ucbit res_4 : 4; /* Reserved */ 846 Ucbit dbtype : 4; /* Data block type */ 847 Uchar link_size; /* Link Size (default is 7) */ 848 Uchar res_6; /* Reserved */ 849 Ucbit res_7 : 2; /* Reserved */ 850 Ucbit host_appl_code : 6; /* Host application code of disk */ 851 Uchar session_format; /* Session format (DA/CDI/XA) */ 852 Uchar res_9; /* Reserved */ 853 Uchar packet_size[4]; /* # of user datablocks/fixed packet */ 854 Uchar audio_pause_len[2]; /* # of blocks where index is zero */ 855 Uchar media_cat_number[16]; /* Media catalog Number (MCN) */ 856 Uchar ISRC[14]; /* ISRC for this track */ 857 Uchar sub_header[4]; 858 Uchar vendor_uniq[4]; 859 }; 860 861 #endif 862 863 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */ 864 865 struct cd_wr_speed_performance { 866 Uchar res0; /* Reserved */ 867 Ucbit rot_ctl_sel : 2; /* Rotational control selected */ 868 Ucbit res_1_27 : 6; /* Reserved */ 869 Uchar wr_speed_supp[2]; /* Supported write speed */ 870 }; 871 872 struct cd_mode_page_2A { /* CD Cap / mech status */ 873 MP_P_CODE; /* parsave & pagecode */ 874 Uchar p_len; /* 0x14 = 20 Bytes (MMC) */ 875 /* 0x18 = 24 Bytes (MMC-2) */ 876 /* 0x1C >= 28 Bytes (MMC-3) */ 877 Ucbit cd_r_read : 1; /* Reads CD-R media */ 878 Ucbit cd_rw_read : 1; /* Reads CD-RW media */ 879 Ucbit method2 : 1; /* Reads fixed packet method2 media */ 880 Ucbit dvd_rom_read : 1; /* Reads DVD ROM media */ 881 Ucbit dvd_r_read : 1; /* Reads DVD-R media */ 882 Ucbit dvd_ram_read : 1; /* Reads DVD-RAM media */ 883 Ucbit res_2_67 : 2; /* Reserved */ 884 Ucbit cd_r_write : 1; /* Supports writing CD-R media */ 885 Ucbit cd_rw_write : 1; /* Supports writing CD-RW media */ 886 Ucbit test_write : 1; /* Supports emulation write */ 887 Ucbit res_3_3 : 1; /* Reserved */ 888 Ucbit dvd_r_write : 1; /* Supports writing DVD-R media */ 889 Ucbit dvd_ram_write : 1; /* Supports writing DVD-RAM media */ 890 Ucbit res_3_67 : 2; /* Reserved */ 891 Ucbit audio_play : 1; /* Supports Audio play operation */ 892 Ucbit composite : 1; /* Deliveres composite A/V stream */ 893 Ucbit digital_port_2 : 1; /* Supports digital output on port 2 */ 894 Ucbit digital_port_1 : 1; /* Supports digital output on port 1 */ 895 Ucbit mode_2_form_1 : 1; /* Reads Mode-2 form 1 media (XA) */ 896 Ucbit mode_2_form_2 : 1; /* Reads Mode-2 form 2 media */ 897 Ucbit multi_session : 1; /* Reads multi-session media */ 898 Ucbit BUF : 1; /* Supports Buffer under. free rec. */ 899 Ucbit cd_da_supported : 1; /* Reads audio data with READ CD cmd */ 900 Ucbit cd_da_accurate : 1; /* READ CD data stream is accurate */ 901 Ucbit rw_supported : 1; /* Reads R-W sub channel information */ 902 Ucbit rw_deint_corr : 1; /* Reads de-interleved R-W sub chan */ 903 Ucbit c2_pointers : 1; /* Supports C2 error pointers */ 904 Ucbit ISRC : 1; /* Reads ISRC information */ 905 Ucbit UPC : 1; /* Reads media catalog number (UPC) */ 906 Ucbit read_bar_code : 1; /* Supports reading bar codes */ 907 Ucbit lock : 1; /* PREVENT/ALLOW may lock media */ 908 Ucbit lock_state : 1; /* Lock state 0=unlocked 1=locked */ 909 Ucbit prevent_jumper : 1; /* State of prev/allow jumper 0=pres */ 910 Ucbit eject : 1; /* Ejects disc/cartr with STOP LoEj */ 911 Ucbit res_6_4 : 1; /* Reserved */ 912 Ucbit loading_type : 3; /* Loading mechanism type */ 913 Ucbit sep_chan_vol : 1; /* Vol controls each channel separat */ 914 Ucbit sep_chan_mute : 1; /* Mute controls each channel separat*/ 915 Ucbit disk_present_rep: 1; /* Changer supports disk present rep */ 916 Ucbit sw_slot_sel : 1; /* Load empty slot in changer */ 917 Ucbit side_change : 1; /* Side change capable */ 918 Ucbit pw_in_lead_in : 1; /* Reads raw P-W sucode from lead in */ 919 Ucbit res_7 : 2; /* Reserved */ 920 Uchar max_read_speed[2]; /* Max. read speed in KB/s */ 921 Uchar num_vol_levels[2]; /* # of supported volume levels */ 922 Uchar buffer_size[2]; /* Buffer size for the data in KB */ 923 Uchar cur_read_speed[2]; /* Current read speed in KB/s */ 924 Uchar res_16; /* Reserved */ 925 Ucbit res_17_0 : 1; /* Reserved */ 926 Ucbit BCK : 1; /* Data valid on falling edge of BCK */ 927 Ucbit RCK : 1; /* Set: HIGH high LRCK=left channel */ 928 Ucbit LSBF : 1; /* Set: LSB first Clear: MSB first */ 929 Ucbit length : 2; /* 0=32BCKs 1=16BCKs 2=24BCKs 3=24I2c*/ 930 Ucbit res_17 : 2; /* Reserved */ 931 Uchar max_write_speed[2]; /* Max. write speed supported in KB/s*/ 932 Uchar cur_write_speed[2]; /* Current write speed in KB/s */ 933 934 /* Byte 22 ... Only in MMC-2 */ 935 Uchar copy_man_rev[2]; /* Copy management revision supported*/ 936 Uchar res_24; /* Reserved */ 937 Uchar res_25; /* Reserved */ 938 939 /* Byte 26 ... Only in MMC-3 */ 940 Uchar res_26; /* Reserved */ 941 Ucbit res_27_27 : 6; /* Reserved */ 942 Ucbit rot_ctl_sel : 2; /* Rotational control selected */ 943 Uchar v3_cur_write_speed[2]; /* Current write speed in KB/s */ 944 Uchar num_wr_speed_des[2]; /* # of wr speed perf descr. tables */ 945 struct cd_wr_speed_performance 946 wr_speed_des[1]; /* wr speed performance descriptor */ 947 /* Actually more (num_wr_speed_des) */ 948 }; 949 950 #else /* Motorola byteorder */ 951 952 struct cd_wr_speed_performance { 953 Uchar res0; /* Reserved */ 954 Ucbit res_1_27 : 6; /* Reserved */ 955 Ucbit rot_ctl_sel : 2; /* Rotational control selected */ 956 Uchar wr_speed_supp[2]; /* Supported write speed */ 957 }; 958 959 struct cd_mode_page_2A { /* CD Cap / mech status */ 960 MP_P_CODE; /* parsave & pagecode */ 961 Uchar p_len; /* 0x14 = 20 Bytes (MMC) */ 962 /* 0x18 = 24 Bytes (MMC-2) */ 963 /* 0x1C >= 28 Bytes (MMC-3) */ 964 Ucbit res_2_67 : 2; /* Reserved */ 965 Ucbit dvd_ram_read : 1; /* Reads DVD-RAM media */ 966 Ucbit dvd_r_read : 1; /* Reads DVD-R media */ 967 Ucbit dvd_rom_read : 1; /* Reads DVD ROM media */ 968 Ucbit method2 : 1; /* Reads fixed packet method2 media */ 969 Ucbit cd_rw_read : 1; /* Reads CD-RW media */ 970 Ucbit cd_r_read : 1; /* Reads CD-R media */ 971 Ucbit res_3_67 : 2; /* Reserved */ 972 Ucbit dvd_ram_write : 1; /* Supports writing DVD-RAM media */ 973 Ucbit dvd_r_write : 1; /* Supports writing DVD-R media */ 974 Ucbit res_3_3 : 1; /* Reserved */ 975 Ucbit test_write : 1; /* Supports emulation write */ 976 Ucbit cd_rw_write : 1; /* Supports writing CD-RW media */ 977 Ucbit cd_r_write : 1; /* Supports writing CD-R media */ 978 Ucbit BUF : 1; /* Supports Buffer under. free rec. */ 979 Ucbit multi_session : 1; /* Reads multi-session media */ 980 Ucbit mode_2_form_2 : 1; /* Reads Mode-2 form 2 media */ 981 Ucbit mode_2_form_1 : 1; /* Reads Mode-2 form 1 media (XA) */ 982 Ucbit digital_port_1 : 1; /* Supports digital output on port 1 */ 983 Ucbit digital_port_2 : 1; /* Supports digital output on port 2 */ 984 Ucbit composite : 1; /* Deliveres composite A/V stream */ 985 Ucbit audio_play : 1; /* Supports Audio play operation */ 986 Ucbit read_bar_code : 1; /* Supports reading bar codes */ 987 Ucbit UPC : 1; /* Reads media catalog number (UPC) */ 988 Ucbit ISRC : 1; /* Reads ISRC information */ 989 Ucbit c2_pointers : 1; /* Supports C2 error pointers */ 990 Ucbit rw_deint_corr : 1; /* Reads de-interleved R-W sub chan */ 991 Ucbit rw_supported : 1; /* Reads R-W sub channel information */ 992 Ucbit cd_da_accurate : 1; /* READ CD data stream is accurate */ 993 Ucbit cd_da_supported : 1; /* Reads audio data with READ CD cmd */ 994 Ucbit loading_type : 3; /* Loading mechanism type */ 995 Ucbit res_6_4 : 1; /* Reserved */ 996 Ucbit eject : 1; /* Ejects disc/cartr with STOP LoEj */ 997 Ucbit prevent_jumper : 1; /* State of prev/allow jumper 0=pres */ 998 Ucbit lock_state : 1; /* Lock state 0=unlocked 1=locked */ 999 Ucbit lock : 1; /* PREVENT/ALLOW may lock media */ 1000 Ucbit res_7 : 2; /* Reserved */ 1001 Ucbit pw_in_lead_in : 1; /* Reads raw P-W sucode from lead in */ 1002 Ucbit side_change : 1; /* Side change capable */ 1003 Ucbit sw_slot_sel : 1; /* Load empty slot in changer */ 1004 Ucbit disk_present_rep: 1; /* Changer supports disk present rep */ 1005 Ucbit sep_chan_mute : 1; /* Mute controls each channel separat*/ 1006 Ucbit sep_chan_vol : 1; /* Vol controls each channel separat */ 1007 Uchar max_read_speed[2]; /* Max. read speed in KB/s */ 1008 Uchar num_vol_levels[2]; /* # of supported volume levels */ 1009 Uchar buffer_size[2]; /* Buffer size for the data in KB */ 1010 Uchar cur_read_speed[2]; /* Current read speed in KB/s */ 1011 Uchar res_16; /* Reserved */ 1012 Ucbit res_17 : 2; /* Reserved */ 1013 Ucbit length : 2; /* 0=32BCKs 1=16BCKs 2=24BCKs 3=24I2c*/ 1014 Ucbit LSBF : 1; /* Set: LSB first Clear: MSB first */ 1015 Ucbit RCK : 1; /* Set: HIGH high LRCK=left channel */ 1016 Ucbit BCK : 1; /* Data valid on falling edge of BCK */ 1017 Ucbit res_17_0 : 1; /* Reserved */ 1018 Uchar max_write_speed[2]; /* Max. write speed supported in KB/s*/ 1019 Uchar cur_write_speed[2]; /* Current write speed in KB/s */ 1020 1021 /* Byte 22 ... Only in MMC-2 */ 1022 Uchar copy_man_rev[2]; /* Copy management revision supported*/ 1023 Uchar res_24; /* Reserved */ 1024 Uchar res_25; /* Reserved */ 1025 1026 /* Byte 26 ... Only in MMC-3 */ 1027 Uchar res_26; /* Reserved */ 1028 Ucbit res_27_27 : 6; /* Reserved */ 1029 Ucbit rot_ctl_sel : 2; /* Rotational control selected */ 1030 Uchar v3_cur_write_speed[2]; /* Current write speed in KB/s */ 1031 Uchar num_wr_speed_des[2]; /* # of wr speed perf descr. tables */ 1032 struct cd_wr_speed_performance 1033 wr_speed_des[1]; /* wr speed performance descriptor */ 1034 /* Actually more (num_wr_speed_des) */ 1035 }; 1036 1037 #endif 1038 1039 #define LT_CADDY 0 1040 #define LT_TRAY 1 1041 #define LT_POP_UP 2 1042 #define LT_RES3 3 1043 #define LT_CHANGER_IND 4 1044 #define LT_CHANGER_CART 5 1045 #define LT_RES6 6 1046 #define LT_RES7 7 1047 1048 1049 struct scsi_mode_data { 1050 struct scsi_mode_header header; 1051 struct scsi_mode_blockdesc blockdesc; 1052 union pagex { 1053 struct acb_mode_data acb; 1054 struct scsi_mode_page_01 page1; 1055 struct scsi_mode_page_02 page2; 1056 struct scsi_mode_page_03 page3; 1057 struct scsi_mode_page_04 page4; 1058 struct scsi_mode_page_05 page5; 1059 struct scsi_mode_page_07 page7; 1060 struct scsi_mode_page_08 page8; 1061 struct scsi_mode_page_09 page9; 1062 struct scsi_mode_page_0A pageA; 1063 struct scsi_mode_page_0B pageB; 1064 struct scsi_mode_page_0C pageC; 1065 struct scsi_mode_page_0D pageD; 1066 struct sony_mode_page_20 sony20; 1067 struct toshiba_mode_page_20 toshiba20; 1068 struct ccs_mode_page_38 ccs38; 1069 } pagex; 1070 }; 1071 1072 struct scsi_capacity { 1073 Int32_t c_baddr; /* must convert byteorder!! */ 1074 Int32_t c_bsize; /* must convert byteorder!! */ 1075 }; 1076 1077 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */ 1078 1079 struct scsi_def_header { 1080 Ucbit : 8; 1081 Ucbit format : 3; 1082 Ucbit gdl : 1; 1083 Ucbit mdl : 1; 1084 Ucbit : 3; 1085 Uchar length[2]; 1086 }; 1087 1088 #else /* Motorola byteorder */ 1089 1090 struct scsi_def_header { 1091 Ucbit : 8; 1092 Ucbit : 3; 1093 Ucbit mdl : 1; 1094 Ucbit gdl : 1; 1095 Ucbit format : 3; 1096 Uchar length[2]; 1097 }; 1098 #endif 1099 1100 1101 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */ 1102 1103 struct scsi_format_header { 1104 Ucbit res : 8; /* Adaptec 5500: 1 --> format track */ 1105 Ucbit vu : 1; /* Vendor Unique */ 1106 Ucbit immed : 1; /* Return Immediately from Format */ 1107 Ucbit tryout : 1; /* Check if format parameters OK */ 1108 Ucbit ipattern : 1; /* Init patter descriptor present */ 1109 Ucbit serr : 1; /* Stop on error */ 1110 Ucbit dcert : 1; /* Disable certification */ 1111 Ucbit dmdl : 1; /* Disable manufacturer defect list */ 1112 Ucbit enable : 1; /* Enable to use the next 3 bits */ 1113 Uchar length[2]; /* Length of following list in bytes*/ 1114 }; 1115 1116 #else /* Motorola byteorder */ 1117 1118 struct scsi_format_header { 1119 Ucbit res : 8; /* Adaptec 5500: 1 --> format track */ 1120 Ucbit enable : 1; /* Enable to use the next 3 bits */ 1121 Ucbit dmdl : 1; /* Disable manufacturer defect list */ 1122 Ucbit dcert : 1; /* Disable certification */ 1123 Ucbit serr : 1; /* Stop on error */ 1124 Ucbit ipattern : 1; /* Init patter descriptor present */ 1125 Ucbit tryout : 1; /* Check if format parameters OK */ 1126 Ucbit immed : 1; /* Return Immediately from Format */ 1127 Ucbit vu : 1; /* Vendor Unique */ 1128 Uchar length[2]; /* Length of following list in bytes*/ 1129 }; 1130 #endif 1131 1132 struct scsi_def_bfi { 1133 Uchar cyl[3]; 1134 Uchar head; 1135 Uchar bfi[4]; 1136 }; 1137 1138 struct scsi_def_phys { 1139 Uchar cyl[3]; 1140 Uchar head; 1141 Uchar sec[4]; 1142 }; 1143 1144 struct scsi_def_list { 1145 struct scsi_def_header hd; 1146 union { 1147 Uchar list_block[1][4]; 1148 struct scsi_def_bfi list_bfi[1]; 1149 struct scsi_def_phys list_phys[1]; 1150 } def_list; 1151 }; 1152 1153 struct scsi_format_data { 1154 struct scsi_format_header hd; 1155 union { 1156 Uchar list_block[1][4]; 1157 struct scsi_def_bfi list_bfi[1]; 1158 struct scsi_def_phys list_phys[1]; 1159 } def_list; 1160 }; 1161 1162 #define def_block def_list.list_block 1163 #define def_bfi def_list.list_bfi 1164 #define def_phys def_list.list_phys 1165 1166 #define SC_DEF_BLOCK 0 1167 #define SC_DEF_BFI 4 1168 #define SC_DEF_PHYS 5 1169 #define SC_DEF_VU 6 1170 #define SC_DEF_RES 7 1171 1172 struct scsi_format_cap_header { 1173 Uchar res[3]; /* Reserved */ 1174 Uchar len; /* Len (a multiple of 8) */ 1175 }; 1176 1177 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */ 1178 1179 struct scsi_format_cap_desc { 1180 Uchar nblock[4]; /* Number of blocks */ 1181 Ucbit desc_type : 2; /* Descriptor type */ 1182 Ucbit fmt_type : 6; /* Format Type */ 1183 Uchar blen[3]; /* Logical block length */ 1184 }; 1185 1186 #else /* Motorola byteorder */ 1187 1188 struct scsi_format_cap_desc { 1189 Uchar nblock[4]; /* Number of blocks */ 1190 Ucbit fmt_type : 6; /* Format Type */ 1191 Ucbit desc_type : 2; /* Descriptor type */ 1192 Uchar blen[3]; /* Logical block length */ 1193 }; 1194 #endif 1195 1196 /* 1197 * Defines for 'fmt_type'. 1198 */ 1199 #define FCAP_TYPE_FULL 0x00 /* Full Format */ 1200 #define FCAP_TYPE_EXPAND_SPARE 0x01 /* Spare area expansion */ 1201 #define FCAP_TYPE_ZONE_REFORMAT 0x04 /* DVD-RAM Zone Reformat */ 1202 #define FCAP_TYPE_ZONE_FORMAT 0x05 /* DVD-RAM Zone Format */ 1203 #define FCAP_TYPE_CDRW_FULL 0x10 /* CD-RW/DVD-RW Full Format */ 1204 #define FACP_TYPE_CDRW_GROW_SES 0x11 /* CD-RW/DVD-RW grow session */ 1205 #define FACP_TYPE_CDRW_ADD_SES 0x12 /* CD-RW/DVD-RW add session */ 1206 #define FACP_TYPE_DVDRW_QGROW 0x13 /* DVD-RW quick grow last border*/ 1207 #define FACP_TYPE_DVDRW_QADD_SES 0x14 /* DVD-RW quick add session */ 1208 #define FACP_TYPE_DVDRW_QUICK 0x15 /* DVD-RW quick interm. session */ 1209 #define FCAP_TYPE_FULL_SPARE 0x20 /* Full Format with sparing */ 1210 #define FCAP_TYPE_MRW_FULL 0x24 /* CD-RW/DVD+RW Full Format */ 1211 #define FCAP_TYPE_DVDPLUS_BASIC 0x26 /* DVD+RW Basic Format */ 1212 #define FCAP_TYPE_DVDPLUS_FULL 0x26 /* DVD+RW Full Format */ 1213 #define FCAP_TYPE_BDRE_SPARE 0x30 /* BD-RE Full Format with spare */ 1214 #define FCAP_TYPE_BDRE 0x31 /* BD-RE Full Format without spare*/ 1215 #define FCAP_TYPE_BDR_SPARE 0x32 /* BD-R Full Format with spare */ 1216 1217 /* 1218 * Defines for 'desc_type'. 1219 * In case of FCAP_DESC_RES, the descriptor is a formatted capacity descriptor 1220 * and the 'blen' field is type dependent. 1221 * For all other cases, this is the Current/Maximum Capacity descriptor and 1222 * the value of 'fmt_type' is reserved and must be zero. 1223 */ 1224 #define FCAP_DESC_RES 0 /* Reserved */ 1225 #define FCAP_DESC_UNFORM 1 /* Unformatted Media */ 1226 #define FCAP_DESC_FORM 2 /* Formatted Media */ 1227 #define FCAP_DESC_NOMEDIA 3 /* No Media */ 1228 1229 struct scsi_cap_data { 1230 struct scsi_format_cap_header hd; 1231 struct scsi_format_cap_desc list[1]; 1232 }; 1233 1234 1235 struct scsi_send_diag_cmd { 1236 Uchar cmd; 1237 Uchar addr[4]; 1238 Ucbit : 8; 1239 }; 1240 1241 #if defined(_BIT_FIELDS_LTOH) /* Intel byteorder */ 1242 1243 struct scsi_sector_header { 1244 Uchar cyl[2]; 1245 Uchar head; 1246 Uchar sec; 1247 Ucbit : 5; 1248 Ucbit rp : 1; 1249 Ucbit sp : 1; 1250 Ucbit dt : 1; 1251 }; 1252 1253 #else /* Motorola byteorder */ 1254 1255 struct scsi_sector_header { 1256 Uchar cyl[2]; 1257 Uchar head; 1258 Uchar sec; 1259 Ucbit dt : 1; 1260 Ucbit sp : 1; 1261 Ucbit rp : 1; 1262 Ucbit : 5; 1263 }; 1264 #endif 1265 1266 #ifdef __cplusplus 1267 } 1268 #endif 1269 1270 #endif /* _SCG_SCSIREG_H */ 1271