1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Interrupt Timer Subsystem 4 * 5 * Copyright (C) 2017 Intel Corporation. 6 * Copyright 2019 Google LLC 7 * 8 * Modified from coreboot itss.h 9 */ 10 11 #ifndef _ASM_ARCH_ITSS_H 12 #define _ASM_ARCH_ITSS_H 13 14 #include <irq.h> 15 16 #define GPIO_IRQ_START 50 17 #define GPIO_IRQ_END ITSS_MAX_IRQ 18 19 #define ITSS_MAX_IRQ 119 20 #define IRQS_PER_IPC 32 21 #define NUM_IPC_REGS DIV_ROUND_UP(ITSS_MAX_IRQ, IRQS_PER_IPC) 22 23 /* Max PXRC registers in ITSS */ 24 #define MAX_PXRC_CONFIG (PCR_ITSS_PIRQH_ROUT - PCR_ITSS_PIRQA_ROUT + 1) 25 26 /* PIRQA Routing Control Register */ 27 #define PCR_ITSS_PIRQA_ROUT 0x3100 28 /* PIRQB Routing Control Register */ 29 #define PCR_ITSS_PIRQB_ROUT 0x3101 30 /* PIRQC Routing Control Register */ 31 #define PCR_ITSS_PIRQC_ROUT 0x3102 32 /* PIRQD Routing Control Register */ 33 #define PCR_ITSS_PIRQD_ROUT 0x3103 34 /* PIRQE Routing Control Register */ 35 #define PCR_ITSS_PIRQE_ROUT 0x3104 36 /* PIRQF Routing Control Register */ 37 #define PCR_ITSS_PIRQF_ROUT 0x3105 38 /* PIRQG Routing Control Register */ 39 #define PCR_ITSS_PIRQG_ROUT 0x3106 40 /* PIRQH Routing Control Register */ 41 #define PCR_ITSS_PIRQH_ROUT 0x3107 42 /* ITSS Interrupt polarity control */ 43 #define PCR_ITSS_IPC0_CONF 0x3200 44 /* ITSS Power reduction control */ 45 #define PCR_ITSS_ITSSPRC 0x3300 46 47 struct itss_plat { 48 #if CONFIG_IS_ENABLED(OF_PLATDATA) 49 /* Put this first since driver model will copy the data here */ 50 struct dtd_intel_itss dtplat; 51 #endif 52 }; 53 54 /* struct pmc_route - Routing for PMC to GPIO */ 55 struct pmc_route { 56 u32 pmc; 57 u32 gpio; 58 }; 59 60 struct itss_priv { 61 struct pmc_route *route; 62 uint route_count; 63 u32 irq_snapshot[NUM_IPC_REGS]; 64 }; 65 66 #endif /* _ASM_ARCH_ITSS_H */ 67