1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * (C) Copyright 2015 - 2016, Xilinx, Inc,
4 * Michal Simek <michal.simek@xilinx.com>
5 * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
6 */
7
8 #include <console.h>
9 #include <common.h>
10 #include <compiler.h>
11 #include <cpu_func.h>
12 #include <log.h>
13 #include <zynqmppl.h>
14 #include <zynqmp_firmware.h>
15 #include <asm/cache.h>
16 #include <linux/bitops.h>
17 #include <linux/sizes.h>
18 #include <asm/arch/sys_proto.h>
19 #include <memalign.h>
20
21 #define DUMMY_WORD 0xffffffff
22
23 /* Xilinx binary format header */
24 static const u32 bin_format[] = {
25 DUMMY_WORD, /* Dummy words */
26 DUMMY_WORD,
27 DUMMY_WORD,
28 DUMMY_WORD,
29 DUMMY_WORD,
30 DUMMY_WORD,
31 DUMMY_WORD,
32 DUMMY_WORD,
33 DUMMY_WORD,
34 DUMMY_WORD,
35 DUMMY_WORD,
36 DUMMY_WORD,
37 DUMMY_WORD,
38 DUMMY_WORD,
39 DUMMY_WORD,
40 DUMMY_WORD,
41 0x000000bb, /* Sync word */
42 0x11220044, /* Sync word */
43 DUMMY_WORD,
44 DUMMY_WORD,
45 0xaa995566, /* Sync word */
46 };
47
48 #define SWAP_NO 1
49 #define SWAP_DONE 2
50
51 /*
52 * Load the whole word from unaligned buffer
53 * Keep in your mind that it is byte loading on little-endian system
54 */
load_word(const void * buf,u32 swap)55 static u32 load_word(const void *buf, u32 swap)
56 {
57 u32 word = 0;
58 u8 *bitc = (u8 *)buf;
59 int p;
60
61 if (swap == SWAP_NO) {
62 for (p = 0; p < 4; p++) {
63 word <<= 8;
64 word |= bitc[p];
65 }
66 } else {
67 for (p = 3; p >= 0; p--) {
68 word <<= 8;
69 word |= bitc[p];
70 }
71 }
72
73 return word;
74 }
75
check_header(const void * buf)76 static u32 check_header(const void *buf)
77 {
78 u32 i, pattern;
79 int swap = SWAP_NO;
80 u32 *test = (u32 *)buf;
81
82 debug("%s: Let's check bitstream header\n", __func__);
83
84 /* Checking that passing bin is not a bitstream */
85 for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
86 pattern = load_word(&test[i], swap);
87
88 /*
89 * Bitstreams in binary format are swapped
90 * compare to regular bistream.
91 * Do not swap dummy word but if swap is done assume
92 * that parsing buffer is binary format
93 */
94 if ((__swab32(pattern) != DUMMY_WORD) &&
95 (__swab32(pattern) == bin_format[i])) {
96 swap = SWAP_DONE;
97 debug("%s: data swapped - let's swap\n", __func__);
98 }
99
100 debug("%s: %d/%px: pattern %x/%x bin_format\n", __func__, i,
101 &test[i], pattern, bin_format[i]);
102 }
103 debug("%s: Found bitstream header at %px %s swapinng\n", __func__,
104 buf, swap == SWAP_NO ? "without" : "with");
105
106 return swap;
107 }
108
check_data(u8 * buf,size_t bsize,u32 * swap)109 static void *check_data(u8 *buf, size_t bsize, u32 *swap)
110 {
111 u32 word, p = 0; /* possition */
112
113 /* Because buf doesn't need to be aligned let's read it by chars */
114 for (p = 0; p < bsize; p++) {
115 word = load_word(&buf[p], SWAP_NO);
116 debug("%s: word %x %x/%px\n", __func__, word, p, &buf[p]);
117
118 /* Find the first bitstream dummy word */
119 if (word == DUMMY_WORD) {
120 debug("%s: Found dummy word at position %x/%px\n",
121 __func__, p, &buf[p]);
122 *swap = check_header(&buf[p]);
123 if (*swap) {
124 /* FIXME add full bitstream checking here */
125 return &buf[p];
126 }
127 }
128 /* Loop can be huge - support CTRL + C */
129 if (ctrlc())
130 return NULL;
131 }
132 return NULL;
133 }
134
zynqmp_align_dma_buffer(u32 * buf,u32 len,u32 swap)135 static ulong zynqmp_align_dma_buffer(u32 *buf, u32 len, u32 swap)
136 {
137 u32 *new_buf;
138 u32 i;
139
140 if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
141 new_buf = (u32 *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
142
143 /*
144 * This might be dangerous but permits to flash if
145 * ARCH_DMA_MINALIGN is greater than header size
146 */
147 if (new_buf > (u32 *)buf) {
148 debug("%s: Aligned buffer is after buffer start\n",
149 __func__);
150 new_buf -= ARCH_DMA_MINALIGN;
151 }
152 printf("%s: Align buffer at %px to %px(swap %d)\n", __func__,
153 buf, new_buf, swap);
154
155 for (i = 0; i < (len/4); i++)
156 new_buf[i] = load_word(&buf[i], swap);
157
158 buf = new_buf;
159 } else if ((swap != SWAP_DONE) &&
160 (zynqmp_firmware_version() <= PMUFW_V1_0)) {
161 /* For bitstream which are aligned */
162 new_buf = buf;
163
164 printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
165 swap);
166
167 for (i = 0; i < (len/4); i++)
168 new_buf[i] = load_word(&buf[i], swap);
169 }
170
171 return (ulong)buf;
172 }
173
zynqmp_validate_bitstream(xilinx_desc * desc,const void * buf,size_t bsize,u32 blocksize,u32 * swap)174 static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf,
175 size_t bsize, u32 blocksize, u32 *swap)
176 {
177 ulong *buf_start;
178 ulong diff;
179
180 buf_start = check_data((u8 *)buf, blocksize, swap);
181
182 if (!buf_start)
183 return FPGA_FAIL;
184
185 /* Check if data is postpone from start */
186 diff = (ulong)buf_start - (ulong)buf;
187 if (diff) {
188 printf("%s: Bitstream is not validated yet (diff %lx)\n",
189 __func__, diff);
190 return FPGA_FAIL;
191 }
192
193 if ((ulong)buf < SZ_1M) {
194 printf("%s: Bitstream has to be placed up to 1MB (%px)\n",
195 __func__, buf);
196 return FPGA_FAIL;
197 }
198
199 return 0;
200 }
201
zynqmp_load(xilinx_desc * desc,const void * buf,size_t bsize,bitstream_type bstype)202 static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
203 bitstream_type bstype)
204 {
205 ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1);
206 u32 swap = 0;
207 ulong bin_buf;
208 int ret;
209 u32 buf_lo, buf_hi;
210 u32 ret_payload[PAYLOAD_ARG_CNT];
211 bool xilfpga_old = false;
212
213 if (zynqmp_firmware_version() <= PMUFW_V1_0) {
214 puts("WARN: PMUFW v1.0 or less is detected\n");
215 puts("WARN: Not all bitstream formats are supported\n");
216 puts("WARN: Please upgrade PMUFW\n");
217 xilfpga_old = true;
218 if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap))
219 return FPGA_FAIL;
220 bsizeptr = (u32 *)&bsize;
221 flush_dcache_range((ulong)bsizeptr,
222 (ulong)bsizeptr + sizeof(size_t));
223 bstype |= BIT(ZYNQMP_FPGA_BIT_NS);
224 }
225
226 bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap);
227
228 debug("%s called!\n", __func__);
229 flush_dcache_range(bin_buf, bin_buf + bsize);
230
231 buf_lo = (u32)bin_buf;
232 buf_hi = upper_32_bits(bin_buf);
233
234 if (xilfpga_old)
235 ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
236 buf_hi, (u32)(uintptr_t)bsizeptr,
237 bstype, ret_payload);
238 else
239 ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
240 buf_hi, (u32)bsize, 0, ret_payload);
241
242 if (ret)
243 printf("PL FPGA LOAD failed with err: 0x%08x\n", ret);
244
245 return ret;
246 }
247
248 #if defined(CONFIG_CMD_FPGA_LOAD_SECURE) && !defined(CONFIG_SPL_BUILD)
zynqmp_loads(xilinx_desc * desc,const void * buf,size_t bsize,struct fpga_secure_info * fpga_sec_info)249 static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize,
250 struct fpga_secure_info *fpga_sec_info)
251 {
252 int ret;
253 u32 buf_lo, buf_hi;
254 u32 ret_payload[PAYLOAD_ARG_CNT];
255 u8 flag = 0;
256
257 flush_dcache_range((ulong)buf, (ulong)buf +
258 ALIGN(bsize, CONFIG_SYS_CACHELINE_SIZE));
259
260 if (!fpga_sec_info->encflag)
261 flag |= BIT(ZYNQMP_FPGA_BIT_ENC_DEV_KEY);
262
263 if (fpga_sec_info->userkey_addr &&
264 fpga_sec_info->encflag == FPGA_ENC_USR_KEY) {
265 flush_dcache_range((ulong)fpga_sec_info->userkey_addr,
266 (ulong)fpga_sec_info->userkey_addr +
267 ALIGN(KEY_PTR_LEN,
268 CONFIG_SYS_CACHELINE_SIZE));
269 flag |= BIT(ZYNQMP_FPGA_BIT_ENC_USR_KEY);
270 }
271
272 if (!fpga_sec_info->authflag)
273 flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_OCM);
274
275 if (fpga_sec_info->authflag == ZYNQMP_FPGA_AUTH_DDR)
276 flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_DDR);
277
278 buf_lo = lower_32_bits((ulong)buf);
279 buf_hi = upper_32_bits((ulong)buf);
280
281 ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
282 buf_hi,
283 (u32)(uintptr_t)fpga_sec_info->userkey_addr,
284 flag, ret_payload);
285 if (ret)
286 puts("PL FPGA LOAD fail\n");
287 else
288 puts("Bitstream successfully loaded\n");
289
290 return ret;
291 }
292 #endif
293
zynqmp_pcap_info(xilinx_desc * desc)294 static int zynqmp_pcap_info(xilinx_desc *desc)
295 {
296 int ret;
297 u32 ret_payload[PAYLOAD_ARG_CNT];
298
299 ret = xilinx_pm_request(PM_FPGA_GET_STATUS, 0, 0, 0,
300 0, ret_payload);
301 if (!ret)
302 printf("PCAP status\t0x%x\n", ret_payload[1]);
303
304 return ret;
305 }
306
307 struct xilinx_fpga_op zynqmp_op = {
308 .load = zynqmp_load,
309 #if defined(CONFIG_CMD_FPGA_LOAD_SECURE) && !defined(CONFIG_SPL_BUILD)
310 .loads = zynqmp_loads,
311 #endif
312 .info = zynqmp_pcap_info,
313 };
314