1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. 4 * Copyright 2020 NXP 5 */ 6 7 /* 8 * mpc8548cds board configuration file 9 * 10 * Please refer to doc/README.mpc85xxcds for more info. 11 * 12 */ 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 #define CONFIG_SYS_SRIO 17 #define CONFIG_SRIO1 /* SRIO port 1 */ 18 19 #define CONFIG_PCI1 /* PCI controller 1 */ 20 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 21 #undef CONFIG_PCI2 22 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 23 24 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 25 26 #ifndef __ASSEMBLY__ 27 #include <linux/stringify.h> 28 extern unsigned long get_clock_freq(void); 29 #endif 30 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 31 32 /* 33 * These can be toggled for performance analysis, otherwise use default. 34 */ 35 #define CONFIG_L2_CACHE /* toggle L2 cache */ 36 #define CONFIG_BTB /* toggle branch predition */ 37 38 /* 39 * Only possible on E500 Version 2 or newer cores. 40 */ 41 #define CONFIG_ENABLE_36BIT_PHYS 1 42 43 #define CONFIG_SYS_CCSRBAR 0xe0000000 44 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 45 46 /* DDR Setup */ 47 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 48 #define CONFIG_DDR_SPD 49 50 #define CONFIG_DDR_ECC 51 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 52 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 53 54 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 55 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 56 57 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 58 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 59 60 /* I2C addresses of SPD EEPROMs */ 61 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 62 63 /* Make sure required options are set */ 64 #ifndef CONFIG_SPD_EEPROM 65 #error ("CONFIG_SPD_EEPROM is required") 66 #endif 67 68 /* 69 * Physical Address Map 70 * 71 * 32bit: 72 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable 73 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable 74 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable 75 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable 76 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 77 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable 78 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable 79 * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable 80 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable 81 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 82 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 83 * 84 * 36bit: 85 * 0x00000_0000 0x07fff_ffff DDR 2G cacheable 86 * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable 87 * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable 88 * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable 89 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable 90 * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable 91 * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable 92 * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable 93 * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable 94 * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable 95 * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable 96 * 97 */ 98 99 /* 100 * Local Bus Definitions 101 */ 102 103 /* 104 * FLASH on the Local Bus 105 * Two banks, 8M each, using the CFI driver. 106 * Boot from BR0/OR0 bank at 0xff00_0000 107 * Alternate BR1/OR1 bank at 0xff80_0000 108 * 109 * BR0, BR1: 110 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 111 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 112 * Port Size = 16 bits = BRx[19:20] = 10 113 * Use GPCM = BRx[24:26] = 000 114 * Valid = BRx[31] = 1 115 * 116 * 0 4 8 12 16 20 24 28 117 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 118 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 119 * 120 * OR0, OR1: 121 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 122 * Reserved ORx[17:18] = 11, confusion here? 123 * CSNT = ORx[20] = 1 124 * ACS = half cycle delay = ORx[21:22] = 11 125 * SCY = 6 = ORx[24:27] = 0110 126 * TRLX = use relaxed timing = ORx[29] = 1 127 * EAD = use external address latch delay = OR[31] = 1 128 * 129 * 0 4 8 12 16 20 24 28 130 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 131 */ 132 133 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 134 #ifdef CONFIG_PHYS_64BIT 135 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull 136 #else 137 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 138 #endif 139 140 #define CONFIG_SYS_BR0_PRELIM \ 141 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V) 142 #define CONFIG_SYS_BR1_PRELIM \ 143 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 144 145 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 146 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 147 148 #define CONFIG_SYS_FLASH_BANKS_LIST \ 149 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} 150 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 151 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 152 #undef CONFIG_SYS_FLASH_CHECKSUM 153 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 154 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 155 156 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 157 158 #define CONFIG_SYS_FLASH_EMPTY_INFO 159 160 #define CONFIG_HWCONFIG /* enable hwconfig */ 161 162 /* 163 * SDRAM on the Local Bus 164 */ 165 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 166 #ifdef CONFIG_PHYS_64BIT 167 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull 168 #else 169 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE 170 #endif 171 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 172 173 /* 174 * Base Register 2 and Option Register 2 configure SDRAM. 175 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 176 * 177 * For BR2, need: 178 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 179 * port-size = 32-bits = BR2[19:20] = 11 180 * no parity checking = BR2[21:22] = 00 181 * SDRAM for MSEL = BR2[24:26] = 011 182 * Valid = BR[31] = 1 183 * 184 * 0 4 8 12 16 20 24 28 185 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 186 * 187 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 188 * FIXME: the top 17 bits of BR2. 189 */ 190 191 #define CONFIG_SYS_BR2_PRELIM \ 192 (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \ 193 | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V) 194 195 /* 196 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 197 * 198 * For OR2, need: 199 * 64MB mask for AM, OR2[0:7] = 1111 1100 200 * XAM, OR2[17:18] = 11 201 * 9 columns OR2[19-21] = 010 202 * 13 rows OR2[23-25] = 100 203 * EAD set for extra time OR[31] = 1 204 * 205 * 0 4 8 12 16 20 24 28 206 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 207 */ 208 209 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 210 211 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 212 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 213 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 214 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 215 216 /* 217 * Common settings for all Local Bus SDRAM commands. 218 * At run time, either BSMA1516 (for CPU 1.1) 219 * or BSMA1617 (for CPU 1.0) (old) 220 * is OR'ed in too. 221 */ 222 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 223 | LSDMR_PRETOACT7 \ 224 | LSDMR_ACTTORW7 \ 225 | LSDMR_BL8 \ 226 | LSDMR_WRC4 \ 227 | LSDMR_CL3 \ 228 | LSDMR_RFEN \ 229 ) 230 231 /* 232 * The CADMUS registers are connected to CS3 on CDS. 233 * The new memory map places CADMUS at 0xf8000000. 234 * 235 * For BR3, need: 236 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 237 * port-size = 8-bits = BR[19:20] = 01 238 * no parity checking = BR[21:22] = 00 239 * GPMC for MSEL = BR[24:26] = 000 240 * Valid = BR[31] = 1 241 * 242 * 0 4 8 12 16 20 24 28 243 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 244 * 245 * For OR3, need: 246 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 247 * disable buffer ctrl OR[19] = 0 248 * CSNT OR[20] = 1 249 * ACS OR[21:22] = 11 250 * XACS OR[23] = 1 251 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 252 * SETA OR[28] = 0 253 * TRLX OR[29] = 1 254 * EHTR OR[30] = 1 255 * EAD extra time OR[31] = 1 256 * 257 * 0 4 8 12 16 20 24 28 258 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 259 */ 260 261 #define CONFIG_FSL_CADMUS 262 263 #define CADMUS_BASE_ADDR 0xf8000000 264 #ifdef CONFIG_PHYS_64BIT 265 #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull 266 #else 267 #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR 268 #endif 269 #define CONFIG_SYS_BR3_PRELIM \ 270 (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V) 271 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 272 273 #define CONFIG_SYS_INIT_RAM_LOCK 1 274 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 275 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 276 277 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 278 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 279 280 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 281 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 282 283 /* Serial Port */ 284 #define CONFIG_SYS_NS16550_SERIAL 285 #define CONFIG_SYS_NS16550_REG_SIZE 1 286 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 287 288 #define CONFIG_SYS_BAUDRATE_TABLE \ 289 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 290 291 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 292 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 293 294 /* 295 * I2C 296 */ 297 #if !CONFIG_IS_ENABLED(DM_I2C) 298 #define CONFIG_SYS_I2C 299 #define CONFIG_SYS_FSL_I2C_SPEED 400000 300 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 301 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 302 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 303 #else 304 #define CONFIG_SYS_SPD_BUS_NUM 0 305 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM 306 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 307 #endif 308 #define CONFIG_SYS_I2C_FSL 309 310 /* EEPROM */ 311 #define CONFIG_ID_EEPROM 312 #define CONFIG_SYS_I2C_EEPROM_CCID 313 #define CONFIG_SYS_ID_EEPROM 314 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 315 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 316 317 /* 318 * General PCI 319 * Memory space is mapped 1-1, but I/O space must start from 0. 320 */ 321 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 322 #ifdef CONFIG_PHYS_64BIT 323 #define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 324 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 325 #else 326 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 327 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 328 #endif 329 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 330 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 331 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 332 #ifdef CONFIG_PHYS_64BIT 333 #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull 334 #else 335 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 336 #endif 337 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 338 339 #ifdef CONFIG_PCIE1 340 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 341 #ifdef CONFIG_PHYS_64BIT 342 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull 343 #else 344 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 345 #endif 346 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 347 #ifdef CONFIG_PHYS_64BIT 348 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull 349 #else 350 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 351 #endif 352 #endif 353 354 /* 355 * RapidIO MMU 356 */ 357 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 358 #ifdef CONFIG_PHYS_64BIT 359 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull 360 #else 361 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 362 #endif 363 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 364 365 #ifdef CONFIG_LEGACY 366 #define BRIDGE_ID 17 367 #define VIA_ID 2 368 #else 369 #define BRIDGE_ID 28 370 #define VIA_ID 4 371 #endif 372 373 #if defined(CONFIG_PCI) 374 375 #if !defined(CONFIG_DM_PCI) 376 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 377 #define CONFIG_PCI_INDIRECT_BRIDGE 1 378 #define CONFIG_SYS_PCIE1_NAME "Slot" 379 #ifdef CONFIG_PHYS_64BIT 380 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 381 #else 382 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 383 #endif 384 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 385 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 386 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 387 #endif 388 389 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 390 391 #endif /* CONFIG_PCI */ 392 393 #if defined(CONFIG_TSEC_ENET) 394 395 #define CONFIG_TSEC1 1 396 #define CONFIG_TSEC1_NAME "eTSEC0" 397 #define CONFIG_TSEC2 1 398 #define CONFIG_TSEC2_NAME "eTSEC1" 399 #define CONFIG_TSEC3 1 400 #define CONFIG_TSEC3_NAME "eTSEC2" 401 #define CONFIG_TSEC4 402 #define CONFIG_TSEC4_NAME "eTSEC3" 403 #undef CONFIG_MPC85XX_FEC 404 405 #define TSEC1_PHY_ADDR 0 406 #define TSEC2_PHY_ADDR 1 407 #define TSEC3_PHY_ADDR 2 408 #define TSEC4_PHY_ADDR 3 409 410 #define TSEC1_PHYIDX 0 411 #define TSEC2_PHYIDX 0 412 #define TSEC3_PHYIDX 0 413 #define TSEC4_PHYIDX 0 414 #define TSEC1_FLAGS TSEC_GIGABIT 415 #define TSEC2_FLAGS TSEC_GIGABIT 416 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 417 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 418 419 /* Options are: eTSEC[0-3] */ 420 #define CONFIG_ETHPRIME "eTSEC0" 421 #endif /* CONFIG_TSEC_ENET */ 422 423 /* 424 * Environment 425 */ 426 427 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 428 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 429 430 /* 431 * BOOTP options 432 */ 433 #define CONFIG_BOOTP_BOOTFILESIZE 434 435 #undef CONFIG_WATCHDOG /* watchdog disabled */ 436 437 /* 438 * Miscellaneous configurable options 439 */ 440 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 441 442 /* 443 * For booting Linux, the board info and command line data 444 * have to be in the first 64 MB of memory, since this is 445 * the maximum mapped by the Linux kernel during initialization. 446 */ 447 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 448 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 449 450 #if defined(CONFIG_CMD_KGDB) 451 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 452 #endif 453 454 /* 455 * Environment Configuration 456 */ 457 #if defined(CONFIG_TSEC_ENET) 458 #define CONFIG_HAS_ETH0 459 #define CONFIG_HAS_ETH1 460 #define CONFIG_HAS_ETH2 461 #define CONFIG_HAS_ETH3 462 #endif 463 464 #define CONFIG_IPADDR 192.168.1.253 465 466 #define CONFIG_HOSTNAME "unknown" 467 #define CONFIG_ROOTPATH "/nfsroot" 468 #define CONFIG_BOOTFILE "8548cds/uImage.uboot" 469 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ 470 471 #define CONFIG_SERVERIP 192.168.1.1 472 #define CONFIG_GATEWAYIP 192.168.1.1 473 #define CONFIG_NETMASK 255.255.255.0 474 475 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 476 477 #define CONFIG_EXTRA_ENV_SETTINGS \ 478 "hwconfig=fsl_ddr:ecc=off\0" \ 479 "netdev=eth0\0" \ 480 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 481 "tftpflash=tftpboot $loadaddr $uboot; " \ 482 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 483 " +$filesize; " \ 484 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 485 " +$filesize; " \ 486 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 487 " $filesize; " \ 488 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 489 " +$filesize; " \ 490 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 491 " $filesize\0" \ 492 "consoledev=ttyS1\0" \ 493 "ramdiskaddr=2000000\0" \ 494 "ramdiskfile=ramdisk.uboot\0" \ 495 "fdtaddr=1e00000\0" \ 496 "fdtfile=mpc8548cds.dtb\0" 497 498 #define CONFIG_NFSBOOTCOMMAND \ 499 "setenv bootargs root=/dev/nfs rw " \ 500 "nfsroot=$serverip:$rootpath " \ 501 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 502 "console=$consoledev,$baudrate $othbootargs;" \ 503 "tftp $loadaddr $bootfile;" \ 504 "tftp $fdtaddr $fdtfile;" \ 505 "bootm $loadaddr - $fdtaddr" 506 507 #define CONFIG_RAMBOOTCOMMAND \ 508 "setenv bootargs root=/dev/ram rw " \ 509 "console=$consoledev,$baudrate $othbootargs;" \ 510 "tftp $ramdiskaddr $ramdiskfile;" \ 511 "tftp $loadaddr $bootfile;" \ 512 "tftp $fdtaddr $fdtfile;" \ 513 "bootm $loadaddr $ramdiskaddr $fdtaddr" 514 515 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 516 517 #endif /* __CONFIG_H */ 518