1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2019 MediaTek Inc. 4 */ 5 6 #ifndef _DT_BINDINGS_CLK_MT8512_H 7 #define _DT_BINDINGS_CLK_MT8512_H 8 9 /* TOPCKGEN */ 10 11 #define CLK_TOP_CLK_NULL 0 12 #define CLK_TOP_CLK32K 1 13 #define CLK_TOP_SYSPLL1_D2 2 14 #define CLK_TOP_SYSPLL1_D4 3 15 #define CLK_TOP_SYSPLL1_D8 4 16 #define CLK_TOP_SYSPLL1_D16 5 17 #define CLK_TOP_SYSPLL_D3 6 18 #define CLK_TOP_SYSPLL2_D2 7 19 #define CLK_TOP_SYSPLL2_D4 8 20 #define CLK_TOP_SYSPLL2_D8 9 21 #define CLK_TOP_SYSPLL_D5 10 22 #define CLK_TOP_SYSPLL3_D4 11 23 #define CLK_TOP_SYSPLL_D7 12 24 #define CLK_TOP_SYSPLL4_D2 13 25 #define CLK_TOP_UNIVPLL 14 26 #define CLK_TOP_UNIVPLL_D2 15 27 #define CLK_TOP_UNIVPLL1_D2 16 28 #define CLK_TOP_UNIVPLL1_D4 17 29 #define CLK_TOP_UNIVPLL1_D8 18 30 #define CLK_TOP_UNIVPLL_D3 19 31 #define CLK_TOP_UNIVPLL2_D2 20 32 #define CLK_TOP_UNIVPLL2_D4 21 33 #define CLK_TOP_UNIVPLL2_D8 22 34 #define CLK_TOP_UNIVPLL_D5 23 35 #define CLK_TOP_UNIVPLL3_D2 24 36 #define CLK_TOP_UNIVPLL3_D4 25 37 #define CLK_TOP_TCONPLL_D2 26 38 #define CLK_TOP_TCONPLL_D4 27 39 #define CLK_TOP_TCONPLL_D8 28 40 #define CLK_TOP_TCONPLL_D16 29 41 #define CLK_TOP_TCONPLL_D32 30 42 #define CLK_TOP_TCONPLL_D64 31 43 #define CLK_TOP_USB20_192M 32 44 #define CLK_TOP_USB20_192M_D2 33 45 #define CLK_TOP_USB20_192M_D4_T 34 46 #define CLK_TOP_APLL1 35 47 #define CLK_TOP_APLL1_D2 36 48 #define CLK_TOP_APLL1_D3 37 49 #define CLK_TOP_APLL1_D4 38 50 #define CLK_TOP_APLL1_D8 39 51 #define CLK_TOP_APLL1_D16 40 52 #define CLK_TOP_APLL2 41 53 #define CLK_TOP_APLL2_D2 42 54 #define CLK_TOP_APLL2_D3 43 55 #define CLK_TOP_APLL2_D4 44 56 #define CLK_TOP_APLL2_D8 45 57 #define CLK_TOP_APLL2_D16 46 58 #define CLK_TOP_CLK26M 47 59 #define CLK_TOP_SYS_26M_D2 48 60 #define CLK_TOP_MSDCPLL 49 61 #define CLK_TOP_MSDCPLL_D2 50 62 #define CLK_TOP_DSPPLL 51 63 #define CLK_TOP_DSPPLL_D2 52 64 #define CLK_TOP_DSPPLL_D4 53 65 #define CLK_TOP_DSPPLL_D8 54 66 #define CLK_TOP_IPPLL 55 67 #define CLK_TOP_IPPLL_D2 56 68 #define CLK_TOP_NFI2X_CK_D2 57 69 #define CLK_TOP_AXI_SEL 58 70 #define CLK_TOP_MEM_SEL 59 71 #define CLK_TOP_UART_SEL 60 72 #define CLK_TOP_SPI_SEL 61 73 #define CLK_TOP_SPIS_SEL 62 74 #define CLK_TOP_MSDC50_0_HC_SEL 63 75 #define CLK_TOP_MSDC2_2_HC_SEL 64 76 #define CLK_TOP_MSDC50_0_SEL 65 77 #define CLK_TOP_MSDC50_2_SEL 66 78 #define CLK_TOP_MSDC30_1_SEL 67 79 #define CLK_TOP_AUDIO_SEL 68 80 #define CLK_TOP_AUD_INTBUS_SEL 69 81 #define CLK_TOP_HAPLL1_SEL 70 82 #define CLK_TOP_HAPLL2_SEL 71 83 #define CLK_TOP_A2SYS_SEL 72 84 #define CLK_TOP_A1SYS_SEL 73 85 #define CLK_TOP_ASM_L_SEL 74 86 #define CLK_TOP_ASM_M_SEL 75 87 #define CLK_TOP_ASM_H_SEL 76 88 #define CLK_TOP_AUD_SPDIF_SEL 77 89 #define CLK_TOP_AUD_1_SEL 78 90 #define CLK_TOP_AUD_2_SEL 79 91 #define CLK_TOP_SSUSB_SYS_SEL 80 92 #define CLK_TOP_SSUSB_XHCI_SEL 81 93 #define CLK_TOP_SPM_SEL 82 94 #define CLK_TOP_I2C_SEL 83 95 #define CLK_TOP_PWM_SEL 84 96 #define CLK_TOP_DSP_SEL 85 97 #define CLK_TOP_NFI2X_SEL 86 98 #define CLK_TOP_SPINFI_SEL 87 99 #define CLK_TOP_ECC_SEL 88 100 #define CLK_TOP_GCPU_SEL 89 101 #define CLK_TOP_GCPU_CPM_SEL 90 102 #define CLK_TOP_MBIST_DIAG_SEL 91 103 #define CLK_TOP_IP0_NNA_SEL 92 104 #define CLK_TOP_IP1_NNA_SEL 93 105 #define CLK_TOP_IP2_WFST_SEL 94 106 #define CLK_TOP_SFLASH_SEL 95 107 #define CLK_TOP_SRAM_SEL 96 108 #define CLK_TOP_MM_SEL 97 109 #define CLK_TOP_DPI0_SEL 98 110 #define CLK_TOP_DBG_ATCLK_SEL 99 111 #define CLK_TOP_OCC_104M_SEL 100 112 #define CLK_TOP_OCC_68M_SEL 101 113 #define CLK_TOP_OCC_182M_SEL 102 114 115 /* TOPCKGEN Gates */ 116 #define CLK_TOP_CONN_32K 0 117 #define CLK_TOP_CONN_26M 1 118 #define CLK_TOP_DSP_32K 2 119 #define CLK_TOP_DSP_26M 3 120 #define CLK_TOP_USB20_48M_EN 4 121 #define CLK_TOP_UNIVPLL_48M_EN 5 122 #define CLK_TOP_SSUSB_TOP_CK_EN 6 123 #define CLK_TOP_SSUSB_PHY_CK_EN 7 124 #define CLK_TOP_I2SI1_MCK 8 125 #define CLK_TOP_TDMIN_MCK 9 126 #define CLK_TOP_I2SO1_MCK 10 127 128 /* INFRASYS */ 129 130 #define CLK_INFRA_DSP_AXI 0 131 #define CLK_INFRA_APXGPT 1 132 #define CLK_INFRA_ICUSB 2 133 #define CLK_INFRA_GCE 3 134 #define CLK_INFRA_THERM 4 135 #define CLK_INFRA_PWM_HCLK 5 136 #define CLK_INFRA_PWM1 6 137 #define CLK_INFRA_PWM2 7 138 #define CLK_INFRA_PWM3 8 139 #define CLK_INFRA_PWM4 9 140 #define CLK_INFRA_PWM5 10 141 #define CLK_INFRA_PWM 11 142 #define CLK_INFRA_UART0 12 143 #define CLK_INFRA_UART1 13 144 #define CLK_INFRA_UART2 14 145 #define CLK_INFRA_DSP_UART 15 146 #define CLK_INFRA_GCE_26M 16 147 #define CLK_INFRA_CQDMA_FPC 17 148 #define CLK_INFRA_BTIF 18 149 #define CLK_INFRA_SPI 19 150 #define CLK_INFRA_MSDC0 20 151 #define CLK_INFRA_MSDC1 21 152 #define CLK_INFRA_DVFSRC 22 153 #define CLK_INFRA_GCPU 23 154 #define CLK_INFRA_TRNG 24 155 #define CLK_INFRA_AUXADC 25 156 #define CLK_INFRA_AUXADC_MD 26 157 #define CLK_INFRA_AP_DMA 27 158 #define CLK_INFRA_DEBUGSYS 28 159 #define CLK_INFRA_AUDIO 29 160 #define CLK_INFRA_FLASHIF 30 161 #define CLK_INFRA_PWM_FB6 31 162 #define CLK_INFRA_PWM_FB7 32 163 #define CLK_INFRA_AUD_ASRC 33 164 #define CLK_INFRA_AUD_26M 34 165 #define CLK_INFRA_SPIS 35 166 #define CLK_INFRA_CQ_DMA 36 167 #define CLK_INFRA_AP_MSDC0 37 168 #define CLK_INFRA_MD_MSDC0 38 169 #define CLK_INFRA_MSDC0_SRC 39 170 #define CLK_INFRA_MSDC1_SRC 40 171 #define CLK_INFRA_IRRX_26M 41 172 #define CLK_INFRA_IRRX_32K 42 173 #define CLK_INFRA_I2C0_AXI 43 174 #define CLK_INFRA_I2C1_AXI 44 175 #define CLK_INFRA_I2C2_AXI 45 176 #define CLK_INFRA_NFI 46 177 #define CLK_INFRA_NFIECC 47 178 #define CLK_INFRA_NFI_HCLK 48 179 #define CLK_INFRA_SUSB_133 49 180 #define CLK_INFRA_USB_SYS 50 181 #define CLK_INFRA_USB_XHCI 51 182 #define CLK_INFRA_NR_CLK 52 183 184 /* APMIXEDSYS */ 185 186 #define CLK_APMIXED_ARMPLL 0 187 #define CLK_APMIXED_MAINPLL 1 188 #define CLK_APMIXED_UNIVPLL2 2 189 #define CLK_APMIXED_MSDCPLL 3 190 #define CLK_APMIXED_APLL1 4 191 #define CLK_APMIXED_APLL2 5 192 #define CLK_APMIXED_IPPLL 6 193 #define CLK_APMIXED_DSPPLL 7 194 #define CLK_APMIXED_TCONPLL 8 195 #define CLK_APMIXED_NR_CLK 9 196 197 #endif /* _DT_BINDINGS_CLK_MT8512_H */ 198