1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * UniPhier SG (SoC Glue) block registers
4  *
5  * Copyright (C) 2011-2015 Copyright (C) 2011-2015 Panasonic Corporation
6  * Copyright (C) 2016-2017 Socionext Inc.
7  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8  */
9 
10 #ifndef UNIPHIER_SG_REGS_H
11 #define UNIPHIER_SG_REGS_H
12 
13 #include <linux/bitops.h>
14 
15 #ifndef __ASSEMBLY__
16 #include <linux/compiler.h>
17 #ifdef CONFIG_ARCH_UNIPHIER_V8_MULTI
18 extern void __iomem *sg_base;
19 #else
20 #define sg_base			((void __iomem *)SG_BASE)
21 #endif
22 #endif /* __ASSEMBLY__ */
23 
24 /* Base Address */
25 #define SG_BASE			0x5f800000
26 
27 /* Revision */
28 #define SG_REVISION		0x0000
29 #define   SG_REVISION_TYPE_MASK		GENMASK(23, 16)
30 #define   SG_REVISION_MODEL_MASK	GENMASK(10, 8)
31 #define   SG_REVISION_REV_MASK		GENMASK(4, 0)
32 
33 /* Memory Configuration */
34 #define SG_MEMCONF		0x0400
35 
36 #define SG_MEMCONF_CH0_SZ_MASK		((0x1 << 10) | (0x03 << 0))
37 #define SG_MEMCONF_CH0_SZ_64M		((0x0 << 10) | (0x01 << 0))
38 #define SG_MEMCONF_CH0_SZ_128M		((0x0 << 10) | (0x02 << 0))
39 #define SG_MEMCONF_CH0_SZ_256M		((0x0 << 10) | (0x03 << 0))
40 #define SG_MEMCONF_CH0_SZ_512M		((0x1 << 10) | (0x00 << 0))
41 #define SG_MEMCONF_CH0_SZ_1G		((0x1 << 10) | (0x01 << 0))
42 #define SG_MEMCONF_CH0_NUM_MASK		(0x1 << 8)
43 #define SG_MEMCONF_CH0_NUM_1		(0x1 << 8)
44 #define SG_MEMCONF_CH0_NUM_2		(0x0 << 8)
45 
46 #define SG_MEMCONF_CH1_SZ_MASK		((0x1 << 11) | (0x03 << 2))
47 #define SG_MEMCONF_CH1_SZ_64M		((0x0 << 11) | (0x01 << 2))
48 #define SG_MEMCONF_CH1_SZ_128M		((0x0 << 11) | (0x02 << 2))
49 #define SG_MEMCONF_CH1_SZ_256M		((0x0 << 11) | (0x03 << 2))
50 #define SG_MEMCONF_CH1_SZ_512M		((0x1 << 11) | (0x00 << 2))
51 #define SG_MEMCONF_CH1_SZ_1G		((0x1 << 11) | (0x01 << 2))
52 #define SG_MEMCONF_CH1_NUM_MASK		(0x1 << 9)
53 #define SG_MEMCONF_CH1_NUM_1		(0x1 << 9)
54 #define SG_MEMCONF_CH1_NUM_2		(0x0 << 9)
55 
56 #define SG_MEMCONF_CH2_SZ_MASK		((0x1 << 26) | (0x03 << 16))
57 #define SG_MEMCONF_CH2_SZ_64M		((0x0 << 26) | (0x01 << 16))
58 #define SG_MEMCONF_CH2_SZ_128M		((0x0 << 26) | (0x02 << 16))
59 #define SG_MEMCONF_CH2_SZ_256M		((0x0 << 26) | (0x03 << 16))
60 #define SG_MEMCONF_CH2_SZ_512M		((0x1 << 26) | (0x00 << 16))
61 #define SG_MEMCONF_CH2_SZ_1G		((0x1 << 26) | (0x01 << 16))
62 #define SG_MEMCONF_CH2_NUM_MASK		(0x1 << 24)
63 #define SG_MEMCONF_CH2_NUM_1		(0x1 << 24)
64 #define SG_MEMCONF_CH2_NUM_2		(0x0 << 24)
65 /* PH1-LD6b, ProXstream2, PH1-LD20 only */
66 #define SG_MEMCONF_CH2_DISABLE		(0x1 << 21)
67 
68 #define SG_MEMCONF_SPARSEMEM		(0x1 << 4)
69 
70 #define SG_USBPHYCTRL		0x0500
71 #define SG_ETPHYPSHUT		0x0554
72 #define SG_ETPHYCNT		0x0550
73 
74 /* Pin Control */
75 #define SG_PINCTRL_BASE		0x1000
76 
77 /* PH1-Pro4, PH1-Pro5 */
78 #define SG_LOADPINCTRL		0x1700
79 
80 /* Input Enable */
81 #define SG_IECTRL		0x1d00
82 
83 /* Pin Monitor */
84 #define SG_PINMON0		0x00100100
85 #define SG_PINMON2		0x00100108
86 
87 #define SG_PINMON0_CLK_MODE_UPLLSRC_MASK	(0x3 << 19)
88 #define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT	(0x0 << 19)
89 #define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A	(0x2 << 19)
90 #define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B	(0x3 << 19)
91 
92 #define SG_PINMON0_CLK_MODE_AXOSEL_MASK		(0x3 << 16)
93 #define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ	(0x0 << 16)
94 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ	(0x1 << 16)
95 #define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ	(0x2 << 16)
96 #define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ	(0x3 << 16)
97 
98 #define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT	(0x0 << 16)
99 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U	(0x1 << 16)
100 #define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ	(0x2 << 16)
101 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A	(0x3 << 16)
102 
103 #endif /* UNIPHIER_SG_REGS_H */
104