1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * This file is part of the libpayload project. 4 * 5 * Copyright (C) 2008 Advanced Micro Devices, Inc. 6 */ 7 8 #ifndef _COREBOOT_SYSINFO_H 9 #define _COREBOOT_SYSINFO_H 10 11 #include <asm/coreboot_tables.h> 12 13 /* Maximum number of memory range definitions */ 14 #define SYSINFO_MAX_MEM_RANGES 32 15 /* Allow a maximum of 8 GPIOs */ 16 #define SYSINFO_MAX_GPIOS 8 17 /* Up to 10 MAC addresses */ 18 #define SYSINFO_MAX_MACS 10 19 20 /** 21 * struct sysinfo_t - Information passed to U-Boot from coreboot 22 * 23 * Coreboot passes on a lot of information using a list of individual data 24 * structures identified by a numeric tag. These are parsed in U-Boot to produce 25 * this struct. Some of the pointers here point back to the tagged data 26 * structure, since it is assumed to remain around while U-Boot is running. 27 * 28 * The 'cbsysinfo' command can display this information. 29 * 30 * @cpu_khz: CPU frequence in KHz (e.g. 1100000) 31 * @serial: Pointer to the serial information, NULL if none 32 * @ser_ioport: Not actually provided by a tag and not used on modern hardware, 33 * which typicaally uses a memory-mapped port 34 * @ser_base: Not used at all, but present to match up with the coreboot data 35 * structure 36 * @n_memranges: Number of memory ranges 37 * @memrange: List of memory ranges: 38 * @base: Base address of range 39 * @size: Size of range in bytes 40 * @type: Type of range (CB_MEM_RAM, etc.) 41 * @option_table: Provides a pointer to the CMOS RAM options table, which 42 * indicates which options are available. The header is followed by a list 43 * of struct cb_cmos_entries records, so that an option can be found from 44 * its name. This is not used in U-Boot. NULL if not present 45 * @cmos_range_start: Start bit of the CMOS checksum range (in fact this must 46 * be a multiple of 8) 47 * @cmos_range_end: End bit of the CMOS checksum range (multiple of 8). This is 48 * the inclusive end. 49 * @cmos_checksum_location: Location of checksum, multiplied by 8. This is the 50 * byte offset into the CMOS RAM of the first checksum byte. The second one 51 * follows immediately. The checksum is a simple 16-bit sum of all the 52 * bytes from offset cmos_range_start / 8 to cmos_range_end / 8, inclusive, 53 * in big-endian format (so sum >> 8 is stored in the first byte). 54 * @vbnv_start: Start offset of CMOS RAM used for Chromium OS verified boot 55 * (typically 0x34) 56 * @vbnv_size: Number of bytes used by Chromium OS verified boot (typically 57 * 0x10) 58 * @extra_version: Extra version information, typically "" 59 * @build: Build date, e.g. "Wed Nov 18 02:51:58 UTC 2020" 60 * @compile_time: Compilation time, e.g. "02:51:58" 61 * @compile_by: Who compiled coreboot (never set?) 62 * @compile_host: Name of the machine that compiled coreboot (never set?) 63 * @compile_domain: Domain name of the machine that compiled coreboot (never 64 * set?) 65 * @compiler: Name of the compiler used to build coreboot (never set?) 66 * @linker: Name of the linker used to build coreboot (never set?) 67 * @assembler: Name of the assembler used to build coreboot (never set?) 68 * @cb_version: Coreboot version string, e.g. v1.9308_26_0.0.22-2599-g232f22c75d 69 * @framebuffer: Address of framebuffer tag, or NULL if none. See 70 * struct cb_framebuffer for the definition 71 * @num_gpios: Number of verified-boot GPIOs 72 * @gpios: List of GPIOs: 73 * @port: GPIO number, or 0xffffffff if not a GPIO 74 * @polarity: CB_GPIO_ACTIVE_LOW or CB_GPIO_ACTIVE_HIGH 75 * @value: Value of GPIO (0 or 1) 76 * @name: Name of GPIO 77 * 78 * A typical list is: 79 * id: port polarity val name 80 * 0: - active-high 1 write protect 81 * 1: - active-high 0 recovery 82 * 2: - active-high 1 lid 83 * 3: - active-high 0 power 84 * 4: - active-high 0 oprom 85 * 5: 29 active-high 0 EC in RW 86 * 87 * @num_macs: Number of MAC addresses 88 * @macs: List of MAC addresses 89 * @serialno: Serial number, or NULL (never set?) 90 * @mbtable: Address of the multiboot table, or NULL. This is a 91 * struct multiboot_header, not used in U-Boot 92 * @header: Address of header, if there is a CB_TAG_FORWARD, else NULL 93 * @mainboard: Pointer to mainboard info or NULL. Typically the vendor is 94 * "Google" and the part number is "" 95 * @vboot_handoff: Pointer to Chromium OS verified boot hand-off information. 96 * This is struct vboot_handoff, providing access to internal information 97 * generated by coreboot when this is being used 98 * @vboot_handoff_size: Size of hand-off information (typically 0xc0c) 99 * @vdat_addr: Pointer to Chromium OS verified boot data, which uses 100 * struct chromeos_acpi. It sits in the Intel Global NVS struct, after the 101 * first 0x100 bytes 102 * @vdat_size: Size of this data, typically 0xf00 103 * @smbios_start: Address of SMBIOS tables 104 * @smbios_size: Size of SMBIOS tables (e.g. 0x800) 105 * @x86_rom_var_mtrr_index: MTRR number used for ROM caching. Not used in U-Boot 106 * @tstamp_table: Pointer to timestamp_table, struct timestamp_table 107 * @cbmem_cons: Pointer to the console dump, struct cbmem_console. This provides 108 * access to the console output generated by coreboot, typically about 64KB 109 * and mostly PCI enumeration info 110 * @mrc_cache: Pointer to memory-reference-code cache, typically NULL 111 * acpi_gnvs: @Pointer to Intel Global NVS struct, see struct acpi_global_nvs 112 * @board_id: Board ID indicating the board variant, typically 0xffffffff 113 * @ram_code: RAM code indicating the SDRAM type, typically 0xffffffff 114 * @wifi_calibration: WiFi calibration info, NULL if none 115 * @ramoops_buffer: Address of kernel Ramoops buffer 116 * @ramoops_buffer_size: Sizeof of Ramoops buffer, typically 1MB 117 * @spi_flash: Information about SPI flash: 118 * @size: Size in bytes, e.g. 16MB 119 * @sector_size; Sector size of flash device, e.g. 4KB 120 * @erase_cmd: Command used to erase flash, or 0 if not used 121 * @fmap_offset: SPI-flash offset of the flash map (FMAP) table. This has a 122 * __FMAP__ header. It provides information about the different top-level 123 * sections in the SPI flash, e.g. 0x204000 124 * @cbfs_offset: SPI-flash offset of the Coreboot Filesystem (CBFS) used for 125 * read-only data, e.g. 0x205000. This is typically called 'COREBOOT' in 126 * the flash map. It holds various coreboot binaries as well as 127 * video-configuration files and graphics data for the Chromium OS 128 * verified boot user interface. 129 * @cbfs_size: Size of CBFS, e.g. 0x17b000 130 * @boot_media_size; Size of boot media (i.e. SPI flash), e.g. 16MB 131 * @mtc_start; Start of MTC region (Nvidia private data), 0 if not used. See 132 * https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/nvidia/tegra210/mtc.c 133 * @mtc_size: Size of MTC region 134 * @chromeos_vpd: Chromium OS Vital Product Data region, typically NULL, meaning 135 * not used 136 */ 137 struct sysinfo_t { 138 unsigned int cpu_khz; 139 struct cb_serial *serial; 140 unsigned short ser_ioport; 141 unsigned long ser_base; // for mmapped serial 142 143 int n_memranges; 144 145 struct memrange { 146 unsigned long long base; 147 unsigned long long size; 148 unsigned int type; 149 } memrange[SYSINFO_MAX_MEM_RANGES]; 150 151 struct cb_cmos_option_table *option_table; 152 u32 cmos_range_start; 153 u32 cmos_range_end; 154 u32 cmos_checksum_location; 155 u32 vbnv_start; 156 u32 vbnv_size; 157 158 char *version; 159 char *extra_version; 160 char *build; 161 char *compile_time; 162 char *compile_by; 163 char *compile_host; 164 char *compile_domain; 165 char *compiler; 166 char *linker; 167 char *assembler; 168 169 char *cb_version; 170 171 struct cb_framebuffer *framebuffer; 172 173 int num_gpios; 174 struct cb_gpio gpios[SYSINFO_MAX_GPIOS]; 175 int num_macs; 176 struct mac_address macs[SYSINFO_MAX_MACS]; 177 char *serialno; 178 179 unsigned long *mbtable; /** Pointer to the multiboot table */ 180 181 struct cb_header *header; 182 struct cb_mainboard *mainboard; 183 184 void *vboot_handoff; 185 u32 vboot_handoff_size; 186 void *vdat_addr; 187 u32 vdat_size; 188 u64 smbios_start; 189 u32 smbios_size; 190 191 int x86_rom_var_mtrr_index; 192 193 void *tstamp_table; 194 void *cbmem_cons; 195 void *mrc_cache; 196 void *acpi_gnvs; 197 u32 board_id; 198 u32 ram_code; 199 void *wifi_calibration; 200 u64 ramoops_buffer; 201 u32 ramoops_buffer_size; 202 struct { 203 u32 size; 204 u32 sector_size; 205 u32 erase_cmd; 206 } spi_flash; 207 u64 fmap_offset; 208 u64 cbfs_offset; 209 u64 cbfs_size; 210 u64 boot_media_size; 211 u64 mtc_start; 212 u32 mtc_size; 213 void *chromeos_vpd; 214 }; 215 216 extern struct sysinfo_t lib_sysinfo; 217 218 int get_coreboot_info(struct sysinfo_t *info); 219 220 #endif 221