1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
4 * Copyright 2020 NXP
5 */
6
7 #include <common.h>
8 #include <command.h>
9 #include <env.h>
10 #include <hang.h>
11 #include <hwconfig.h>
12 #include <image.h>
13 #include <init.h>
14 #include <net.h>
15 #include <pci.h>
16 #include <i2c.h>
17 #include <asm/processor.h>
18 #include <asm/mmu.h>
19 #include <asm/cache.h>
20 #include <asm/immap_85xx.h>
21 #include <asm/fsl_pci.h>
22 #include <fsl_ddr_sdram.h>
23 #include <asm/io.h>
24 #include <asm/fsl_law.h>
25 #include <asm/fsl_lbc.h>
26 #include <asm/mp.h>
27 #include <miiphy.h>
28 #include <linux/delay.h>
29 #include <linux/libfdt.h>
30 #include <fdt_support.h>
31 #include <fsl_mdio.h>
32 #include <tsec.h>
33 #include <vsc7385.h>
34 #include <ioports.h>
35 #include <asm/fsl_serdes.h>
36 #include <netdev.h>
37
38 #ifdef CONFIG_QE
39
40 #define GPIO_GETH_SW_PORT 1
41 #define GPIO_GETH_SW_PIN 29
42 #define GPIO_GETH_SW_DATA (1 << (31 - GPIO_GETH_SW_PIN))
43
44 #define GPIO_SLIC_PORT 1
45 #define GPIO_SLIC_PIN 30
46 #define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN))
47
48 const qe_iop_conf_t qe_iop_conf_tab[] = {
49 /* GPIO */
50 {1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */
51 {0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */
52 {GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */
53 {GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0}, /* RST_SLIC_N */
54 {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
55 };
56 #endif
57
58 struct cpld_data {
59 u8 cpld_rev_major;
60 u8 pcba_rev;
61 u8 wd_cfg;
62 u8 rst_bps_sw;
63 u8 load_default_n;
64 u8 rst_bps_wd;
65 u8 bypass_enable;
66 u8 bps_led;
67 u8 status_led; /* offset: 0x8 */
68 u8 fxo_led; /* offset: 0x9 */
69 u8 fxs_led; /* offset: 0xa */
70 u8 rev4[2];
71 u8 system_rst; /* offset: 0xd */
72 u8 bps_out;
73 u8 rev5[3];
74 u8 cpld_rev_minor;
75 };
76
77 #define CPLD_WD_CFG 0x03
78 #define CPLD_RST_BSW 0x00
79 #define CPLD_RST_BWD 0x00
80 #define CPLD_BYPASS_EN 0x03
81 #define CPLD_STATUS_LED 0x01
82 #define CPLD_FXO_LED 0x01
83 #define CPLD_FXS_LED 0x0F
84 #define CPLD_SYS_RST 0x00
85
board_cpld_init(void)86 void board_cpld_init(void)
87 {
88 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
89
90 out_8(&cpld_data->wd_cfg, CPLD_WD_CFG);
91 out_8(&cpld_data->status_led, CPLD_STATUS_LED);
92 out_8(&cpld_data->fxo_led, CPLD_FXO_LED);
93 out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
94 out_8(&cpld_data->system_rst, CPLD_SYS_RST);
95 }
96
board_gpio_init(void)97 void board_gpio_init(void)
98 {
99 #ifdef CONFIG_QE
100 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
101 par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
102
103 /* Enable VSC7385 switch */
104 setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA);
105
106 /* Enable SLIC */
107 setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA);
108 #else
109
110 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
111
112 /*
113 * GPIO10 DDR Reset, open drain
114 * GPIO7 LOAD_DEFAULT_N Input
115 * GPIO11 WDI (watchdog input)
116 * GPIO12 Ethernet Switch Reset
117 * GPIO13 SLIC Reset
118 */
119
120 setbits_be32(&pgpio->gpdir, 0x02130000);
121 #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
122 /* init DDR3 reset signal */
123 setbits_be32(&pgpio->gpdir, 0x00200000);
124 setbits_be32(&pgpio->gpodr, 0x00200000);
125 clrbits_be32(&pgpio->gpdat, 0x00200000);
126 udelay(1000);
127 setbits_be32(&pgpio->gpdat, 0x00200000);
128 udelay(1000);
129 clrbits_be32(&pgpio->gpdir, 0x00200000);
130 #endif
131
132 #ifdef CONFIG_VSC7385_ENET
133 /* reset VSC7385 Switch */
134 setbits_be32(&pgpio->gpdir, 0x00080000);
135 setbits_be32(&pgpio->gpdat, 0x00080000);
136 #endif
137
138 #ifdef CONFIG_SLIC
139 /* reset SLIC */
140 setbits_be32(&pgpio->gpdir, 0x00040000);
141 setbits_be32(&pgpio->gpdat, 0x00040000);
142 #endif
143 #endif
144 }
145
board_early_init_f(void)146 int board_early_init_f(void)
147 {
148 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
149
150 setbits_be32(&gur->pmuxcr,
151 (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
152 clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV);
153
154 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
155 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA);
156
157 board_gpio_init();
158 board_cpld_init();
159
160 return 0;
161 }
162
checkboard(void)163 int checkboard(void)
164 {
165 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
166 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
167 u8 in, out, io_config, val;
168 int bus_num = CONFIG_SYS_SPD_BUS_NUM;
169
170 printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME,
171 in_8(&cpld_data->cpld_rev_major) & 0x0F,
172 in_8(&cpld_data->cpld_rev_minor) & 0x0F,
173 in_8(&cpld_data->pcba_rev) & 0x0F);
174
175 /* Initialize i2c early for rom_loc and flash bank information */
176 #if CONFIG_IS_ENABLED(DM_I2C)
177 struct udevice *dev;
178 int ret;
179
180 ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_PCA9557_ADDR,
181 1, &dev);
182 if (ret) {
183 printf("%s: Cannot find udev for a bus %d\n", __func__,
184 bus_num);
185 return -ENXIO;
186 }
187
188 if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
189 dm_i2c_read(dev, 1, &out, 1) < 0 ||
190 dm_i2c_read(dev, 3, &io_config, 1) < 0) {
191 printf("Error reading i2c boot information!\n");
192 return 0; /* Don't want to hang() on this error */
193 }
194 #else /* Non DM I2C support - will be removed */
195 i2c_set_bus_num(bus_num);
196
197 if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
198 i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
199 i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
200 printf("Error reading i2c boot information!\n");
201 return 0; /* Don't want to hang() on this error */
202 }
203 #endif
204
205 val = (in & io_config) | (out & (~io_config));
206
207 puts("rom_loc: ");
208 if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
209 puts("sd");
210 #ifdef __SW_BOOT_SPI
211 } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) {
212 puts("spi");
213 #endif
214 #ifdef __SW_BOOT_NAND
215 } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_NAND) {
216 puts("nand");
217 #endif
218 #ifdef __SW_BOOT_PCIE
219 } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_PCIE) {
220 puts("pcie");
221 #endif
222 } else {
223 if (val & 0x2)
224 puts("nor lower bank");
225 else
226 puts("nor upper bank");
227 }
228 puts("\n");
229
230 if (val & 0x1) {
231 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
232 puts("SD/MMC : 8-bit Mode\n");
233 puts("eSPI : Disabled\n");
234 } else {
235 puts("SD/MMC : 4-bit Mode\n");
236 puts("eSPI : Enabled\n");
237 }
238
239 return 0;
240 }
241
242 #if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
pci_init_board(void)243 void pci_init_board(void)
244 {
245 fsl_pcie_init_board(0);
246 }
247 #endif
248
board_early_init_r(void)249 int board_early_init_r(void)
250 {
251 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
252 int flash_esel = find_tlb_idx((void *)flashbase, 1);
253 #ifdef CONFIG_VSC7385_ENET
254 unsigned int vscfw_addr;
255 char *tmp;
256 #endif
257
258 /*
259 * Remap Boot flash region to caching-inhibited
260 * so that flash can be erased properly.
261 */
262
263 /* Flush d-cache and invalidate i-cache of any FLASH data */
264 flush_dcache();
265 invalidate_icache();
266
267 if (flash_esel == -1) {
268 /* very unlikely unless something is messed up */
269 puts("Error: Could not find TLB for FLASH BASE\n");
270 flash_esel = 2; /* give our best effort to continue */
271 } else {
272 /* invalidate existing TLB entry for flash */
273 disable_tlb(flash_esel);
274 }
275
276 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
277 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
278 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
279
280 #ifdef CONFIG_VSC7385_ENET
281 /* If a VSC7385 microcode image is present, then upload it. */
282 tmp = env_get("vscfw_addr");
283 if (tmp) {
284 vscfw_addr = simple_strtoul(tmp, NULL, 16);
285 printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
286 if (vsc7385_upload_firmware((void *)vscfw_addr,
287 CONFIG_VSC7385_IMAGE_SIZE))
288 puts("Failure uploading VSC7385 microcode.\n");
289 } else {
290 puts("No address specified for VSC7385 microcode.\n");
291 }
292 #endif
293 return 0;
294 }
295
296 #ifndef CONFIG_DM_ETH
board_eth_init(struct bd_info * bis)297 int board_eth_init(struct bd_info *bis)
298 {
299 struct fsl_pq_mdio_info mdio_info;
300 struct tsec_info_struct tsec_info[4];
301 ccsr_gur_t *gur __attribute__((unused)) =
302 (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
303 int num = 0;
304
305 #ifdef CONFIG_TSEC1
306 SET_STD_TSEC_INFO(tsec_info[num], 1);
307 num++;
308 #endif
309 #ifdef CONFIG_TSEC2
310 SET_STD_TSEC_INFO(tsec_info[num], 2);
311 if (is_serdes_configured(SGMII_TSEC2)) {
312 printf("eTSEC2 is in sgmii mode.\n");
313 tsec_info[num].flags |= TSEC_SGMII;
314 }
315 num++;
316 #endif
317 #ifdef CONFIG_TSEC3
318 SET_STD_TSEC_INFO(tsec_info[num], 3);
319 num++;
320 #endif
321
322 if (!num) {
323 printf("No TSECs initialized\n");
324 return 0;
325 }
326
327 mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1);
328 mdio_info.name = DEFAULT_MII_NAME;
329
330 fsl_pq_mdio_init(bis, &mdio_info);
331
332 tsec_eth_init(bis, tsec_info, num);
333
334 #if defined(CONFIG_UEC_ETH)
335 /* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */
336 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0);
337 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3);
338
339 uec_standard_init(bis);
340 #endif
341
342 return pci_eth_init(bis);
343 }
344 #endif
345
346 #ifdef CONFIG_OF_BOARD_SETUP
ft_board_setup(void * blob,struct bd_info * bd)347 int ft_board_setup(void *blob, struct bd_info *bd)
348 {
349 phys_addr_t base;
350 phys_size_t size;
351 #if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
352 const char *soc_usb_compat = "fsl-usb2-dr";
353 int usb_err, usb1_off, usb2_off;
354 #endif
355 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
356 int err;
357 #endif
358
359 ft_cpu_setup(blob, bd);
360
361 base = env_get_bootm_low();
362 size = env_get_bootm_size();
363
364 fdt_fixup_memory(blob, (u64)base, (u64)size);
365
366 #if !defined(CONFIG_DM_PCI)
367 FT_FSL_PCI_SETUP;
368 #endif
369
370 #ifdef CONFIG_QE
371 do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
372 sizeof("okay"), 0);
373 #endif
374
375 #if defined(CONFIG_HAS_FSL_DR_USB)
376 fsl_fdt_fixup_dr_usb(blob, bd);
377 #endif
378
379 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
380 /* Delete eLBC node as it is muxed with USB2 controller */
381 if (hwconfig("usb2")) {
382 const char *soc_elbc_compat = "fsl,p1020-elbc";
383 int off = fdt_node_offset_by_compatible(blob, -1,
384 soc_elbc_compat);
385 if (off < 0) {
386 printf("WARNING: could not find compatible node %s\n",
387 soc_elbc_compat);
388 return off;
389 }
390 err = fdt_del_node(blob, off);
391 if (err < 0) {
392 printf("WARNING: could not remove %s\n",
393 soc_elbc_compat);
394 return err;
395 }
396 return 0;
397 }
398 #endif
399
400 #if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
401 /* Delete USB2 node as it is muxed with eLBC */
402 usb1_off = fdt_node_offset_by_compatible(blob, -1,
403 soc_usb_compat);
404 if (usb1_off < 0) {
405 printf("WARNING: could not find compatible node %s\n",
406 soc_usb_compat);
407 return usb1_off;
408 }
409 usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
410 soc_usb_compat);
411 if (usb2_off < 0) {
412 printf("WARNING: could not find compatible node %s\n",
413 soc_usb_compat);
414 return usb2_off;
415 }
416 usb_err = fdt_del_node(blob, usb2_off);
417 if (usb_err < 0) {
418 printf("WARNING: could not remove %s\n", soc_usb_compat);
419 return usb_err;
420 }
421 #endif
422
423 return 0;
424 }
425 #endif
426