1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuation settings for the Motorola MC5272C3 board. 4 * 5 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> 6 */ 7 8 /* 9 * board/config.h - configuration options, board specific 10 */ 11 12 #ifndef _M5272C3_H 13 #define _M5272C3_H 14 15 /* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 #define CONFIG_MCFTMR 20 21 #define CONFIG_MCFUART 22 #define CONFIG_SYS_UART_PORT (0) 23 24 #undef CONFIG_WATCHDOG 25 #define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ 26 27 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ 28 29 /* Configuration for environment 30 * Environment is embedded in u-boot in the second sector of the flash 31 */ 32 33 #define LDS_BOARD_TEXT \ 34 . = DEFINED(env_offset) ? env_offset : .; \ 35 env/embedded.o(.text); 36 37 /* 38 * BOOTP options 39 */ 40 #define CONFIG_BOOTP_BOOTFILESIZE 41 42 #ifdef CONFIG_MCFFEC 43 # define CONFIG_MII_INIT 1 44 # define CONFIG_SYS_DISCOVER_PHY 45 # define CONFIG_SYS_RX_ETH_BUFFER 8 46 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 47 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 48 # ifndef CONFIG_SYS_DISCOVER_PHY 49 # define FECDUPLEX FULL 50 # define FECSPEED _100BASET 51 # else 52 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 53 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 54 # endif 55 # endif /* CONFIG_SYS_DISCOVER_PHY */ 56 #endif 57 58 #ifdef CONFIG_MCFFEC 59 # define CONFIG_IPADDR 192.162.1.2 60 # define CONFIG_NETMASK 255.255.255.0 61 # define CONFIG_SERVERIP 192.162.1.1 62 # define CONFIG_GATEWAYIP 192.162.1.1 63 #endif /* CONFIG_MCFFEC */ 64 65 #define CONFIG_HOSTNAME "M5272C3" 66 #define CONFIG_EXTRA_ENV_SETTINGS \ 67 "netdev=eth0\0" \ 68 "loadaddr=10000\0" \ 69 "u-boot=u-boot.bin\0" \ 70 "load=tftp ${loadaddr) ${u-boot}\0" \ 71 "upd=run load; run prog\0" \ 72 "prog=prot off ffe00000 ffe3ffff;" \ 73 "era ffe00000 ffe3ffff;" \ 74 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 75 "save\0" \ 76 "" 77 78 #define CONFIG_SYS_LOAD_ADDR 0x20000 79 #define CONFIG_SYS_CLK 66000000 80 81 /* 82 * Low Level Configuration Settings 83 * (address mappings, register initial values, etc.) 84 * You should know what you are doing if you make changes here. 85 */ 86 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 87 #define CONFIG_SYS_SCR 0x0003 88 #define CONFIG_SYS_SPR 0xffff 89 90 /*----------------------------------------------------------------------- 91 * Definitions for initial stack pointer and data area (in DPRAM) 92 */ 93 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 94 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 95 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 96 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 97 98 /*----------------------------------------------------------------------- 99 * Start addresses for the final memory configuration 100 * (Set up by the startup code) 101 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 102 */ 103 #define CONFIG_SYS_SDRAM_BASE 0x00000000 104 #define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */ 105 #define CONFIG_SYS_FLASH_BASE 0xffe00000 106 107 #ifdef CONFIG_MONITOR_IS_IN_RAM 108 #define CONFIG_SYS_MONITOR_BASE 0x20000 109 #else 110 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 111 #endif 112 113 #define CONFIG_SYS_MONITOR_LEN 0x20000 114 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 115 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 116 117 /* 118 * For booting Linux, the board info and command line data 119 * have to be in the first 8 MB of memory, since this is 120 * the maximum mapped by the Linux kernel during initialization ?? 121 */ 122 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 123 124 /* 125 * FLASH organization 126 */ 127 #ifdef CONFIG_SYS_FLASH_CFI 128 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 129 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 130 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 131 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 132 #endif 133 134 /*----------------------------------------------------------------------- 135 * Cache Configuration 136 */ 137 #define CONFIG_SYS_CACHELINE_SIZE 16 138 139 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 140 CONFIG_SYS_INIT_RAM_SIZE - 8) 141 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 142 CONFIG_SYS_INIT_RAM_SIZE - 4) 143 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 144 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 145 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 146 CF_ACR_EN | CF_ACR_SM_ALL) 147 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 148 CF_CACR_DISD | CF_CACR_INVI | \ 149 CF_CACR_CEIB | CF_CACR_DCM | \ 150 CF_CACR_EUSP) 151 152 /*----------------------------------------------------------------------- 153 * Memory bank definitions 154 */ 155 #define CONFIG_SYS_BR0_PRELIM 0xFFE00201 156 #define CONFIG_SYS_OR0_PRELIM 0xFFE00014 157 #define CONFIG_SYS_BR1_PRELIM 0 158 #define CONFIG_SYS_OR1_PRELIM 0 159 #define CONFIG_SYS_BR2_PRELIM 0x30000001 160 #define CONFIG_SYS_OR2_PRELIM 0xFFF80000 161 #define CONFIG_SYS_BR3_PRELIM 0 162 #define CONFIG_SYS_OR3_PRELIM 0 163 #define CONFIG_SYS_BR4_PRELIM 0 164 #define CONFIG_SYS_OR4_PRELIM 0 165 #define CONFIG_SYS_BR5_PRELIM 0 166 #define CONFIG_SYS_OR5_PRELIM 0 167 #define CONFIG_SYS_BR6_PRELIM 0 168 #define CONFIG_SYS_OR6_PRELIM 0 169 #define CONFIG_SYS_BR7_PRELIM 0x00000701 170 #define CONFIG_SYS_OR7_PRELIM 0xFFC0007C 171 172 /*----------------------------------------------------------------------- 173 * Port configuration 174 */ 175 #define CONFIG_SYS_PACNT 0x00000000 176 #define CONFIG_SYS_PADDR 0x0000 177 #define CONFIG_SYS_PADAT 0x0000 178 #define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */ 179 #define CONFIG_SYS_PBDDR 0x0000 180 #define CONFIG_SYS_PBDAT 0x0000 181 #define CONFIG_SYS_PDCNT 0x00000000 182 #endif /* _M5272C3_H */ 183