1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Freescale i.MX6 PCI Express Root-Complex driver
4 *
5 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
6 *
7 * Based on upstream Linux kernel driver:
8 * pci-imx6.c: Sean Cross <xobs@kosagi.com>
9 * pcie-designware.c: Jingoo Han <jg1.han@samsung.com>
10 */
11
12 #include <common.h>
13 #include <init.h>
14 #include <log.h>
15 #include <malloc.h>
16 #include <pci.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/iomux.h>
19 #include <asm/arch/crm_regs.h>
20 #include <asm/gpio.h>
21 #include <asm/io.h>
22 #include <dm.h>
23 #include <linux/delay.h>
24 #include <linux/sizes.h>
25 #include <errno.h>
26 #include <asm/arch/sys_proto.h>
27
28 #define PCI_ACCESS_READ 0
29 #define PCI_ACCESS_WRITE 1
30
31 #ifdef CONFIG_MX6SX
32 #define MX6_DBI_ADDR 0x08ffc000
33 #define MX6_IO_ADDR 0x08000000
34 #define MX6_MEM_ADDR 0x08100000
35 #define MX6_ROOT_ADDR 0x08f00000
36 #else
37 #define MX6_DBI_ADDR 0x01ffc000
38 #define MX6_IO_ADDR 0x01000000
39 #define MX6_MEM_ADDR 0x01100000
40 #define MX6_ROOT_ADDR 0x01f00000
41 #endif
42 #define MX6_DBI_SIZE 0x4000
43 #define MX6_IO_SIZE 0x100000
44 #define MX6_MEM_SIZE 0xe00000
45 #define MX6_ROOT_SIZE 0xfc000
46
47 /* PCIe Port Logic registers (memory-mapped) */
48 #define PL_OFFSET 0x700
49 #define PCIE_PL_PFLR (PL_OFFSET + 0x08)
50 #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
51 #define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
52 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
53 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
54 #define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4)
55 #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (1 << 29)
56
57 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
58 #define PCIE_PHY_CTRL_DATA_LOC 0
59 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
60 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17
61 #define PCIE_PHY_CTRL_WR_LOC 18
62 #define PCIE_PHY_CTRL_RD_LOC 19
63
64 #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
65 #define PCIE_PHY_STAT_DATA_LOC 0
66 #define PCIE_PHY_STAT_ACK_LOC 16
67
68 /* PHY registers (not memory-mapped) */
69 #define PCIE_PHY_RX_ASIC_OUT 0x100D
70
71 #define PHY_RX_OVRD_IN_LO 0x1005
72 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
73 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
74
75 #define PCIE_PHY_PUP_REQ (1 << 7)
76
77 /* iATU registers */
78 #define PCIE_ATU_VIEWPORT 0x900
79 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
80 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
81 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
82 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
83 #define PCIE_ATU_CR1 0x904
84 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
85 #define PCIE_ATU_TYPE_IO (0x2 << 0)
86 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
87 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
88 #define PCIE_ATU_CR2 0x908
89 #define PCIE_ATU_ENABLE (0x1 << 31)
90 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
91 #define PCIE_ATU_LOWER_BASE 0x90C
92 #define PCIE_ATU_UPPER_BASE 0x910
93 #define PCIE_ATU_LIMIT 0x914
94 #define PCIE_ATU_LOWER_TARGET 0x918
95 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
96 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
97 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
98 #define PCIE_ATU_UPPER_TARGET 0x91C
99
100 struct imx_pcie_priv {
101 void __iomem *dbi_base;
102 void __iomem *cfg_base;
103 };
104
105 /*
106 * PHY access functions
107 */
pcie_phy_poll_ack(void __iomem * dbi_base,int exp_val)108 static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
109 {
110 u32 val;
111 u32 max_iterations = 10;
112 u32 wait_counter = 0;
113
114 do {
115 val = readl(dbi_base + PCIE_PHY_STAT);
116 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
117 wait_counter++;
118
119 if (val == exp_val)
120 return 0;
121
122 udelay(1);
123 } while (wait_counter < max_iterations);
124
125 return -ETIMEDOUT;
126 }
127
pcie_phy_wait_ack(void __iomem * dbi_base,int addr)128 static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
129 {
130 u32 val;
131 int ret;
132
133 val = addr << PCIE_PHY_CTRL_DATA_LOC;
134 writel(val, dbi_base + PCIE_PHY_CTRL);
135
136 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
137 writel(val, dbi_base + PCIE_PHY_CTRL);
138
139 ret = pcie_phy_poll_ack(dbi_base, 1);
140 if (ret)
141 return ret;
142
143 val = addr << PCIE_PHY_CTRL_DATA_LOC;
144 writel(val, dbi_base + PCIE_PHY_CTRL);
145
146 ret = pcie_phy_poll_ack(dbi_base, 0);
147 if (ret)
148 return ret;
149
150 return 0;
151 }
152
153 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
pcie_phy_read(void __iomem * dbi_base,int addr,int * data)154 static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
155 {
156 u32 val, phy_ctl;
157 int ret;
158
159 ret = pcie_phy_wait_ack(dbi_base, addr);
160 if (ret)
161 return ret;
162
163 /* assert Read signal */
164 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
165 writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
166
167 ret = pcie_phy_poll_ack(dbi_base, 1);
168 if (ret)
169 return ret;
170
171 val = readl(dbi_base + PCIE_PHY_STAT);
172 *data = val & 0xffff;
173
174 /* deassert Read signal */
175 writel(0x00, dbi_base + PCIE_PHY_CTRL);
176
177 ret = pcie_phy_poll_ack(dbi_base, 0);
178 if (ret)
179 return ret;
180
181 return 0;
182 }
183
pcie_phy_write(void __iomem * dbi_base,int addr,int data)184 static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
185 {
186 u32 var;
187 int ret;
188
189 /* write addr */
190 /* cap addr */
191 ret = pcie_phy_wait_ack(dbi_base, addr);
192 if (ret)
193 return ret;
194
195 var = data << PCIE_PHY_CTRL_DATA_LOC;
196 writel(var, dbi_base + PCIE_PHY_CTRL);
197
198 /* capture data */
199 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
200 writel(var, dbi_base + PCIE_PHY_CTRL);
201
202 ret = pcie_phy_poll_ack(dbi_base, 1);
203 if (ret)
204 return ret;
205
206 /* deassert cap data */
207 var = data << PCIE_PHY_CTRL_DATA_LOC;
208 writel(var, dbi_base + PCIE_PHY_CTRL);
209
210 /* wait for ack de-assertion */
211 ret = pcie_phy_poll_ack(dbi_base, 0);
212 if (ret)
213 return ret;
214
215 /* assert wr signal */
216 var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
217 writel(var, dbi_base + PCIE_PHY_CTRL);
218
219 /* wait for ack */
220 ret = pcie_phy_poll_ack(dbi_base, 1);
221 if (ret)
222 return ret;
223
224 /* deassert wr signal */
225 var = data << PCIE_PHY_CTRL_DATA_LOC;
226 writel(var, dbi_base + PCIE_PHY_CTRL);
227
228 /* wait for ack de-assertion */
229 ret = pcie_phy_poll_ack(dbi_base, 0);
230 if (ret)
231 return ret;
232
233 writel(0x0, dbi_base + PCIE_PHY_CTRL);
234
235 return 0;
236 }
237
imx6_pcie_link_up(struct imx_pcie_priv * priv)238 static int imx6_pcie_link_up(struct imx_pcie_priv *priv)
239 {
240 u32 rc, ltssm;
241 int rx_valid, temp;
242
243 /* link is debug bit 36, debug register 1 starts at bit 32 */
244 rc = readl(priv->dbi_base + PCIE_PHY_DEBUG_R1);
245 if ((rc & PCIE_PHY_DEBUG_R1_LINK_UP) &&
246 !(rc & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))
247 return -EAGAIN;
248
249 /*
250 * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
251 * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
252 * If (MAC/LTSSM.state == Recovery.RcvrLock)
253 * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
254 * to gen2 is stuck
255 */
256 pcie_phy_read(priv->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
257 ltssm = readl(priv->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;
258
259 if (rx_valid & 0x01)
260 return 0;
261
262 if (ltssm != 0x0d)
263 return 0;
264
265 printf("transition to gen2 is stuck, reset PHY!\n");
266
267 pcie_phy_read(priv->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
268 temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
269 pcie_phy_write(priv->dbi_base, PHY_RX_OVRD_IN_LO, temp);
270
271 udelay(3000);
272
273 pcie_phy_read(priv->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
274 temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
275 pcie_phy_write(priv->dbi_base, PHY_RX_OVRD_IN_LO, temp);
276
277 return 0;
278 }
279
280 /*
281 * iATU region setup
282 */
imx_pcie_regions_setup(struct imx_pcie_priv * priv)283 static int imx_pcie_regions_setup(struct imx_pcie_priv *priv)
284 {
285 /*
286 * i.MX6 defines 16MB in the AXI address map for PCIe.
287 *
288 * That address space excepted the pcie registers is
289 * split and defined into different regions by iATU,
290 * with sizes and offsets as follows:
291 *
292 * 0x0100_0000 --- 0x010F_FFFF 1MB IORESOURCE_IO
293 * 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM
294 * 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + Registers
295 */
296
297 /* CMD reg:I/O space, MEM space, and Bus Master Enable */
298 setbits_le32(priv->dbi_base + PCI_COMMAND,
299 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
300
301 /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
302 setbits_le32(priv->dbi_base + PCI_CLASS_REVISION,
303 PCI_CLASS_BRIDGE_PCI << 16);
304
305 /* Region #0 is used for Outbound CFG space access. */
306 writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
307
308 writel(lower_32_bits((uintptr_t)priv->cfg_base),
309 priv->dbi_base + PCIE_ATU_LOWER_BASE);
310 writel(upper_32_bits((uintptr_t)priv->cfg_base),
311 priv->dbi_base + PCIE_ATU_UPPER_BASE);
312 writel(lower_32_bits((uintptr_t)priv->cfg_base + MX6_ROOT_SIZE),
313 priv->dbi_base + PCIE_ATU_LIMIT);
314
315 writel(0, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
316 writel(0, priv->dbi_base + PCIE_ATU_UPPER_TARGET);
317 writel(PCIE_ATU_TYPE_CFG0, priv->dbi_base + PCIE_ATU_CR1);
318 writel(PCIE_ATU_ENABLE, priv->dbi_base + PCIE_ATU_CR2);
319
320 return 0;
321 }
322
323 /*
324 * PCI Express accessors
325 */
get_bus_address(struct imx_pcie_priv * priv,pci_dev_t d,int where)326 static void __iomem *get_bus_address(struct imx_pcie_priv *priv,
327 pci_dev_t d, int where)
328 {
329 void __iomem *va_address;
330
331 /* Reconfigure Region #0 */
332 writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
333
334 if (PCI_BUS(d) < 2)
335 writel(PCIE_ATU_TYPE_CFG0, priv->dbi_base + PCIE_ATU_CR1);
336 else
337 writel(PCIE_ATU_TYPE_CFG1, priv->dbi_base + PCIE_ATU_CR1);
338
339 if (PCI_BUS(d) == 0) {
340 va_address = priv->dbi_base;
341 } else {
342 writel(d << 8, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
343 va_address = priv->cfg_base;
344 }
345
346 va_address += (where & ~0x3);
347
348 return va_address;
349 }
350
imx_pcie_addr_valid(pci_dev_t d)351 static int imx_pcie_addr_valid(pci_dev_t d)
352 {
353 if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 1))
354 return -EINVAL;
355 if ((PCI_BUS(d) == 1) && (PCI_DEV(d) > 0))
356 return -EINVAL;
357 return 0;
358 }
359
360 /*
361 * Replace the original ARM DABT handler with a simple jump-back one.
362 *
363 * The problem here is that if we have a PCIe bridge attached to this PCIe
364 * controller, but no PCIe device is connected to the bridges' downstream
365 * port, the attempt to read/write from/to the config space will produce
366 * a DABT. This is a behavior of the controller and can not be disabled
367 * unfortuatelly.
368 *
369 * To work around the problem, we backup the current DABT handler address
370 * and replace it with our own DABT handler, which only bounces right back
371 * into the code.
372 */
imx_pcie_fix_dabt_handler(bool set)373 static void imx_pcie_fix_dabt_handler(bool set)
374 {
375 extern uint32_t *_data_abort;
376 uint32_t *data_abort_addr = (uint32_t *)&_data_abort;
377
378 static const uint32_t data_abort_bounce_handler = 0xe25ef004;
379 uint32_t data_abort_bounce_addr = (uint32_t)&data_abort_bounce_handler;
380
381 static uint32_t data_abort_backup;
382
383 if (set) {
384 data_abort_backup = *data_abort_addr;
385 *data_abort_addr = data_abort_bounce_addr;
386 } else {
387 *data_abort_addr = data_abort_backup;
388 }
389 }
390
imx_pcie_read_cfg(struct imx_pcie_priv * priv,pci_dev_t d,int where,u32 * val)391 static int imx_pcie_read_cfg(struct imx_pcie_priv *priv, pci_dev_t d,
392 int where, u32 *val)
393 {
394 void __iomem *va_address;
395 int ret;
396
397 ret = imx_pcie_addr_valid(d);
398 if (ret) {
399 *val = 0xffffffff;
400 return 0;
401 }
402
403 va_address = get_bus_address(priv, d, where);
404
405 /*
406 * Read the PCIe config space. We must replace the DABT handler
407 * here in case we got data abort from the PCIe controller, see
408 * imx_pcie_fix_dabt_handler() description. Note that writing the
409 * "val" with valid value is also imperative here as in case we
410 * did got DABT, the val would contain random value.
411 */
412 imx_pcie_fix_dabt_handler(true);
413 writel(0xffffffff, val);
414 *val = readl(va_address);
415 imx_pcie_fix_dabt_handler(false);
416
417 return 0;
418 }
419
imx_pcie_write_cfg(struct imx_pcie_priv * priv,pci_dev_t d,int where,u32 val)420 static int imx_pcie_write_cfg(struct imx_pcie_priv *priv, pci_dev_t d,
421 int where, u32 val)
422 {
423 void __iomem *va_address = NULL;
424 int ret;
425
426 ret = imx_pcie_addr_valid(d);
427 if (ret)
428 return ret;
429
430 va_address = get_bus_address(priv, d, where);
431
432 /*
433 * Write the PCIe config space. We must replace the DABT handler
434 * here in case we got data abort from the PCIe controller, see
435 * imx_pcie_fix_dabt_handler() description.
436 */
437 imx_pcie_fix_dabt_handler(true);
438 writel(val, va_address);
439 imx_pcie_fix_dabt_handler(false);
440
441 return 0;
442 }
443
444 /*
445 * Initial bus setup
446 */
imx6_pcie_assert_core_reset(struct imx_pcie_priv * priv,bool prepare_for_boot)447 static int imx6_pcie_assert_core_reset(struct imx_pcie_priv *priv,
448 bool prepare_for_boot)
449 {
450 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
451
452 if (is_mx6dqp())
453 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
454
455 #if defined(CONFIG_MX6SX)
456 struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
457
458 /* SSP_EN is not used on MX6SX anymore */
459 setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
460 /* Force PCIe PHY reset */
461 setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
462 /* Power up PCIe PHY */
463 setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
464 #else
465 /*
466 * If the bootloader already enabled the link we need some special
467 * handling to get the core back into a state where it is safe to
468 * touch it for configuration. As there is no dedicated reset signal
469 * wired up for MX6QDL, we need to manually force LTSSM into "detect"
470 * state before completely disabling LTSSM, which is a prerequisite
471 * for core configuration.
472 *
473 * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
474 * indication that the bootloader activated the link.
475 */
476 if ((is_mx6dq() || is_mx6sdl()) && prepare_for_boot) {
477 u32 val, gpr1, gpr12;
478
479 gpr1 = readl(&iomuxc_regs->gpr[1]);
480 gpr12 = readl(&iomuxc_regs->gpr[12]);
481 if ((gpr1 & IOMUXC_GPR1_PCIE_REF_CLK_EN) &&
482 (gpr12 & IOMUXC_GPR12_PCIE_CTL_2)) {
483 val = readl(priv->dbi_base + PCIE_PL_PFLR);
484 val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
485 val |= PCIE_PL_PFLR_FORCE_LINK;
486
487 imx_pcie_fix_dabt_handler(true);
488 writel(val, priv->dbi_base + PCIE_PL_PFLR);
489 imx_pcie_fix_dabt_handler(false);
490
491 gpr12 &= ~IOMUXC_GPR12_PCIE_CTL_2;
492 writel(val, &iomuxc_regs->gpr[12]);
493 }
494 }
495 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
496 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
497 #endif
498
499 return 0;
500 }
501
imx6_pcie_init_phy(void)502 static int imx6_pcie_init_phy(void)
503 {
504 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
505
506 clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
507
508 clrsetbits_le32(&iomuxc_regs->gpr[12],
509 IOMUXC_GPR12_DEVICE_TYPE_MASK,
510 IOMUXC_GPR12_DEVICE_TYPE_RC);
511 clrsetbits_le32(&iomuxc_regs->gpr[12],
512 IOMUXC_GPR12_LOS_LEVEL_MASK,
513 IOMUXC_GPR12_LOS_LEVEL_9);
514
515 #ifdef CONFIG_MX6SX
516 clrsetbits_le32(&iomuxc_regs->gpr[12],
517 IOMUXC_GPR12_RX_EQ_MASK,
518 IOMUXC_GPR12_RX_EQ_2);
519 #endif
520
521 writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) |
522 (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) |
523 (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) |
524 (127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET) |
525 (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET),
526 &iomuxc_regs->gpr[8]);
527
528 return 0;
529 }
530
imx6_pcie_toggle_power(void)531 __weak int imx6_pcie_toggle_power(void)
532 {
533 #ifdef CONFIG_PCIE_IMX_POWER_GPIO
534 gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "pcie_power");
535 gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0);
536 mdelay(20);
537 gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1);
538 mdelay(20);
539 gpio_free(CONFIG_PCIE_IMX_POWER_GPIO);
540 #endif
541 return 0;
542 }
543
imx6_pcie_toggle_reset(void)544 __weak int imx6_pcie_toggle_reset(void)
545 {
546 /*
547 * See 'PCI EXPRESS BASE SPECIFICATION, REV 3.0, SECTION 6.6.1'
548 * for detailed understanding of the PCIe CR reset logic.
549 *
550 * The PCIe #PERST reset line _MUST_ be connected, otherwise your
551 * design does not conform to the specification. You must wait at
552 * least 20 ms after de-asserting the #PERST so the EP device can
553 * do self-initialisation.
554 *
555 * In case your #PERST pin is connected to a plain GPIO pin of the
556 * CPU, you can define CONFIG_PCIE_IMX_PERST_GPIO in your board's
557 * configuration file and the condition below will handle the rest
558 * of the reset toggling.
559 *
560 * In case your #PERST toggling logic is more complex, for example
561 * connected via CPLD or somesuch, you can override this function
562 * in your board file and implement reset logic as needed. You must
563 * not forget to wait at least 20 ms after de-asserting #PERST in
564 * this case either though.
565 *
566 * In case your #PERST line of the PCIe EP device is not connected
567 * at all, your design is broken and you should fix your design,
568 * otherwise you will observe problems like for example the link
569 * not coming up after rebooting the system back from running Linux
570 * that uses the PCIe as well OR the PCIe link might not come up in
571 * Linux at all in the first place since it's in some non-reset
572 * state due to being previously used in U-Boot.
573 */
574 #ifdef CONFIG_PCIE_IMX_PERST_GPIO
575 gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "pcie_reset");
576 gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0);
577 mdelay(20);
578 gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1);
579 mdelay(20);
580 gpio_free(CONFIG_PCIE_IMX_PERST_GPIO);
581 #else
582 puts("WARNING: Make sure the PCIe #PERST line is connected!\n");
583 #endif
584 return 0;
585 }
586
imx6_pcie_deassert_core_reset(void)587 static int imx6_pcie_deassert_core_reset(void)
588 {
589 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
590
591 imx6_pcie_toggle_power();
592
593 enable_pcie_clock();
594
595 if (is_mx6dqp())
596 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
597
598 /*
599 * Wait for the clock to settle a bit, when the clock are sourced
600 * from the CPU, we need about 30 ms to settle.
601 */
602 mdelay(50);
603
604 #if defined(CONFIG_MX6SX)
605 /* SSP_EN is not used on MX6SX anymore */
606 clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
607 /* Clear PCIe PHY reset bit */
608 clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
609 #else
610 /* Enable PCIe */
611 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
612 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
613 #endif
614
615 imx6_pcie_toggle_reset();
616
617 return 0;
618 }
619
imx_pcie_link_up(struct imx_pcie_priv * priv)620 static int imx_pcie_link_up(struct imx_pcie_priv *priv)
621 {
622 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
623 uint32_t tmp;
624 int count = 0;
625
626 imx6_pcie_assert_core_reset(priv, false);
627 imx6_pcie_init_phy();
628 imx6_pcie_deassert_core_reset();
629
630 imx_pcie_regions_setup(priv);
631
632 /*
633 * By default, the subordinate is set equally to the secondary
634 * bus (0x01) when the RC boots.
635 * This means that theoretically, only bus 1 is reachable from the RC.
636 * Force the PCIe RC subordinate to 0xff, otherwise no downstream
637 * devices will be detected if the enumeration is applied strictly.
638 */
639 tmp = readl(priv->dbi_base + 0x18);
640 tmp |= (0xff << 16);
641 writel(tmp, priv->dbi_base + 0x18);
642
643 /*
644 * FIXME: Force the PCIe RC to Gen1 operation
645 * The RC must be forced into Gen1 mode before bringing the link
646 * up, otherwise no downstream devices are detected. After the
647 * link is up, a managed Gen1->Gen2 transition can be initiated.
648 */
649 tmp = readl(priv->dbi_base + 0x7c);
650 tmp &= ~0xf;
651 tmp |= 0x1;
652 writel(tmp, priv->dbi_base + 0x7c);
653
654 /* LTSSM enable, starting link. */
655 setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
656
657 while (!imx6_pcie_link_up(priv)) {
658 udelay(10);
659 count++;
660 if (count >= 4000) {
661 #ifdef CONFIG_PCI_SCAN_SHOW
662 puts("PCI: pcie phy link never came up\n");
663 #endif
664 debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
665 readl(priv->dbi_base + PCIE_PHY_DEBUG_R0),
666 readl(priv->dbi_base + PCIE_PHY_DEBUG_R1));
667 return -EINVAL;
668 }
669 }
670
671 return 0;
672 }
673
674 #if !CONFIG_IS_ENABLED(DM_PCI)
675 static struct imx_pcie_priv imx_pcie_priv = {
676 .dbi_base = (void __iomem *)MX6_DBI_ADDR,
677 .cfg_base = (void __iomem *)MX6_ROOT_ADDR,
678 };
679
680 static struct imx_pcie_priv *priv = &imx_pcie_priv;
681
imx_pcie_read_config(struct pci_controller * hose,pci_dev_t d,int where,u32 * val)682 static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
683 int where, u32 *val)
684 {
685 struct imx_pcie_priv *priv = hose->priv_data;
686
687 return imx_pcie_read_cfg(priv, d, where, val);
688 }
689
imx_pcie_write_config(struct pci_controller * hose,pci_dev_t d,int where,u32 val)690 static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
691 int where, u32 val)
692 {
693 struct imx_pcie_priv *priv = hose->priv_data;
694
695 return imx_pcie_write_cfg(priv, d, where, val);
696 }
697
imx_pcie_init(void)698 void imx_pcie_init(void)
699 {
700 /* Static instance of the controller. */
701 static struct pci_controller pcc;
702 struct pci_controller *hose = &pcc;
703 int ret;
704
705 memset(&pcc, 0, sizeof(pcc));
706
707 hose->priv_data = priv;
708
709 /* PCI I/O space */
710 pci_set_region(&hose->regions[0],
711 MX6_IO_ADDR, MX6_IO_ADDR,
712 MX6_IO_SIZE, PCI_REGION_IO);
713
714 /* PCI memory space */
715 pci_set_region(&hose->regions[1],
716 MX6_MEM_ADDR, MX6_MEM_ADDR,
717 MX6_MEM_SIZE, PCI_REGION_MEM);
718
719 /* System memory space */
720 pci_set_region(&hose->regions[2],
721 MMDC0_ARB_BASE_ADDR, MMDC0_ARB_BASE_ADDR,
722 0xefffffff, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
723
724 hose->region_count = 3;
725
726 pci_set_ops(hose,
727 pci_hose_read_config_byte_via_dword,
728 pci_hose_read_config_word_via_dword,
729 imx_pcie_read_config,
730 pci_hose_write_config_byte_via_dword,
731 pci_hose_write_config_word_via_dword,
732 imx_pcie_write_config);
733
734 /* Start the controller. */
735 ret = imx_pcie_link_up(priv);
736
737 if (!ret) {
738 pci_register_hose(hose);
739 hose->last_busno = pci_hose_scan(hose);
740 }
741 }
742
imx_pcie_remove(void)743 void imx_pcie_remove(void)
744 {
745 imx6_pcie_assert_core_reset(priv, true);
746 }
747
748 /* Probe function. */
pci_init_board(void)749 void pci_init_board(void)
750 {
751 imx_pcie_init();
752 }
753 #else
imx_pcie_dm_read_config(const struct udevice * dev,pci_dev_t bdf,uint offset,ulong * value,enum pci_size_t size)754 static int imx_pcie_dm_read_config(const struct udevice *dev, pci_dev_t bdf,
755 uint offset, ulong *value,
756 enum pci_size_t size)
757 {
758 struct imx_pcie_priv *priv = dev_get_priv(dev);
759 u32 tmpval;
760 int ret;
761
762 ret = imx_pcie_read_cfg(priv, bdf, offset, &tmpval);
763 if (ret)
764 return ret;
765
766 *value = pci_conv_32_to_size(tmpval, offset, size);
767 return 0;
768 }
769
imx_pcie_dm_write_config(struct udevice * dev,pci_dev_t bdf,uint offset,ulong value,enum pci_size_t size)770 static int imx_pcie_dm_write_config(struct udevice *dev, pci_dev_t bdf,
771 uint offset, ulong value,
772 enum pci_size_t size)
773 {
774 struct imx_pcie_priv *priv = dev_get_priv(dev);
775 u32 tmpval, newval;
776 int ret;
777
778 ret = imx_pcie_read_cfg(priv, bdf, offset, &tmpval);
779 if (ret)
780 return ret;
781
782 newval = pci_conv_size_to_32(tmpval, value, offset, size);
783 return imx_pcie_write_cfg(priv, bdf, offset, newval);
784 }
785
imx_pcie_dm_probe(struct udevice * dev)786 static int imx_pcie_dm_probe(struct udevice *dev)
787 {
788 struct imx_pcie_priv *priv = dev_get_priv(dev);
789
790 return imx_pcie_link_up(priv);
791 }
792
imx_pcie_dm_remove(struct udevice * dev)793 static int imx_pcie_dm_remove(struct udevice *dev)
794 {
795 struct imx_pcie_priv *priv = dev_get_priv(dev);
796
797 imx6_pcie_assert_core_reset(priv, true);
798
799 return 0;
800 }
801
imx_pcie_of_to_plat(struct udevice * dev)802 static int imx_pcie_of_to_plat(struct udevice *dev)
803 {
804 struct imx_pcie_priv *priv = dev_get_priv(dev);
805
806 priv->dbi_base = (void __iomem *)devfdt_get_addr_index(dev, 0);
807 priv->cfg_base = (void __iomem *)devfdt_get_addr_index(dev, 1);
808 if (!priv->dbi_base || !priv->cfg_base)
809 return -EINVAL;
810
811 return 0;
812 }
813
814 static const struct dm_pci_ops imx_pcie_ops = {
815 .read_config = imx_pcie_dm_read_config,
816 .write_config = imx_pcie_dm_write_config,
817 };
818
819 static const struct udevice_id imx_pcie_ids[] = {
820 { .compatible = "fsl,imx6q-pcie" },
821 { .compatible = "fsl,imx6sx-pcie" },
822 { }
823 };
824
825 U_BOOT_DRIVER(imx_pcie) = {
826 .name = "imx_pcie",
827 .id = UCLASS_PCI,
828 .of_match = imx_pcie_ids,
829 .ops = &imx_pcie_ops,
830 .probe = imx_pcie_dm_probe,
831 .remove = imx_pcie_dm_remove,
832 .of_to_plat = imx_pcie_of_to_plat,
833 .priv_auto = sizeof(struct imx_pcie_priv),
834 .flags = DM_FLAG_OS_PREPARE,
835 };
836 #endif
837