1 /* SPDX-License-Identifier: GPL-2.0 */
2 /**
3 * core.h - DesignWare USB3 DRD Core Header
4 *
5 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 *
10 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.h) and ported
11 * to uboot.
12 *
13 * commit 460d098cb6 : usb: dwc3: make HIRD threshold configurable
14 *
15 */
16
17 #ifndef __DRIVERS_USB_DWC3_CORE_H
18 #define __DRIVERS_USB_DWC3_CORE_H
19
20 #include <linux/bitops.h>
21 #include <linux/ioport.h>
22
23 #include <linux/usb/ch9.h>
24 #include <linux/usb/otg.h>
25 #include <linux/usb/phy.h>
26
27 #define DWC3_MSG_MAX 500
28
29 /* Global constants */
30 #define DWC3_EP0_BOUNCE_SIZE 512
31 #define DWC3_ENDPOINTS_NUM 32
32 #define DWC3_XHCI_RESOURCES_NUM 2
33
34 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */
35 #define DWC3_EVENT_SIZE 4 /* bytes */
36 #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */
37 #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM)
38 #define DWC3_EVENT_TYPE_MASK 0xfe
39
40 #define DWC3_EVENT_TYPE_DEV 0
41 #define DWC3_EVENT_TYPE_CARKIT 3
42 #define DWC3_EVENT_TYPE_I2C 4
43
44 #define DWC3_DEVICE_EVENT_DISCONNECT 0
45 #define DWC3_DEVICE_EVENT_RESET 1
46 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2
47 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
48 #define DWC3_DEVICE_EVENT_WAKEUP 4
49 #define DWC3_DEVICE_EVENT_HIBER_REQ 5
50 #define DWC3_DEVICE_EVENT_EOPF 6
51 #define DWC3_DEVICE_EVENT_SOF 7
52 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
53 #define DWC3_DEVICE_EVENT_CMD_CMPL 10
54 #define DWC3_DEVICE_EVENT_OVERFLOW 11
55
56 #define DWC3_GEVNTCOUNT_MASK 0xfffc
57 #define DWC3_GSNPSID_MASK 0xffff0000
58 #define DWC3_GSNPSREV_MASK 0xffff
59
60 /* DWC3 registers memory space boundries */
61 #define DWC3_XHCI_REGS_START 0x0
62 #define DWC3_XHCI_REGS_END 0x7fff
63 #define DWC3_GLOBALS_REGS_START 0xc100
64 #define DWC3_GLOBALS_REGS_END 0xc6ff
65 #define DWC3_DEVICE_REGS_START 0xc700
66 #define DWC3_DEVICE_REGS_END 0xcbff
67 #define DWC3_OTG_REGS_START 0xcc00
68 #define DWC3_OTG_REGS_END 0xccff
69
70 /* Global Registers */
71 #define DWC3_GSBUSCFG0 0xc100
72 #define DWC3_GSBUSCFG1 0xc104
73 #define DWC3_GTXTHRCFG 0xc108
74 #define DWC3_GRXTHRCFG 0xc10c
75 #define DWC3_GCTL 0xc110
76 #define DWC3_GEVTEN 0xc114
77 #define DWC3_GSTS 0xc118
78 #define DWC3_GUCTL1 0xc11c
79 #define DWC3_GSNPSID 0xc120
80 #define DWC3_GGPIO 0xc124
81 #define DWC3_GUID 0xc128
82 #define DWC3_GUCTL 0xc12c
83 #define DWC3_GBUSERRADDR0 0xc130
84 #define DWC3_GBUSERRADDR1 0xc134
85 #define DWC3_GPRTBIMAP0 0xc138
86 #define DWC3_GPRTBIMAP1 0xc13c
87 #define DWC3_GHWPARAMS0 0xc140
88 #define DWC3_GHWPARAMS1 0xc144
89 #define DWC3_GHWPARAMS2 0xc148
90 #define DWC3_GHWPARAMS3 0xc14c
91 #define DWC3_GHWPARAMS4 0xc150
92 #define DWC3_GHWPARAMS5 0xc154
93 #define DWC3_GHWPARAMS6 0xc158
94 #define DWC3_GHWPARAMS7 0xc15c
95 #define DWC3_GDBGFIFOSPACE 0xc160
96 #define DWC3_GDBGLTSSM 0xc164
97 #define DWC3_GPRTBIMAP_HS0 0xc180
98 #define DWC3_GPRTBIMAP_HS1 0xc184
99 #define DWC3_GPRTBIMAP_FS0 0xc188
100 #define DWC3_GPRTBIMAP_FS1 0xc18c
101
102 #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
103 #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
104
105 #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
106
107 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
108
109 #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
110 #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
111
112 #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))
113 #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))
114 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))
115 #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
116
117 #define DWC3_GHWPARAMS8 0xc600
118
119 /* Device Registers */
120 #define DWC3_DCFG 0xc700
121 #define DWC3_DCTL 0xc704
122 #define DWC3_DEVTEN 0xc708
123 #define DWC3_DSTS 0xc70c
124 #define DWC3_DGCMDPAR 0xc710
125 #define DWC3_DGCMD 0xc714
126 #define DWC3_DALEPENA 0xc720
127 #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10))
128 #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10))
129 #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10))
130 #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10))
131
132 /* OTG Registers */
133 #define DWC3_OCFG 0xcc00
134 #define DWC3_OCTL 0xcc04
135 #define DWC3_OEVT 0xcc08
136 #define DWC3_OEVTEN 0xcc0C
137 #define DWC3_OSTS 0xcc10
138
139 /* Bit fields */
140
141 /* Global Configuration Register */
142 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
143 #define DWC3_GCTL_U2RSTECN (1 << 16)
144 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
145 #define DWC3_GCTL_CLK_BUS (0)
146 #define DWC3_GCTL_CLK_PIPE (1)
147 #define DWC3_GCTL_CLK_PIPEHALF (2)
148 #define DWC3_GCTL_CLK_MASK (3)
149
150 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
151 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
152 #define DWC3_GCTL_PRTCAP_HOST 1
153 #define DWC3_GCTL_PRTCAP_DEVICE 2
154 #define DWC3_GCTL_PRTCAP_OTG 3
155
156 #define DWC3_GCTL_CORESOFTRESET (1 << 11)
157 #define DWC3_GCTL_SOFITPSYNC (1 << 10)
158 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
159 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
160 #define DWC3_GCTL_DISSCRAMBLE (1 << 3)
161 #define DWC3_GCTL_U2EXIT_LFPS (1 << 2)
162 #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
163 #define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
164
165 /* Global User Control Register */
166 #define DWC3_GUCTL_HSTINAUTORETRY BIT(14)
167
168 /* Global User Control 1 Register */
169 #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
170 #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
171
172 /* Global USB2 PHY Configuration Register */
173 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
174 #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30)
175 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
176 #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8)
177 #define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3)
178 #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
179 #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10)
180 #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
181 #define USBTRDTIM_UTMI_8_BIT 9
182 #define USBTRDTIM_UTMI_16_BIT 5
183 #define UTMI_PHYIF_16_BIT 1
184 #define UTMI_PHYIF_8_BIT 0
185
186 /* Global USB3 PIPE Control Register */
187 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
188 #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29)
189 #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24)
190 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
191 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
192 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
193 #define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18)
194 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
195 #define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9)
196 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8)
197 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
198 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
199
200 /* Global TX Fifo Size Register */
201 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
202 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
203
204 /* Global Event Size Registers */
205 #define DWC3_GEVNTSIZ_INTMASK (1 << 31)
206 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
207
208 /* Global HWPARAMS1 Register */
209 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
210 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
211 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
212 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
213 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
214 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
215
216 /* Global HWPARAMS3 Register */
217 #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
218 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
219 #define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1
220 #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
221 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
222 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
223 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
224 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
225 #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
226 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
227 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
228
229 /* Global HWPARAMS4 Register */
230 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
231 #define DWC3_MAX_HIBER_SCRATCHBUFS 15
232
233 /* Global HWPARAMS6 Register */
234 #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7)
235
236 /* Device Configuration Register */
237 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
238 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
239
240 #define DWC3_DCFG_SPEED_MASK (7 << 0)
241 #define DWC3_DCFG_SUPERSPEED (4 << 0)
242 #define DWC3_DCFG_HIGHSPEED (0 << 0)
243 #define DWC3_DCFG_FULLSPEED2 (1 << 0)
244 #define DWC3_DCFG_LOWSPEED (2 << 0)
245 #define DWC3_DCFG_FULLSPEED1 (3 << 0)
246
247 #define DWC3_DCFG_LPM_CAP (1 << 22)
248
249 /* Device Control Register */
250 #define DWC3_DCTL_RUN_STOP (1 << 31)
251 #define DWC3_DCTL_CSFTRST (1 << 30)
252 #define DWC3_DCTL_LSFTRST (1 << 29)
253
254 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
255 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
256
257 #define DWC3_DCTL_APPL1RES (1 << 23)
258
259 /* These apply for core versions 1.87a and earlier */
260 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
261 #define DWC3_DCTL_TRGTULST(n) ((n) << 17)
262 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
263 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
264 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
265 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
266 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
267
268 /* These apply for core versions 1.94a and later */
269 #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf)
270 #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20)
271
272 #define DWC3_DCTL_KEEP_CONNECT (1 << 19)
273 #define DWC3_DCTL_L1_HIBER_EN (1 << 18)
274 #define DWC3_DCTL_CRS (1 << 17)
275 #define DWC3_DCTL_CSS (1 << 16)
276
277 #define DWC3_DCTL_INITU2ENA (1 << 12)
278 #define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
279 #define DWC3_DCTL_INITU1ENA (1 << 10)
280 #define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
281 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
282
283 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
284 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
285
286 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
287 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
288 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
289 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
290 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
291 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
292 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
293
294 /* Device Event Enable Register */
295 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
296 #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)
297 #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10)
298 #define DWC3_DEVTEN_ERRTICERREN (1 << 9)
299 #define DWC3_DEVTEN_SOFEN (1 << 7)
300 #define DWC3_DEVTEN_EOPFEN (1 << 6)
301 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)
302 #define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
303 #define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
304 #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
305 #define DWC3_DEVTEN_USBRSTEN (1 << 1)
306 #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
307
308 /* Device Status Register */
309 #define DWC3_DSTS_DCNRD (1 << 29)
310
311 /* This applies for core versions 1.87a and earlier */
312 #define DWC3_DSTS_PWRUPREQ (1 << 24)
313
314 /* These apply for core versions 1.94a and later */
315 #define DWC3_DSTS_RSS (1 << 25)
316 #define DWC3_DSTS_SSS (1 << 24)
317
318 #define DWC3_DSTS_COREIDLE (1 << 23)
319 #define DWC3_DSTS_DEVCTRLHLT (1 << 22)
320
321 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
322 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
323
324 #define DWC3_DSTS_RXFIFOEMPTY (1 << 17)
325
326 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
327 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
328
329 #define DWC3_DSTS_CONNECTSPD (7 << 0)
330
331 #define DWC3_DSTS_SUPERSPEED (4 << 0)
332 #define DWC3_DSTS_HIGHSPEED (0 << 0)
333 #define DWC3_DSTS_FULLSPEED2 (1 << 0)
334 #define DWC3_DSTS_LOWSPEED (2 << 0)
335 #define DWC3_DSTS_FULLSPEED1 (3 << 0)
336
337 /* Device Generic Command Register */
338 #define DWC3_DGCMD_SET_LMP 0x01
339 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
340 #define DWC3_DGCMD_XMIT_FUNCTION 0x03
341
342 /* These apply for core versions 1.94a and later */
343 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
344 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
345
346 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
347 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
348 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
349 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
350
351 #define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1)
352 #define DWC3_DGCMD_CMDACT (1 << 10)
353 #define DWC3_DGCMD_CMDIOC (1 << 8)
354
355 /* Device Generic Command Parameter Register */
356 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0)
357 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
358 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
359 #define DWC3_DGCMDPAR_TX_FIFO (1 << 5)
360 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
361 #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0)
362
363 /* Device Endpoint Command Register */
364 #define DWC3_DEPCMD_PARAM_SHIFT 16
365 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
366 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
367 #define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1)
368 #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)
369 #define DWC3_DEPCMD_CMDACT (1 << 10)
370 #define DWC3_DEPCMD_CMDIOC (1 << 8)
371
372 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
373 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
374 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
375 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
376 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
377 #define DWC3_DEPCMD_SETSTALL (0x04 << 0)
378 /* This applies for core versions 1.90a and earlier */
379 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
380 /* This applies for core versions 1.94a and later */
381 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
382 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
383 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
384
385 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
386 #define DWC3_DALEPENA_EP(n) (1 << n)
387
388 #define DWC3_DEPCMD_TYPE_CONTROL 0
389 #define DWC3_DEPCMD_TYPE_ISOC 1
390 #define DWC3_DEPCMD_TYPE_BULK 2
391 #define DWC3_DEPCMD_TYPE_INTR 3
392
393 /* Structures */
394
395 struct dwc3_trb;
396
397 /**
398 * struct dwc3_event_buffer - Software event buffer representation
399 * @buf: _THE_ buffer
400 * @length: size of this buffer
401 * @lpos: event offset
402 * @count: cache of last read event count register
403 * @flags: flags related to this event buffer
404 * @dma: dma_addr_t
405 * @dwc: pointer to DWC controller
406 */
407 struct dwc3_event_buffer {
408 void *buf;
409 unsigned length;
410 unsigned int lpos;
411 unsigned int count;
412 unsigned int flags;
413
414 #define DWC3_EVENT_PENDING (1UL << 0)
415
416 dma_addr_t dma;
417
418 struct dwc3 *dwc;
419 };
420
421 #define DWC3_EP_FLAG_STALLED (1 << 0)
422 #define DWC3_EP_FLAG_WEDGED (1 << 1)
423
424 #define DWC3_EP_DIRECTION_TX true
425 #define DWC3_EP_DIRECTION_RX false
426
427 #define DWC3_TRB_NUM 32
428 #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1)
429
430 /**
431 * struct dwc3_ep - device side endpoint representation
432 * @endpoint: usb endpoint
433 * @request_list: list of requests for this endpoint
434 * @req_queued: list of requests on this ep which have TRBs setup
435 * @trb_pool: array of transaction buffers
436 * @trb_pool_dma: dma address of @trb_pool
437 * @free_slot: next slot which is going to be used
438 * @busy_slot: first slot which is owned by HW
439 * @desc: usb_endpoint_descriptor pointer
440 * @dwc: pointer to DWC controller
441 * @saved_state: ep state saved during hibernation
442 * @flags: endpoint flags (wedged, stalled, ...)
443 * @current_trb: index of current used trb
444 * @number: endpoint number (1 - 15)
445 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
446 * @resource_index: Resource transfer index
447 * @interval: the interval on which the ISOC transfer is started
448 * @name: a human readable name e.g. ep1out-bulk
449 * @direction: true for TX, false for RX
450 * @stream_capable: true when streams are enabled
451 */
452 struct dwc3_ep {
453 struct usb_ep endpoint;
454 struct list_head request_list;
455 struct list_head req_queued;
456
457 struct dwc3_trb *trb_pool;
458 dma_addr_t trb_pool_dma;
459 u32 free_slot;
460 u32 busy_slot;
461 const struct usb_ss_ep_comp_descriptor *comp_desc;
462 struct dwc3 *dwc;
463
464 u32 saved_state;
465 unsigned flags;
466 #define DWC3_EP_ENABLED (1 << 0)
467 #define DWC3_EP_STALL (1 << 1)
468 #define DWC3_EP_WEDGE (1 << 2)
469 #define DWC3_EP_BUSY (1 << 4)
470 #define DWC3_EP_PENDING_REQUEST (1 << 5)
471 #define DWC3_EP_MISSED_ISOC (1 << 6)
472
473 /* This last one is specific to EP0 */
474 #define DWC3_EP0_DIR_IN (1 << 31)
475
476 unsigned current_trb;
477
478 u8 number;
479 u8 type;
480 u8 resource_index;
481 u32 interval;
482
483 char name[20];
484
485 unsigned direction:1;
486 unsigned stream_capable:1;
487 };
488
489 enum dwc3_phy {
490 DWC3_PHY_UNKNOWN = 0,
491 DWC3_PHY_USB3,
492 DWC3_PHY_USB2,
493 };
494
495 enum dwc3_ep0_next {
496 DWC3_EP0_UNKNOWN = 0,
497 DWC3_EP0_COMPLETE,
498 DWC3_EP0_NRDY_DATA,
499 DWC3_EP0_NRDY_STATUS,
500 };
501
502 enum dwc3_ep0_state {
503 EP0_UNCONNECTED = 0,
504 EP0_SETUP_PHASE,
505 EP0_DATA_PHASE,
506 EP0_STATUS_PHASE,
507 };
508
509 enum dwc3_link_state {
510 /* In SuperSpeed */
511 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
512 DWC3_LINK_STATE_U1 = 0x01,
513 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
514 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
515 DWC3_LINK_STATE_SS_DIS = 0x04,
516 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
517 DWC3_LINK_STATE_SS_INACT = 0x06,
518 DWC3_LINK_STATE_POLL = 0x07,
519 DWC3_LINK_STATE_RECOV = 0x08,
520 DWC3_LINK_STATE_HRESET = 0x09,
521 DWC3_LINK_STATE_CMPLY = 0x0a,
522 DWC3_LINK_STATE_LPBK = 0x0b,
523 DWC3_LINK_STATE_RESET = 0x0e,
524 DWC3_LINK_STATE_RESUME = 0x0f,
525 DWC3_LINK_STATE_MASK = 0x0f,
526 };
527
528 /* TRB Length, PCM and Status */
529 #define DWC3_TRB_SIZE_MASK (0x00ffffff)
530 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
531 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
532 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
533
534 #define DWC3_TRBSTS_OK 0
535 #define DWC3_TRBSTS_MISSED_ISOC 1
536 #define DWC3_TRBSTS_SETUP_PENDING 2
537 #define DWC3_TRB_STS_XFER_IN_PROG 4
538
539 /* TRB Control */
540 #define DWC3_TRB_CTRL_HWO (1 << 0)
541 #define DWC3_TRB_CTRL_LST (1 << 1)
542 #define DWC3_TRB_CTRL_CHN (1 << 2)
543 #define DWC3_TRB_CTRL_CSP (1 << 3)
544 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
545 #define DWC3_TRB_CTRL_ISP_IMI (1 << 10)
546 #define DWC3_TRB_CTRL_IOC (1 << 11)
547 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
548
549 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
550 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
551 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
552 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
553 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
554 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
555 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
556 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
557
558 /**
559 * struct dwc3_trb - transfer request block (hw format)
560 * @bpl: DW0-3
561 * @bph: DW4-7
562 * @size: DW8-B
563 * @trl: DWC-F
564 */
565 struct dwc3_trb {
566 u32 bpl;
567 u32 bph;
568 u32 size;
569 u32 ctrl;
570 } __packed;
571
572 /**
573 * dwc3_hwparams - copy of HWPARAMS registers
574 * @hwparams0 - GHWPARAMS0
575 * @hwparams1 - GHWPARAMS1
576 * @hwparams2 - GHWPARAMS2
577 * @hwparams3 - GHWPARAMS3
578 * @hwparams4 - GHWPARAMS4
579 * @hwparams5 - GHWPARAMS5
580 * @hwparams6 - GHWPARAMS6
581 * @hwparams7 - GHWPARAMS7
582 * @hwparams8 - GHWPARAMS8
583 */
584 struct dwc3_hwparams {
585 u32 hwparams0;
586 u32 hwparams1;
587 u32 hwparams2;
588 u32 hwparams3;
589 u32 hwparams4;
590 u32 hwparams5;
591 u32 hwparams6;
592 u32 hwparams7;
593 u32 hwparams8;
594 };
595
596 /* HWPARAMS0 */
597 #define DWC3_MODE(n) ((n) & 0x7)
598
599 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
600
601 /* HWPARAMS1 */
602 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
603
604 /* HWPARAMS3 */
605 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
606 #define DWC3_NUM_EPS_MASK (0x3f << 12)
607 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
608 (DWC3_NUM_EPS_MASK)) >> 12)
609 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
610 (DWC3_NUM_IN_EPS_MASK)) >> 18)
611
612 /* HWPARAMS7 */
613 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
614
615 struct dwc3_request {
616 struct usb_request request;
617 struct list_head list;
618 struct dwc3_ep *dep;
619 u32 start_slot;
620
621 u8 epnum;
622 struct dwc3_trb *trb;
623 dma_addr_t trb_dma;
624
625 unsigned direction:1;
626 unsigned mapped:1;
627 unsigned queued:1;
628 };
629
630 /*
631 * struct dwc3_scratchpad_array - hibernation scratchpad array
632 * (format defined by hw)
633 */
634 struct dwc3_scratchpad_array {
635 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
636 };
637
638 /**
639 * struct dwc3 - representation of our controller
640 * @ctrl_req: usb control request which is used for ep0
641 * @ep0_trb: trb which is used for the ctrl_req
642 * @ep0_bounce: bounce buffer for ep0
643 * @setup_buf: used while precessing STD USB requests
644 * @ctrl_req_addr: dma address of ctrl_req
645 * @ep0_trb: dma address of ep0_trb
646 * @ep0_usb_req: dummy req used while handling STD USB requests
647 * @ep0_bounce_addr: dma address of ep0_bounce
648 * @scratch_addr: dma address of scratchbuf
649 * @lock: for synchronizing
650 * @dev: pointer to our struct device
651 * @xhci: pointer to our xHCI child
652 * @event_buffer_list: a list of event buffers
653 * @gadget: device side representation of the peripheral controller
654 * @gadget_driver: pointer to the gadget driver
655 * @regs: base address for our registers
656 * @regs_size: address space size
657 * @nr_scratch: number of scratch buffers
658 * @num_event_buffers: calculated number of event buffers
659 * @u1u2: only used on revisions <1.83a for workaround
660 * @maximum_speed: maximum speed requested (mainly for testing purposes)
661 * @revision: revision register contents
662 * @dr_mode: requested mode of operation
663 * @hsphy_mode: UTMI phy mode, one of following:
664 * - USBPHY_INTERFACE_MODE_UTMI
665 * - USBPHY_INTERFACE_MODE_UTMIW
666 * @dcfg: saved contents of DCFG register
667 * @gctl: saved contents of GCTL register
668 * @isoch_delay: wValue from Set Isochronous Delay request;
669 * @u2sel: parameter from Set SEL request.
670 * @u2pel: parameter from Set SEL request.
671 * @u1sel: parameter from Set SEL request.
672 * @u1pel: parameter from Set SEL request.
673 * @num_out_eps: number of out endpoints
674 * @num_in_eps: number of in endpoints
675 * @ep0_next_event: hold the next expected event
676 * @ep0state: state of endpoint zero
677 * @link_state: link state
678 * @speed: device speed (super, high, full, low)
679 * @mem: points to start of memory which is used for this struct.
680 * @hwparams: copy of hwparams registers
681 * @root: debugfs root folder pointer
682 * @regset: debugfs pointer to regdump file
683 * @test_mode: true when we're entering a USB test mode
684 * @test_mode_nr: test feature selector
685 * @lpm_nyet_threshold: LPM NYET response threshold
686 * @hird_threshold: HIRD threshold
687 * @delayed_status: true when gadget driver asks for delayed status
688 * @ep0_bounced: true when we used bounce buffer
689 * @ep0_expect_in: true when we expect a DATA IN transfer
690 * @has_hibernation: true when dwc3 was configured with Hibernation
691 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
692 * there's now way for software to detect this in runtime.
693 * @is_utmi_l1_suspend: the core asserts output signal
694 * 0 - utmi_sleep_n
695 * 1 - utmi_l1_suspend_n
696 * @is_selfpowered: true when we are selfpowered
697 * @is_fpga: true when we are using the FPGA board
698 * @needs_fifo_resize: not all users might want fifo resizing, flag it
699 * @pullups_connected: true when Run/Stop bit is set
700 * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes.
701 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
702 * @start_config_issued: true when StartConfig command has been issued
703 * @three_stage_setup: set if we perform a three phase setup
704 * @disable_scramble_quirk: set if we enable the disable scramble quirk
705 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
706 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
707 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
708 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
709 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
710 * @lfps_filter_quirk: set if we enable LFPS filter quirk
711 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
712 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
713 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
714 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
715 * @tx_de_emphasis: Tx de-emphasis value
716 * 0 - -6dB de-emphasis
717 * 1 - -3.5dB de-emphasis
718 * 2 - No de-emphasis
719 * 3 - Reserved
720 * @index: index of _this_ controller
721 * @list: to maintain the list of dwc3 controllers
722 */
723 struct dwc3 {
724 struct usb_ctrlrequest *ctrl_req;
725 struct dwc3_trb *ep0_trb;
726 void *ep0_bounce;
727 void *scratchbuf;
728 u8 *setup_buf;
729 dma_addr_t ctrl_req_addr;
730 dma_addr_t ep0_trb_addr;
731 dma_addr_t ep0_bounce_addr;
732 dma_addr_t scratch_addr;
733 struct dwc3_request ep0_usb_req;
734
735 /* device lock */
736 spinlock_t lock;
737
738 #if defined(__UBOOT__) && CONFIG_IS_ENABLED(DM_USB)
739 struct udevice *dev;
740 #else
741 struct device *dev;
742 #endif
743
744 struct platform_device *xhci;
745 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
746
747 struct dwc3_event_buffer **ev_buffs;
748 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
749
750 struct usb_gadget gadget;
751 struct usb_gadget_driver *gadget_driver;
752
753 void __iomem *regs;
754 size_t regs_size;
755
756 enum usb_dr_mode dr_mode;
757 enum usb_phy_interface hsphy_mode;
758
759 /* used for suspend/resume */
760 u32 dcfg;
761 u32 gctl;
762
763 u32 nr_scratch;
764 u32 num_event_buffers;
765 u32 u1u2;
766 u32 maximum_speed;
767 u32 revision;
768
769 #define DWC3_REVISION_173A 0x5533173a
770 #define DWC3_REVISION_175A 0x5533175a
771 #define DWC3_REVISION_180A 0x5533180a
772 #define DWC3_REVISION_183A 0x5533183a
773 #define DWC3_REVISION_185A 0x5533185a
774 #define DWC3_REVISION_187A 0x5533187a
775 #define DWC3_REVISION_188A 0x5533188a
776 #define DWC3_REVISION_190A 0x5533190a
777 #define DWC3_REVISION_194A 0x5533194a
778 #define DWC3_REVISION_200A 0x5533200a
779 #define DWC3_REVISION_202A 0x5533202a
780 #define DWC3_REVISION_210A 0x5533210a
781 #define DWC3_REVISION_220A 0x5533220a
782 #define DWC3_REVISION_230A 0x5533230a
783 #define DWC3_REVISION_240A 0x5533240a
784 #define DWC3_REVISION_250A 0x5533250a
785 #define DWC3_REVISION_260A 0x5533260a
786 #define DWC3_REVISION_270A 0x5533270a
787 #define DWC3_REVISION_280A 0x5533280a
788 #define DWC3_REVISION_290A 0x5533290a
789
790 enum dwc3_ep0_next ep0_next_event;
791 enum dwc3_ep0_state ep0state;
792 enum dwc3_link_state link_state;
793
794 u16 isoch_delay;
795 u16 u2sel;
796 u16 u2pel;
797 u8 u1sel;
798 u8 u1pel;
799
800 u8 speed;
801
802 u8 num_out_eps;
803 u8 num_in_eps;
804
805 void *mem;
806
807 struct dwc3_hwparams hwparams;
808 struct dentry *root;
809 struct debugfs_regset32 *regset;
810
811 u8 test_mode;
812 u8 test_mode_nr;
813 u8 lpm_nyet_threshold;
814 u8 hird_threshold;
815
816 unsigned delayed_status:1;
817 unsigned ep0_bounced:1;
818 unsigned ep0_expect_in:1;
819 unsigned has_hibernation:1;
820 unsigned has_lpm_erratum:1;
821 unsigned is_utmi_l1_suspend:1;
822 unsigned is_selfpowered:1;
823 unsigned is_fpga:1;
824 unsigned needs_fifo_resize:1;
825 unsigned pullups_connected:1;
826 unsigned resize_fifos:1;
827 unsigned setup_packet_pending:1;
828 unsigned start_config_issued:1;
829 unsigned three_stage_setup:1;
830
831 unsigned disable_scramble_quirk:1;
832 unsigned u2exit_lfps_quirk:1;
833 unsigned u2ss_inp3_quirk:1;
834 unsigned req_p1p2p3_quirk:1;
835 unsigned del_p1p2p3_quirk:1;
836 unsigned del_phy_power_chg_quirk:1;
837 unsigned lfps_filter_quirk:1;
838 unsigned rx_detect_poll_quirk:1;
839 unsigned dis_u3_susphy_quirk:1;
840 unsigned dis_u2_susphy_quirk:1;
841 unsigned dis_del_phy_power_chg_quirk:1;
842 unsigned dis_tx_ipgap_linecheck_quirk:1;
843 unsigned dis_enblslpm_quirk:1;
844 unsigned dis_u2_freeclk_exists_quirk:1;
845
846 unsigned tx_de_emphasis_quirk:1;
847 unsigned tx_de_emphasis:2;
848 int index;
849 struct list_head list;
850 };
851
852 /* -------------------------------------------------------------------------- */
853
854 /* -------------------------------------------------------------------------- */
855
856 struct dwc3_event_type {
857 u32 is_devspec:1;
858 u32 type:7;
859 u32 reserved8_31:24;
860 } __packed;
861
862 #define DWC3_DEPEVT_XFERCOMPLETE 0x01
863 #define DWC3_DEPEVT_XFERINPROGRESS 0x02
864 #define DWC3_DEPEVT_XFERNOTREADY 0x03
865 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04
866 #define DWC3_DEPEVT_STREAMEVT 0x06
867 #define DWC3_DEPEVT_EPCMDCMPLT 0x07
868
869 /**
870 * dwc3_ep_event_string - returns event name
871 * @event: then event code
872 */
dwc3_ep_event_string(u8 event)873 static inline const char *dwc3_ep_event_string(u8 event)
874 {
875 switch (event) {
876 case DWC3_DEPEVT_XFERCOMPLETE:
877 return "Transfer Complete";
878 case DWC3_DEPEVT_XFERINPROGRESS:
879 return "Transfer In-Progress";
880 case DWC3_DEPEVT_XFERNOTREADY:
881 return "Transfer Not Ready";
882 case DWC3_DEPEVT_RXTXFIFOEVT:
883 return "FIFO";
884 case DWC3_DEPEVT_STREAMEVT:
885 return "Stream";
886 case DWC3_DEPEVT_EPCMDCMPLT:
887 return "Endpoint Command Complete";
888 }
889
890 return "UNKNOWN";
891 }
892
893 /**
894 * struct dwc3_event_depvt - Device Endpoint Events
895 * @one_bit: indicates this is an endpoint event (not used)
896 * @endpoint_number: number of the endpoint
897 * @endpoint_event: The event we have:
898 * 0x00 - Reserved
899 * 0x01 - XferComplete
900 * 0x02 - XferInProgress
901 * 0x03 - XferNotReady
902 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
903 * 0x05 - Reserved
904 * 0x06 - StreamEvt
905 * 0x07 - EPCmdCmplt
906 * @reserved11_10: Reserved, don't use.
907 * @status: Indicates the status of the event. Refer to databook for
908 * more information.
909 * @parameters: Parameters of the current event. Refer to databook for
910 * more information.
911 */
912 struct dwc3_event_depevt {
913 u32 one_bit:1;
914 u32 endpoint_number:5;
915 u32 endpoint_event:4;
916 u32 reserved11_10:2;
917 u32 status:4;
918
919 /* Within XferNotReady */
920 #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)
921
922 /* Within XferComplete */
923 #define DEPEVT_STATUS_BUSERR (1 << 0)
924 #define DEPEVT_STATUS_SHORT (1 << 1)
925 #define DEPEVT_STATUS_IOC (1 << 2)
926 #define DEPEVT_STATUS_LST (1 << 3)
927
928 /* Stream event only */
929 #define DEPEVT_STREAMEVT_FOUND 1
930 #define DEPEVT_STREAMEVT_NOTFOUND 2
931
932 /* Control-only Status */
933 #define DEPEVT_STATUS_CONTROL_DATA 1
934 #define DEPEVT_STATUS_CONTROL_STATUS 2
935
936 u32 parameters:16;
937 } __packed;
938
939 /**
940 * struct dwc3_event_devt - Device Events
941 * @one_bit: indicates this is a non-endpoint event (not used)
942 * @device_event: indicates it's a device event. Should read as 0x00
943 * @type: indicates the type of device event.
944 * 0 - DisconnEvt
945 * 1 - USBRst
946 * 2 - ConnectDone
947 * 3 - ULStChng
948 * 4 - WkUpEvt
949 * 5 - Reserved
950 * 6 - EOPF
951 * 7 - SOF
952 * 8 - Reserved
953 * 9 - ErrticErr
954 * 10 - CmdCmplt
955 * 11 - EvntOverflow
956 * 12 - VndrDevTstRcved
957 * @reserved15_12: Reserved, not used
958 * @event_info: Information about this event
959 * @reserved31_25: Reserved, not used
960 */
961 struct dwc3_event_devt {
962 u32 one_bit:1;
963 u32 device_event:7;
964 u32 type:4;
965 u32 reserved15_12:4;
966 u32 event_info:9;
967 u32 reserved31_25:7;
968 } __packed;
969
970 /**
971 * struct dwc3_event_gevt - Other Core Events
972 * @one_bit: indicates this is a non-endpoint event (not used)
973 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
974 * @phy_port_number: self-explanatory
975 * @reserved31_12: Reserved, not used.
976 */
977 struct dwc3_event_gevt {
978 u32 one_bit:1;
979 u32 device_event:7;
980 u32 phy_port_number:4;
981 u32 reserved31_12:20;
982 } __packed;
983
984 /**
985 * union dwc3_event - representation of Event Buffer contents
986 * @raw: raw 32-bit event
987 * @type: the type of the event
988 * @depevt: Device Endpoint Event
989 * @devt: Device Event
990 * @gevt: Global Event
991 */
992 union dwc3_event {
993 u32 raw;
994 struct dwc3_event_type type;
995 struct dwc3_event_depevt depevt;
996 struct dwc3_event_devt devt;
997 struct dwc3_event_gevt gevt;
998 };
999
1000 /**
1001 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
1002 * parameters
1003 * @param2: third parameter
1004 * @param1: second parameter
1005 * @param0: first parameter
1006 */
1007 struct dwc3_gadget_ep_cmd_params {
1008 u32 param2;
1009 u32 param1;
1010 u32 param0;
1011 };
1012
1013 /*
1014 * DWC3 Features to be used as Driver Data
1015 */
1016
1017 #define DWC3_HAS_PERIPHERAL BIT(0)
1018 #define DWC3_HAS_XHCI BIT(1)
1019 #define DWC3_HAS_OTG BIT(3)
1020
1021 /* prototypes */
1022 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);
1023 void dwc3_of_parse(struct dwc3 *dwc);
1024 int dwc3_init(struct dwc3 *dwc);
1025 void dwc3_remove(struct dwc3 *dwc);
1026
dwc3_host_init(struct dwc3 * dwc)1027 static inline int dwc3_host_init(struct dwc3 *dwc)
1028 { return 0; }
dwc3_host_exit(struct dwc3 * dwc)1029 static inline void dwc3_host_exit(struct dwc3 *dwc)
1030 { }
1031
1032 #ifdef CONFIG_USB_DWC3_GADGET
1033 int dwc3_gadget_init(struct dwc3 *dwc);
1034 void dwc3_gadget_exit(struct dwc3 *dwc);
1035 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1036 int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1037 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1038 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
1039 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params);
1040 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
1041 #else
dwc3_gadget_init(struct dwc3 * dwc)1042 static inline int dwc3_gadget_init(struct dwc3 *dwc)
1043 { return 0; }
dwc3_gadget_exit(struct dwc3 * dwc)1044 static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1045 { }
dwc3_gadget_set_test_mode(struct dwc3 * dwc,int mode)1046 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1047 { return 0; }
dwc3_gadget_get_link_state(struct dwc3 * dwc)1048 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1049 { return 0; }
dwc3_gadget_set_link_state(struct dwc3 * dwc,enum dwc3_link_state state)1050 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1051 enum dwc3_link_state state)
1052 { return 0; }
1053
dwc3_send_gadget_ep_cmd(struct dwc3 * dwc,unsigned ep,unsigned cmd,struct dwc3_gadget_ep_cmd_params * params)1054 static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
1055 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
1056 { return 0; }
dwc3_send_gadget_generic_command(struct dwc3 * dwc,int cmd,u32 param)1057 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1058 int cmd, u32 param)
1059 { return 0; }
1060 #endif
1061
1062 #endif /* __DRIVERS_USB_DWC3_CORE_H */
1063