1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Marek Vasut <marex@denx.de>
4 *
5 * Based on RAM init sequence by Piotr Dymacz <pepe2k@gmail.com>
6 */
7
8 #include <common.h>
9 #include <asm/global_data.h>
10 #include <asm/io.h>
11 #include <asm/addrspace.h>
12 #include <asm/types.h>
13 #include <linux/bitops.h>
14 #include <linux/delay.h>
15 #include <mach/ar71xx_regs.h>
16 #include <mach/ath79.h>
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 enum {
21 AR934X_SDRAM = 0,
22 AR934X_DDR1,
23 AR934X_DDR2,
24 };
25
26 struct ar934x_mem_config {
27 u32 config1;
28 u32 config2;
29 u32 mode;
30 u32 extmode;
31 u32 tap;
32 };
33
34 static const struct ar934x_mem_config ar934x_mem_config[] = {
35 [AR934X_SDRAM] = { 0x7fbe8cd0, 0x959f66a8, 0x33, 0, 0x1f1f },
36 [AR934X_DDR1] = { 0x7fd48cd0, 0x99d0e6a8, 0x33, 0, 0x14 },
37 [AR934X_DDR2] = { 0xc7d48cd0, 0x9dd0e6a8, 0x33, 0, 0x10012 },
38 };
39
ar934x_ddr_init(const u16 cpu_mhz,const u16 ddr_mhz,const u16 ahb_mhz)40 void ar934x_ddr_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz)
41 {
42 void __iomem *ddr_regs;
43 const struct ar934x_mem_config *memcfg;
44 int memtype;
45 u32 reg, cycle, ctl;
46
47 ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
48 MAP_NOCACHE);
49
50 reg = ath79_get_bootstrap();
51 if (reg & AR934X_BOOTSTRAP_SDRAM_DISABLED) { /* DDR */
52 if (reg & AR934X_BOOTSTRAP_DDR1) { /* DDR 1 */
53 memtype = AR934X_DDR1;
54 cycle = 0xffff;
55 } else { /* DDR 2 */
56 memtype = AR934X_DDR2;
57 if (gd->arch.rev) {
58 ctl = BIT(6); /* Undocumented bit :-( */
59 if (reg & BIT(3))
60 cycle = 0xff;
61 else
62 cycle = 0xffff;
63 } else {
64 /* Force DDR2/x16 configuratio on old chips. */
65 ctl = 0;
66 cycle = 0xffff; /* DDR2 16bit */
67 }
68
69 writel(0xe59, ddr_regs + AR934X_DDR_REG_DDR2_CONFIG);
70 udelay(100);
71
72 writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL);
73 udelay(10);
74
75 writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL);
76 udelay(10);
77
78 writel(ctl, ddr_regs + AR934X_DDR_REG_CTL_CONF);
79 udelay(10);
80 }
81 } else { /* SDRAM */
82 memtype = AR934X_SDRAM;
83 cycle = 0xffffffff;
84
85 writel(0x13b, ddr_regs + AR934X_DDR_REG_CTL_CONF);
86 udelay(100);
87
88 /* Undocumented register */
89 writel(0x13b, ddr_regs + 0x118);
90 udelay(100);
91 }
92
93 memcfg = &ar934x_mem_config[memtype];
94
95 writel(memcfg->config1, ddr_regs + AR71XX_DDR_REG_CONFIG);
96 udelay(100);
97
98 writel(memcfg->config2, ddr_regs + AR71XX_DDR_REG_CONFIG2);
99 udelay(100);
100
101 writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL);
102 udelay(10);
103
104 writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_MODE);
105 mdelay(1);
106
107 writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL);
108 udelay(10);
109
110 if (memtype == AR934X_DDR2) {
111 writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_EMR);
112 udelay(100);
113
114 writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL);
115 udelay(10);
116 }
117
118 if (memtype != AR934X_SDRAM)
119 writel(0x402, ddr_regs + AR71XX_DDR_REG_EMR);
120
121 udelay(100);
122
123 writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL);
124 udelay(10);
125
126 writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL);
127 udelay(10);
128
129 writel(memcfg->mode, ddr_regs + AR71XX_DDR_REG_MODE);
130 udelay(100);
131
132 writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL);
133 udelay(10);
134
135 writel(0x412c /* FIXME */, ddr_regs + AR71XX_DDR_REG_REFRESH);
136 udelay(100);
137
138 writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL0);
139 writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL1);
140
141 if (memtype != AR934X_SDRAM) {
142 if ((gd->arch.rev && (reg & BIT(3))) || !gd->arch.rev) {
143 writel(memcfg->tap,
144 ddr_regs + AR934X_DDR_REG_TAP_CTRL2);
145 writel(memcfg->tap,
146 ddr_regs + AR934X_DDR_REG_TAP_CTRL3);
147 }
148 }
149
150 writel(cycle, ddr_regs + AR71XX_DDR_REG_RD_CYCLE);
151 udelay(100);
152
153 writel(0x74444444, ddr_regs + AR934X_DDR_REG_BURST);
154 udelay(100);
155
156 writel(0x222, ddr_regs + AR934X_DDR_REG_BURST2);
157 udelay(100);
158
159 writel(0xfffff, ddr_regs + AR934X_DDR_REG_TIMEOUT_MAX);
160 udelay(100);
161 }
162
ddr_tap_tuning(void)163 void ddr_tap_tuning(void)
164 {
165 }
166