1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Atheros AR71XX/AR724X/AR913X SoC register definitions 4 * 5 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> 6 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> 7 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> 8 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 9 */ 10 11 #ifndef __ASM_MACH_AR71XX_REGS_H 12 #define __ASM_MACH_AR71XX_REGS_H 13 14 #ifndef __ASSEMBLY__ 15 #include <linux/bitops.h> 16 #else 17 #ifndef BIT 18 #define BIT(nr) (1 << (nr)) 19 #endif 20 #endif 21 22 #define AR71XX_APB_BASE 0x18000000 23 #define AR71XX_GE0_BASE 0x19000000 24 #define AR71XX_GE0_SIZE 0x10000 25 #define AR71XX_GE1_BASE 0x1a000000 26 #define AR71XX_GE1_SIZE 0x10000 27 #define AR71XX_EHCI_BASE 0x1b000000 28 #define AR71XX_EHCI_SIZE 0x1000 29 #define AR71XX_OHCI_BASE 0x1c000000 30 #define AR71XX_OHCI_SIZE 0x1000 31 #define AR71XX_SPI_BASE 0x1f000000 32 #define AR71XX_SPI_SIZE 0x01000000 33 34 #define AR71XX_DDR_CTRL_BASE \ 35 (AR71XX_APB_BASE + 0x00000000) 36 #define AR71XX_DDR_CTRL_SIZE 0x100 37 #define AR71XX_UART_BASE \ 38 (AR71XX_APB_BASE + 0x00020000) 39 #define AR71XX_UART_SIZE 0x100 40 #define AR71XX_USB_CTRL_BASE \ 41 (AR71XX_APB_BASE + 0x00030000) 42 #define AR71XX_USB_CTRL_SIZE 0x100 43 #define AR71XX_GPIO_BASE \ 44 (AR71XX_APB_BASE + 0x00040000) 45 #define AR71XX_GPIO_SIZE 0x100 46 #define AR71XX_PLL_BASE \ 47 (AR71XX_APB_BASE + 0x00050000) 48 #define AR71XX_PLL_SIZE 0x100 49 #define AR71XX_RESET_BASE \ 50 (AR71XX_APB_BASE + 0x00060000) 51 #define AR71XX_RESET_SIZE 0x100 52 #define AR71XX_MII_BASE \ 53 (AR71XX_APB_BASE + 0x00070000) 54 #define AR71XX_MII_SIZE 0x100 55 56 #define AR71XX_PCI_MEM_BASE 0x10000000 57 #define AR71XX_PCI_MEM_SIZE 0x07000000 58 59 #define AR71XX_PCI_WIN0_OFFS 0x10000000 60 #define AR71XX_PCI_WIN1_OFFS 0x11000000 61 #define AR71XX_PCI_WIN2_OFFS 0x12000000 62 #define AR71XX_PCI_WIN3_OFFS 0x13000000 63 #define AR71XX_PCI_WIN4_OFFS 0x14000000 64 #define AR71XX_PCI_WIN5_OFFS 0x15000000 65 #define AR71XX_PCI_WIN6_OFFS 0x16000000 66 #define AR71XX_PCI_WIN7_OFFS 0x07000000 67 68 #define AR71XX_PCI_CFG_BASE \ 69 (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) 70 #define AR71XX_PCI_CFG_SIZE 0x100 71 72 #define AR7240_USB_CTRL_BASE \ 73 (AR71XX_APB_BASE + 0x00030000) 74 #define AR7240_USB_CTRL_SIZE 0x100 75 #define AR7240_OHCI_BASE 0x1b000000 76 #define AR7240_OHCI_SIZE 0x1000 77 78 #define AR724X_PCI_MEM_BASE 0x10000000 79 #define AR724X_PCI_MEM_SIZE 0x04000000 80 81 #define AR724X_PCI_CFG_BASE 0x14000000 82 #define AR724X_PCI_CFG_SIZE 0x1000 83 #define AR724X_PCI_CRP_BASE \ 84 (AR71XX_APB_BASE + 0x000c0000) 85 #define AR724X_PCI_CRP_SIZE 0x1000 86 #define AR724X_PCI_CTRL_BASE \ 87 (AR71XX_APB_BASE + 0x000f0000) 88 #define AR724X_PCI_CTRL_SIZE 0x100 89 90 #define AR724X_EHCI_BASE 0x1b000000 91 #define AR724X_EHCI_SIZE 0x1000 92 93 #define AR913X_EHCI_BASE 0x1b000000 94 #define AR913X_EHCI_SIZE 0x1000 95 #define AR913X_WMAC_BASE \ 96 (AR71XX_APB_BASE + 0x000C0000) 97 #define AR913X_WMAC_SIZE 0x30000 98 99 #define AR933X_UART_BASE \ 100 (AR71XX_APB_BASE + 0x00020000) 101 #define AR933X_UART_SIZE 0x14 102 #define AR933X_GMAC_BASE \ 103 (AR71XX_APB_BASE + 0x00070000) 104 #define AR933X_GMAC_SIZE 0x04 105 #define AR933X_WMAC_BASE \ 106 (AR71XX_APB_BASE + 0x00100000) 107 #define AR933X_WMAC_SIZE 0x20000 108 #define AR933X_RTC_BASE \ 109 (AR71XX_APB_BASE + 0x00107000) 110 #define AR933X_RTC_SIZE 0x1000 111 #define AR933X_EHCI_BASE 0x1b000000 112 #define AR933X_EHCI_SIZE 0x1000 113 #define AR933X_SRIF_BASE \ 114 (AR71XX_APB_BASE + 0x00116000) 115 #define AR933X_SRIF_SIZE 0x1000 116 117 #define AR934X_GMAC_BASE \ 118 (AR71XX_APB_BASE + 0x00070000) 119 #define AR934X_GMAC_SIZE 0x14 120 #define AR934X_WMAC_BASE \ 121 (AR71XX_APB_BASE + 0x00100000) 122 #define AR934X_WMAC_SIZE 0x20000 123 #define AR934X_EHCI_BASE 0x1b000000 124 #define AR934X_EHCI_SIZE 0x200 125 #define AR934X_NFC_BASE 0x1b000200 126 #define AR934X_NFC_SIZE 0xb8 127 #define AR934X_SRIF_BASE \ 128 (AR71XX_APB_BASE + 0x00116000) 129 #define AR934X_SRIF_SIZE 0x1000 130 131 #define QCA953X_GMAC_BASE \ 132 (AR71XX_APB_BASE + 0x00070000) 133 #define QCA953X_GMAC_SIZE 0x14 134 #define QCA953X_WMAC_BASE \ 135 (AR71XX_APB_BASE + 0x00100000) 136 #define QCA953X_WMAC_SIZE 0x20000 137 #define QCA953X_RTC_BASE \ 138 (AR71XX_APB_BASE + 0x00107000) 139 #define QCA953X_RTC_SIZE 0x1000 140 #define QCA953X_EHCI_BASE 0x1b000000 141 #define QCA953X_EHCI_SIZE 0x200 142 #define QCA953X_SRIF_BASE \ 143 (AR71XX_APB_BASE + 0x00116000) 144 #define QCA953X_SRIF_SIZE 0x1000 145 146 #define QCA953X_PCI_CFG_BASE0 0x14000000 147 #define QCA953X_PCI_CTRL_BASE0 \ 148 (AR71XX_APB_BASE + 0x000f0000) 149 #define QCA953X_PCI_CRP_BASE0 \ 150 (AR71XX_APB_BASE + 0x000c0000) 151 #define QCA953X_PCI_MEM_BASE0 0x10000000 152 #define QCA953X_PCI_MEM_SIZE 0x02000000 153 154 #define QCA955X_PCI_MEM_BASE0 0x10000000 155 #define QCA955X_PCI_MEM_BASE1 0x12000000 156 #define QCA955X_PCI_MEM_SIZE 0x02000000 157 #define QCA955X_PCI_CFG_BASE0 0x14000000 158 #define QCA955X_PCI_CFG_BASE1 0x16000000 159 #define QCA955X_PCI_CFG_SIZE 0x1000 160 #define QCA955X_PCI_CRP_BASE0 \ 161 (AR71XX_APB_BASE + 0x000c0000) 162 #define QCA955X_PCI_CRP_BASE1 \ 163 (AR71XX_APB_BASE + 0x00250000) 164 #define QCA955X_PCI_CRP_SIZE 0x1000 165 #define QCA955X_PCI_CTRL_BASE0 \ 166 (AR71XX_APB_BASE + 0x000f0000) 167 #define QCA955X_PCI_CTRL_BASE1 \ 168 (AR71XX_APB_BASE + 0x00280000) 169 #define QCA955X_PCI_CTRL_SIZE 0x100 170 171 #define QCA955X_GMAC_BASE \ 172 (AR71XX_APB_BASE + 0x00070000) 173 #define QCA955X_GMAC_SIZE 0x40 174 #define QCA955X_WMAC_BASE \ 175 (AR71XX_APB_BASE + 0x00100000) 176 #define QCA955X_WMAC_SIZE 0x20000 177 #define QCA955X_EHCI0_BASE 0x1b000000 178 #define QCA955X_EHCI1_BASE 0x1b400000 179 #define QCA955X_EHCI_SIZE 0x1000 180 #define QCA955X_NFC_BASE 0x1b800200 181 #define QCA955X_NFC_SIZE 0xb8 182 183 #define QCA956X_PCI_MEM_BASE1 0x12000000 184 #define QCA956X_PCI_MEM_SIZE 0x02000000 185 #define QCA956X_PCI_CFG_BASE1 0x16000000 186 #define QCA956X_PCI_CFG_SIZE 0x1000 187 #define QCA956X_PCI_CRP_BASE1 \ 188 (AR71XX_APB_BASE + 0x00250000) 189 #define QCA956X_PCI_CRP_SIZE 0x1000 190 #define QCA956X_PCI_CTRL_BASE1 \ 191 (AR71XX_APB_BASE + 0x00280000) 192 #define QCA956X_PCI_CTRL_SIZE 0x100 193 194 #define QCA956X_WMAC_BASE \ 195 (AR71XX_APB_BASE + 0x00100000) 196 #define QCA956X_WMAC_SIZE 0x20000 197 #define QCA956X_RTC_BASE \ 198 (AR71XX_APB_BASE + 0x00107000) 199 #define QCA956X_RTC_SIZE 0x1000 200 #define QCA956X_EHCI0_BASE 0x1b000000 201 #define QCA956X_EHCI1_BASE 0x1b400000 202 #define QCA956X_EHCI_SIZE 0x200 203 #define QCA956X_GMAC_BASE \ 204 (AR71XX_APB_BASE + 0x00070000) 205 #define QCA956X_GMAC_SIZE 0x64 206 207 #define QCA956X_SRIF_BASE \ 208 (AR71XX_APB_BASE + 0x00116000) 209 #define QCA956X_SRIF_SIZE 0x1000 210 211 /* 212 * DDR_CTRL block 213 */ 214 #define AR71XX_DDR_REG_CONFIG 0x00 215 #define AR71XX_DDR_REG_CONFIG2 0x04 216 #define AR71XX_DDR_REG_MODE 0x08 217 #define AR71XX_DDR_REG_EMR 0x0c 218 #define AR71XX_DDR_REG_CONTROL 0x10 219 #define AR71XX_DDR_REG_REFRESH 0x14 220 #define AR71XX_DDR_REG_RD_CYCLE 0x18 221 #define AR71XX_DDR_REG_TAP_CTRL0 0x1c 222 #define AR71XX_DDR_REG_TAP_CTRL1 0x20 223 224 #define AR71XX_DDR_REG_PCI_WIN0 0x7c 225 #define AR71XX_DDR_REG_PCI_WIN1 0x80 226 #define AR71XX_DDR_REG_PCI_WIN2 0x84 227 #define AR71XX_DDR_REG_PCI_WIN3 0x88 228 #define AR71XX_DDR_REG_PCI_WIN4 0x8c 229 #define AR71XX_DDR_REG_PCI_WIN5 0x90 230 #define AR71XX_DDR_REG_PCI_WIN6 0x94 231 #define AR71XX_DDR_REG_PCI_WIN7 0x98 232 #define AR71XX_DDR_REG_FLUSH_GE0 0x9c 233 #define AR71XX_DDR_REG_FLUSH_GE1 0xa0 234 #define AR71XX_DDR_REG_FLUSH_USB 0xa4 235 #define AR71XX_DDR_REG_FLUSH_PCI 0xa8 236 237 #define AR724X_DDR_REG_FLUSH_GE0 0x7c 238 #define AR724X_DDR_REG_FLUSH_GE1 0x80 239 #define AR724X_DDR_REG_FLUSH_USB 0x84 240 #define AR724X_DDR_REG_FLUSH_PCIE 0x88 241 242 #define AR913X_DDR_REG_FLUSH_GE0 0x7c 243 #define AR913X_DDR_REG_FLUSH_GE1 0x80 244 #define AR913X_DDR_REG_FLUSH_USB 0x84 245 #define AR913X_DDR_REG_FLUSH_WMAC 0x88 246 247 #define AR933X_DDR_REG_FLUSH_GE0 0x7c 248 #define AR933X_DDR_REG_FLUSH_GE1 0x80 249 #define AR933X_DDR_REG_FLUSH_USB 0x84 250 #define AR933X_DDR_REG_FLUSH_WMAC 0x88 251 #define AR933X_DDR_REG_DDR2_CONFIG 0x8c 252 #define AR933X_DDR_REG_EMR2 0x90 253 #define AR933X_DDR_REG_EMR3 0x94 254 #define AR933X_DDR_REG_BURST 0x98 255 #define AR933X_DDR_REG_TIMEOUT_MAX 0x9c 256 #define AR933X_DDR_REG_TIMEOUT_CNT 0x9c 257 #define AR933X_DDR_REG_TIMEOUT_ADDR 0x9c 258 259 #define AR934X_DDR_REG_TAP_CTRL2 0x24 260 #define AR934X_DDR_REG_TAP_CTRL3 0x28 261 #define AR934X_DDR_REG_FLUSH_GE0 0x9c 262 #define AR934X_DDR_REG_FLUSH_GE1 0xa0 263 #define AR934X_DDR_REG_FLUSH_USB 0xa4 264 #define AR934X_DDR_REG_FLUSH_PCIE 0xa8 265 #define AR934X_DDR_REG_FLUSH_WMAC 0xac 266 #define AR934X_DDR_REG_FLUSH_SRC1 0xb0 267 #define AR934X_DDR_REG_FLUSH_SRC2 0xb4 268 #define AR934X_DDR_REG_DDR2_CONFIG 0xb8 269 #define AR934X_DDR_REG_EMR2 0xbc 270 #define AR934X_DDR_REG_EMR3 0xc0 271 #define AR934X_DDR_REG_BURST 0xc4 272 #define AR934X_DDR_REG_BURST2 0xc8 273 #define AR934X_DDR_REG_TIMEOUT_MAX 0xcc 274 #define AR934X_DDR_REG_CTL_CONF 0x108 275 276 #define QCA953X_DDR_REG_FLUSH_GE0 0x9c 277 #define QCA953X_DDR_REG_FLUSH_GE1 0xa0 278 #define QCA953X_DDR_REG_FLUSH_USB 0xa4 279 #define QCA953X_DDR_REG_FLUSH_PCIE 0xa8 280 #define QCA953X_DDR_REG_FLUSH_WMAC 0xac 281 #define QCA953X_DDR_REG_DDR2_CONFIG 0xb8 282 #define QCA953X_DDR_REG_BURST 0xc4 283 #define QCA953X_DDR_REG_BURST2 0xc8 284 #define QCA953X_DDR_REG_TIMEOUT_MAX 0xcc 285 #define QCA953X_DDR_REG_CTL_CONF 0x108 286 #define QCA953X_DDR_REG_CONFIG3 0x15c 287 288 #define QCA956X_DDR_REG_TAP_CTRL2 0x24 289 #define QCA956X_DDR_REG_TAP_CTRL3 0x28 290 #define QCA956X_DDR_REG_DDR2_CONFIG 0xb8 291 #define QCA956X_DDR_REG_DDR2_EMR2 0xbc 292 #define QCA956X_DDR_REG_DDR2_EMR3 0xc0 293 #define QCA956X_DDR_REG_BURST 0xc4 294 #define QCA956X_DDR_REG_BURST2 0xc8 295 #define QCA956X_DDR_REG_TIMEOUT_MAX 0xcc 296 #define QCA956X_DDR_REG_FSM_WAIT_CTRL 0xe4 297 #define QCA956X_DDR_REG_CTL_CONF 0x108 298 #define QCA956X_DDR_REG_DDR3_CONFIG 0x15c 299 300 /* 301 * PLL block 302 */ 303 #define AR71XX_PLL_REG_CPU_CONFIG 0x00 304 #define AR71XX_PLL_REG_SEC_CONFIG 0x04 305 #define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 306 #define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 307 308 #define AR71XX_PLL_DIV_SHIFT 3 309 #define AR71XX_PLL_DIV_MASK 0x1f 310 #define AR71XX_CPU_DIV_SHIFT 16 311 #define AR71XX_CPU_DIV_MASK 0x3 312 #define AR71XX_DDR_DIV_SHIFT 18 313 #define AR71XX_DDR_DIV_MASK 0x3 314 #define AR71XX_AHB_DIV_SHIFT 20 315 #define AR71XX_AHB_DIV_MASK 0x7 316 317 #define AR71XX_ETH0_PLL_SHIFT 17 318 #define AR71XX_ETH1_PLL_SHIFT 19 319 320 #define AR724X_PLL_REG_CPU_CONFIG 0x00 321 #define AR724X_PLL_REG_PCIE_CONFIG 0x18 322 323 #define AR724X_PLL_DIV_SHIFT 0 324 #define AR724X_PLL_DIV_MASK 0x3ff 325 #define AR724X_PLL_REF_DIV_SHIFT 10 326 #define AR724X_PLL_REF_DIV_MASK 0xf 327 #define AR724X_AHB_DIV_SHIFT 19 328 #define AR724X_AHB_DIV_MASK 0x1 329 #define AR724X_DDR_DIV_SHIFT 22 330 #define AR724X_DDR_DIV_MASK 0x3 331 332 #define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c 333 334 #define AR913X_PLL_REG_CPU_CONFIG 0x00 335 #define AR913X_PLL_REG_ETH_CONFIG 0x04 336 #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 337 #define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 338 339 #define AR913X_PLL_DIV_SHIFT 0 340 #define AR913X_PLL_DIV_MASK 0x3ff 341 #define AR913X_DDR_DIV_SHIFT 22 342 #define AR913X_DDR_DIV_MASK 0x3 343 #define AR913X_AHB_DIV_SHIFT 19 344 #define AR913X_AHB_DIV_MASK 0x1 345 346 #define AR913X_ETH0_PLL_SHIFT 20 347 #define AR913X_ETH1_PLL_SHIFT 22 348 349 #define AR933X_PLL_CPU_CONFIG_REG 0x00 350 #define AR933X_PLL_CLK_CTRL_REG 0x08 351 #define AR933X_PLL_DITHER_FRAC_REG 0x10 352 #define AR933X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 353 354 #define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 355 #define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f 356 #define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 357 #define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 358 #define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 359 #define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 360 361 #define AR933X_PLL_CLK_CTRL_BYPASS BIT(2) 362 #define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 363 #define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x3 364 #define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 365 #define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x3 366 #define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 367 #define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x7 368 369 #define AR934X_PLL_CPU_CONFIG_REG 0x00 370 #define AR934X_PLL_DDR_CONFIG_REG 0x04 371 #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 372 #define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 373 #define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c 374 #define AR934X_PLL_DDR_DIT_FRAC_REG 0x44 375 #define AR934X_PLL_CPU_DIT_FRAC_REG 0x48 376 377 #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 378 #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f 379 #define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6 380 #define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f 381 #define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 382 #define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 383 #define AR934X_PLL_CPU_CONFIG_RANGE_SHIFT 17 384 #define AR934X_PLL_CPU_CONFIG_RANGE_MASK 0x3 385 #define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 386 #define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 387 #define AR934X_PLL_CPU_CONFIG_PLLPWD BIT(30) 388 #define AR934X_PLL_CPU_CONFIG_UPDATING BIT(31) 389 390 #define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 391 #define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff 392 #define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10 393 #define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f 394 #define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 395 #define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f 396 #define AR934X_PLL_DDR_CONFIG_RANGE_SHIFT 21 397 #define AR934X_PLL_DDR_CONFIG_RANGE_MASK 0x3 398 #define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 399 #define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 400 #define AR934X_PLL_DDR_CONFIG_PLLPWD BIT(30) 401 #define AR934X_PLL_DDR_CONFIG_UPDATING BIT(31) 402 403 #define AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) 404 #define AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) 405 #define AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) 406 #define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 407 #define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f 408 #define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 409 #define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f 410 #define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 411 #define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f 412 #define AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) 413 #define AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) 414 #define AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) 415 416 #define AR934X_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL BIT(6) 417 418 #define AR934X_PLL_DDR_DIT_FRAC_MAX_SHIFT 0 419 #define AR934X_PLL_DDR_DIT_FRAC_MAX_MASK 0x3ff 420 #define AR934X_PLL_DDR_DIT_FRAC_MIN_SHIFT 10 421 #define AR934X_PLL_DDR_DIT_FRAC_MIN_MASK 0x3ff 422 #define AR934X_PLL_DDR_DIT_FRAC_STEP_SHIFT 20 423 #define AR934X_PLL_DDR_DIT_FRAC_STEP_MASK 0x3f 424 #define AR934X_PLL_DDR_DIT_UPD_CNT_SHIFT 27 425 #define AR934X_PLL_DDR_DIT_UPD_CNT_MASK 0x3f 426 #define AR934X_PLL_DDR_DIT_DITHER_EN BIT(31) 427 428 #define AR934X_PLL_CPU_DIT_FRAC_MAX_SHIFT 0 429 #define AR934X_PLL_CPU_DIT_FRAC_MAX_MASK 0x3f 430 #define AR934X_PLL_CPU_DIT_FRAC_MIN_SHIFT 6 431 #define AR934X_PLL_CPU_DIT_FRAC_MIN_MASK 0x3f 432 #define AR934X_PLL_CPU_DIT_FRAC_STEP_SHIFT 12 433 #define AR934X_PLL_CPU_DIT_FRAC_STEP_MASK 0x3f 434 #define AR934X_PLL_CPU_DIT_UPD_CNT_SHIFT 18 435 #define AR934X_PLL_CPU_DIT_UPD_CNT_MASK 0x3f 436 #define AR934X_PLL_CPU_DIT_DITHER_EN BIT(31) 437 438 #define QCA953X_PLL_CPU_CONFIG_REG 0x00 439 #define QCA953X_PLL_DDR_CONFIG_REG 0x04 440 #define QCA953X_PLL_CLK_CTRL_REG 0x08 441 #define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 442 #define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c 443 #define QCA953X_PLL_DDR_DIT_FRAC_REG 0x44 444 #define QCA953X_PLL_CPU_DIT_FRAC_REG 0x48 445 446 #define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 447 #define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f 448 #define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6 449 #define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f 450 #define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 451 #define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 452 #define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 453 #define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 454 455 #define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 456 #define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff 457 #define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10 458 #define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f 459 #define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 460 #define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f 461 #define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 462 #define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 463 464 #define QCA953X_PLL_CONFIG_PWD BIT(30) 465 466 #define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) 467 #define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) 468 #define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) 469 #define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 470 #define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f 471 #define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 472 #define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f 473 #define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 474 #define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f 475 #define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) 476 #define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) 477 #define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) 478 479 #define QCA953X_PLL_CPU_DIT_FRAC_MAX_SHIFT 0 480 #define QCA953X_PLL_CPU_DIT_FRAC_MAX_MASK 0x3f 481 #define QCA953X_PLL_CPU_DIT_FRAC_MIN_SHIFT 6 482 #define QCA953X_PLL_CPU_DIT_FRAC_MIN_MASK 0x3f 483 #define QCA953X_PLL_CPU_DIT_FRAC_STEP_SHIFT 12 484 #define QCA953X_PLL_CPU_DIT_FRAC_STEP_MASK 0x3f 485 #define QCA953X_PLL_CPU_DIT_UPD_CNT_SHIFT 18 486 #define QCA953X_PLL_CPU_DIT_UPD_CNT_MASK 0x3f 487 488 #define QCA953X_PLL_DDR_DIT_FRAC_MAX_SHIFT 0 489 #define QCA953X_PLL_DDR_DIT_FRAC_MAX_MASK 0x3ff 490 #define QCA953X_PLL_DDR_DIT_FRAC_MIN_SHIFT 9 491 #define QCA953X_PLL_DDR_DIT_FRAC_MIN_MASK 0x3ff 492 #define QCA953X_PLL_DDR_DIT_FRAC_STEP_SHIFT 20 493 #define QCA953X_PLL_DDR_DIT_FRAC_STEP_MASK 0x3f 494 #define QCA953X_PLL_DDR_DIT_UPD_CNT_SHIFT 27 495 #define QCA953X_PLL_DDR_DIT_UPD_CNT_MASK 0x3f 496 497 #define QCA953X_PLL_DIT_FRAC_EN BIT(31) 498 499 #define QCA955X_PLL_CPU_CONFIG_REG 0x00 500 #define QCA955X_PLL_DDR_CONFIG_REG 0x04 501 #define QCA955X_PLL_CLK_CTRL_REG 0x08 502 #define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 503 #define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 504 505 #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 506 #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f 507 #define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 508 #define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f 509 #define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 510 #define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 511 #define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 512 #define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 513 514 #define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 515 #define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff 516 #define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 517 #define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f 518 #define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 519 #define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f 520 #define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 521 #define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 522 523 #define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) 524 #define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) 525 #define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) 526 #define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 527 #define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f 528 #define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 529 #define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f 530 #define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 531 #define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f 532 #define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) 533 #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) 534 #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) 535 536 #define QCA956X_PLL_CPU_CONFIG_REG 0x00 537 #define QCA956X_PLL_CPU_CONFIG1_REG 0x04 538 #define QCA956X_PLL_DDR_CONFIG_REG 0x08 539 #define QCA956X_PLL_DDR_CONFIG1_REG 0x0c 540 #define QCA956X_PLL_CLK_CTRL_REG 0x10 541 #define QCA956X_PLL_SWITCH_CLK_CTRL_REG 0x28 542 #define QCA956X_PLL_ETH_XMII_CTRL_REG 0x30 543 #define QCA956X_PLL_DDR_DIT_FRAC_REG 0x38 544 #define QCA956X_PLL_DDR_DIT2_FRAC_REG 0x3c 545 #define QCA956X_PLL_CPU_DIT_FRAC_REG 0x40 546 #define QCA956X_PLL_CPU_DIT2_FRAC_REG 0x44 547 #define QCA956X_PLL_ETH_SGMII_SERDES_REG 0x4c 548 549 #define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 550 #define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 551 #define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 552 #define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 553 554 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0 555 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f 556 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5 557 #define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff 558 #define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18 559 #define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff 560 561 #define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 562 #define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f 563 #define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 564 #define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 565 566 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0 567 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f 568 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5 569 #define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff 570 #define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18 571 #define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff 572 573 #define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) 574 #define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) 575 #define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) 576 #define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 577 #define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f 578 #define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 579 #define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f 580 #define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 581 #define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f 582 #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20) 583 #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21) 584 #define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) 585 586 /* 587 * USB_CONFIG block 588 */ 589 #define AR71XX_USB_CTRL_REG_FLADJ 0x00 590 #define AR71XX_USB_CTRL_REG_CONFIG 0x04 591 592 /* 593 * RESET block 594 */ 595 #define AR71XX_RESET_REG_TIMER 0x00 596 #define AR71XX_RESET_REG_TIMER_RELOAD 0x04 597 #define AR71XX_RESET_REG_WDOG_CTRL 0x08 598 #define AR71XX_RESET_REG_WDOG 0x0c 599 #define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 600 #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 601 #define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 602 #define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c 603 #define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 604 #define AR71XX_RESET_REG_RESET_MODULE 0x24 605 #define AR71XX_RESET_REG_PERFC_CTRL 0x2c 606 #define AR71XX_RESET_REG_PERFC0 0x30 607 #define AR71XX_RESET_REG_PERFC1 0x34 608 #define AR71XX_RESET_REG_REV_ID 0x90 609 610 #define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 611 #define AR913X_RESET_REG_RESET_MODULE 0x1c 612 #define AR913X_RESET_REG_PERF_CTRL 0x20 613 #define AR913X_RESET_REG_PERFC0 0x24 614 #define AR913X_RESET_REG_PERFC1 0x28 615 616 #define AR724X_RESET_REG_RESET_MODULE 0x1c 617 618 #define AR933X_RESET_REG_RESET_MODULE 0x1c 619 #define AR933X_RESET_REG_BOOTSTRAP 0xac 620 621 #define AR934X_RESET_REG_RESET_MODULE 0x1c 622 #define AR934X_RESET_REG_BOOTSTRAP 0xb0 623 #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac 624 625 #define QCA953X_RESET_REG_RESET_MODULE 0x1c 626 #define QCA953X_RESET_REG_BOOTSTRAP 0xb0 627 #define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac 628 629 #define QCA955X_RESET_REG_RESET_MODULE 0x1c 630 #define QCA955X_RESET_REG_BOOTSTRAP 0xb0 631 #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac 632 633 #define QCA956X_RESET_REG_RESET_MODULE 0x1c 634 #define QCA956X_RESET_REG_BOOTSTRAP 0xb0 635 #define QCA956X_RESET_REG_EXT_INT_STATUS 0xac 636 637 #define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28) 638 #define MISC_INT_ETHSW BIT(12) 639 #define MISC_INT_TIMER4 BIT(10) 640 #define MISC_INT_TIMER3 BIT(9) 641 #define MISC_INT_TIMER2 BIT(8) 642 #define MISC_INT_DMA BIT(7) 643 #define MISC_INT_OHCI BIT(6) 644 #define MISC_INT_PERFC BIT(5) 645 #define MISC_INT_WDOG BIT(4) 646 #define MISC_INT_UART BIT(3) 647 #define MISC_INT_GPIO BIT(2) 648 #define MISC_INT_ERROR BIT(1) 649 #define MISC_INT_TIMER BIT(0) 650 651 #define AR71XX_RESET_EXTERNAL BIT(28) 652 #define AR71XX_RESET_FULL_CHIP BIT(24) 653 #define AR71XX_RESET_CPU_NMI BIT(21) 654 #define AR71XX_RESET_CPU_COLD BIT(20) 655 #define AR71XX_RESET_DMA BIT(19) 656 #define AR71XX_RESET_SLIC BIT(18) 657 #define AR71XX_RESET_STEREO BIT(17) 658 #define AR71XX_RESET_DDR BIT(16) 659 #define AR71XX_RESET_GE1_MAC BIT(13) 660 #define AR71XX_RESET_GE1_PHY BIT(12) 661 #define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) 662 #define AR71XX_RESET_GE0_MAC BIT(9) 663 #define AR71XX_RESET_GE0_PHY BIT(8) 664 #define AR71XX_RESET_USB_OHCI_DLL BIT(6) 665 #define AR71XX_RESET_USB_HOST BIT(5) 666 #define AR71XX_RESET_USB_PHY BIT(4) 667 #define AR71XX_RESET_PCI_BUS BIT(1) 668 #define AR71XX_RESET_PCI_CORE BIT(0) 669 670 #define AR7240_RESET_USB_HOST BIT(5) 671 #define AR7240_RESET_OHCI_DLL BIT(3) 672 673 #define AR724X_RESET_GE1_MDIO BIT(23) 674 #define AR724X_RESET_GE0_MDIO BIT(22) 675 #define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) 676 #define AR724X_RESET_PCIE_PHY BIT(7) 677 #define AR724X_RESET_PCIE BIT(6) 678 #define AR724X_RESET_USB_HOST BIT(5) 679 #define AR724X_RESET_USB_PHY BIT(4) 680 #define AR724X_RESET_USBSUS_OVERRIDE BIT(3) 681 682 #define AR913X_RESET_AMBA2WMAC BIT(22) 683 #define AR913X_RESET_USBSUS_OVERRIDE BIT(10) 684 #define AR913X_RESET_USB_HOST BIT(5) 685 #define AR913X_RESET_USB_PHY BIT(4) 686 687 #define AR933X_RESET_GE1_MDIO BIT(23) 688 #define AR933X_RESET_GE0_MDIO BIT(22) 689 #define AR933X_RESET_ETH_SWITCH_ANALOG BIT(14) 690 #define AR933X_RESET_GE1_MAC BIT(13) 691 #define AR933X_RESET_WMAC BIT(11) 692 #define AR933X_RESET_GE0_MAC BIT(9) 693 #define AR933X_RESET_ETH_SWITCH BIT(8) 694 #define AR933X_RESET_USB_HOST BIT(5) 695 #define AR933X_RESET_USB_PHY BIT(4) 696 #define AR933X_RESET_USBSUS_OVERRIDE BIT(3) 697 698 #define AR934X_RESET_HOST BIT(31) 699 #define AR934X_RESET_SLIC BIT(30) 700 #define AR934X_RESET_HDMA BIT(29) 701 #define AR934X_RESET_EXTERNAL BIT(28) 702 #define AR934X_RESET_RTC BIT(27) 703 #define AR934X_RESET_PCIE_EP_INT BIT(26) 704 #define AR934X_RESET_CHKSUM_ACC BIT(25) 705 #define AR934X_RESET_FULL_CHIP BIT(24) 706 #define AR934X_RESET_GE1_MDIO BIT(23) 707 #define AR934X_RESET_GE0_MDIO BIT(22) 708 #define AR934X_RESET_CPU_NMI BIT(21) 709 #define AR934X_RESET_CPU_COLD BIT(20) 710 #define AR934X_RESET_HOST_RESET_INT BIT(19) 711 #define AR934X_RESET_PCIE_EP BIT(18) 712 #define AR934X_RESET_UART1 BIT(17) 713 #define AR934X_RESET_DDR BIT(16) 714 #define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) 715 #define AR934X_RESET_NANDF BIT(14) 716 #define AR934X_RESET_GE1_MAC BIT(13) 717 #define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) 718 #define AR934X_RESET_USB_PHY_ANALOG BIT(11) 719 #define AR934X_RESET_HOST_DMA_INT BIT(10) 720 #define AR934X_RESET_GE0_MAC BIT(9) 721 #define AR934X_RESET_ETH_SWITCH BIT(8) 722 #define AR934X_RESET_PCIE_PHY BIT(7) 723 #define AR934X_RESET_PCIE BIT(6) 724 #define AR934X_RESET_USB_HOST BIT(5) 725 #define AR934X_RESET_USB_PHY BIT(4) 726 #define AR934X_RESET_USBSUS_OVERRIDE BIT(3) 727 #define AR934X_RESET_LUT BIT(2) 728 #define AR934X_RESET_MBOX BIT(1) 729 #define AR934X_RESET_I2S BIT(0) 730 731 #define QCA953X_RESET_USB_EXT_PWR BIT(29) 732 #define QCA953X_RESET_EXTERNAL BIT(28) 733 #define QCA953X_RESET_RTC BIT(27) 734 #define QCA953X_RESET_FULL_CHIP BIT(24) 735 #define QCA953X_RESET_GE1_MDIO BIT(23) 736 #define QCA953X_RESET_GE0_MDIO BIT(22) 737 #define QCA953X_RESET_CPU_NMI BIT(21) 738 #define QCA953X_RESET_CPU_COLD BIT(20) 739 #define QCA953X_RESET_DDR BIT(16) 740 #define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) 741 #define QCA953X_RESET_GE1_MAC BIT(13) 742 #define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12) 743 #define QCA953X_RESET_USB_PHY_ANALOG BIT(11) 744 #define QCA953X_RESET_GE0_MAC BIT(9) 745 #define QCA953X_RESET_ETH_SWITCH BIT(8) 746 #define QCA953X_RESET_PCIE_PHY BIT(7) 747 #define QCA953X_RESET_PCIE BIT(6) 748 #define QCA953X_RESET_USB_HOST BIT(5) 749 #define QCA953X_RESET_USB_PHY BIT(4) 750 #define QCA953X_RESET_USBSUS_OVERRIDE BIT(3) 751 752 #define QCA955X_RESET_HOST BIT(31) 753 #define QCA955X_RESET_SLIC BIT(30) 754 #define QCA955X_RESET_HDMA BIT(29) 755 #define QCA955X_RESET_EXTERNAL BIT(28) 756 #define QCA955X_RESET_RTC BIT(27) 757 #define QCA955X_RESET_PCIE_EP_INT BIT(26) 758 #define QCA955X_RESET_CHKSUM_ACC BIT(25) 759 #define QCA955X_RESET_FULL_CHIP BIT(24) 760 #define QCA955X_RESET_GE1_MDIO BIT(23) 761 #define QCA955X_RESET_GE0_MDIO BIT(22) 762 #define QCA955X_RESET_CPU_NMI BIT(21) 763 #define QCA955X_RESET_CPU_COLD BIT(20) 764 #define QCA955X_RESET_HOST_RESET_INT BIT(19) 765 #define QCA955X_RESET_PCIE_EP BIT(18) 766 #define QCA955X_RESET_UART1 BIT(17) 767 #define QCA955X_RESET_DDR BIT(16) 768 #define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) 769 #define QCA955X_RESET_NANDF BIT(14) 770 #define QCA955X_RESET_GE1_MAC BIT(13) 771 #define QCA955X_RESET_SGMII_ANALOG BIT(12) 772 #define QCA955X_RESET_USB_PHY_ANALOG BIT(11) 773 #define QCA955X_RESET_HOST_DMA_INT BIT(10) 774 #define QCA955X_RESET_GE0_MAC BIT(9) 775 #define QCA955X_RESET_SGMII BIT(8) 776 #define QCA955X_RESET_PCIE_PHY BIT(7) 777 #define QCA955X_RESET_PCIE BIT(6) 778 #define QCA955X_RESET_USB_HOST BIT(5) 779 #define QCA955X_RESET_USB_PHY BIT(4) 780 #define QCA955X_RESET_USBSUS_OVERRIDE BIT(3) 781 #define QCA955X_RESET_LUT BIT(2) 782 #define QCA955X_RESET_MBOX BIT(1) 783 #define QCA955X_RESET_I2S BIT(0) 784 785 #define QCA956X_RESET_EXTERNAL BIT(28) 786 #define QCA956X_RESET_FULL_CHIP BIT(24) 787 #define QCA956X_RESET_GE1_MDIO BIT(23) /* Reserved in datasheet */ 788 #define QCA956X_RESET_GE0_MDIO BIT(22) 789 #define QCA956X_RESET_GE1_MAC BIT(13) /* Reserved in datasheet */ 790 #define QCA956X_RESET_SGMII_ASSERT BIT(12) 791 #define QCA956X_RESET_GE0_MAC BIT(9) 792 #define QCA956X_RESET_SGMII BIT(8) 793 #define QCA956X_RESET_SGMII_ANALOG BIT(2) 794 #define QCA956X_RESET_SWITCH BIT(0) 795 796 #define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) 797 #define AR933X_BOOTSTRAP_DDR2 BIT(13) 798 #define AR933X_BOOTSTRAP_EEPBUSY BIT(4) 799 #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) 800 801 #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) 802 #define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) 803 #define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) 804 #define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) 805 #define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) 806 #define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) 807 #define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) 808 #define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) 809 #define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) 810 #define AR934X_BOOTSTRAP_PCIE_RC BIT(6) 811 #define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) 812 #define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) 813 #define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) 814 #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) 815 #define AR934X_BOOTSTRAP_DDR1 BIT(0) 816 817 #define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12) 818 #define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11) 819 #define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5) 820 #define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4) 821 #define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1) 822 #define QCA953X_BOOTSTRAP_DDR1 BIT(0) 823 824 #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) 825 826 #define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2) 827 828 #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) 829 #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) 830 #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) 831 #define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) 832 #define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) 833 #define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) 834 #define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) 835 #define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) 836 #define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) 837 #define AR934X_PCIE_WMAC_INT_WMAC_ALL \ 838 (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \ 839 AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP) 840 841 #define AR934X_PCIE_WMAC_INT_PCIE_ALL \ 842 (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \ 843 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ 844 AR934X_PCIE_WMAC_INT_PCIE_RC3) 845 846 #define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0) 847 #define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1) 848 #define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) 849 #define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) 850 #define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4) 851 #define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) 852 #define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) 853 #define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) 854 #define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) 855 #define QCA953X_PCIE_WMAC_INT_WMAC_ALL \ 856 (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \ 857 QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP) 858 859 #define QCA953X_PCIE_WMAC_INT_PCIE_ALL \ 860 (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \ 861 QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \ 862 QCA953X_PCIE_WMAC_INT_PCIE_RC3) 863 864 #define QCA955X_EXT_INT_WMAC_MISC BIT(0) 865 #define QCA955X_EXT_INT_WMAC_TX BIT(1) 866 #define QCA955X_EXT_INT_WMAC_RXLP BIT(2) 867 #define QCA955X_EXT_INT_WMAC_RXHP BIT(3) 868 #define QCA955X_EXT_INT_PCIE_RC1 BIT(4) 869 #define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) 870 #define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) 871 #define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) 872 #define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) 873 #define QCA955X_EXT_INT_PCIE_RC2 BIT(12) 874 #define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) 875 #define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) 876 #define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) 877 #define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) 878 #define QCA955X_EXT_INT_USB1 BIT(24) 879 #define QCA955X_EXT_INT_USB2 BIT(28) 880 881 #define QCA955X_EXT_INT_WMAC_ALL \ 882 (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ 883 QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP) 884 885 #define QCA955X_EXT_INT_PCIE_RC1_ALL \ 886 (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \ 887 QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \ 888 QCA955X_EXT_INT_PCIE_RC1_INT3) 889 890 #define QCA955X_EXT_INT_PCIE_RC2_ALL \ 891 (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \ 892 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ 893 QCA955X_EXT_INT_PCIE_RC2_INT3) 894 895 #define QCA956X_EXT_INT_WMAC_MISC BIT(0) 896 #define QCA956X_EXT_INT_WMAC_TX BIT(1) 897 #define QCA956X_EXT_INT_WMAC_RXLP BIT(2) 898 #define QCA956X_EXT_INT_WMAC_RXHP BIT(3) 899 #define QCA956X_EXT_INT_PCIE_RC1 BIT(4) 900 #define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5) 901 #define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6) 902 #define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7) 903 #define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8) 904 #define QCA956X_EXT_INT_PCIE_RC2 BIT(12) 905 #define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13) 906 #define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14) 907 #define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15) 908 #define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16) 909 #define QCA956X_EXT_INT_USB1 BIT(24) 910 #define QCA956X_EXT_INT_USB2 BIT(28) 911 912 #define QCA956X_EXT_INT_WMAC_ALL \ 913 (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \ 914 QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP) 915 916 #define QCA956X_EXT_INT_PCIE_RC1_ALL \ 917 (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \ 918 QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \ 919 QCA956X_EXT_INT_PCIE_RC1_INT3) 920 921 #define QCA956X_EXT_INT_PCIE_RC2_ALL \ 922 (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \ 923 QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \ 924 QCA956X_EXT_INT_PCIE_RC2_INT3) 925 926 #define REV_ID_MAJOR_MASK 0xfff0 927 #define REV_ID_MAJOR_AR71XX 0x00a0 928 #define REV_ID_MAJOR_AR913X 0x00b0 929 #define REV_ID_MAJOR_AR7240 0x00c0 930 #define REV_ID_MAJOR_AR7241 0x0100 931 #define REV_ID_MAJOR_AR7242 0x1100 932 #define REV_ID_MAJOR_AR9330 0x0110 933 #define REV_ID_MAJOR_AR9331 0x1110 934 #define REV_ID_MAJOR_AR9341 0x0120 935 #define REV_ID_MAJOR_AR9342 0x1120 936 #define REV_ID_MAJOR_AR9344 0x2120 937 #define REV_ID_MAJOR_QCA9533 0x0140 938 #define REV_ID_MAJOR_QCA9533_V2 0x0160 939 #define REV_ID_MAJOR_QCA9556 0x0130 940 #define REV_ID_MAJOR_QCA9558 0x1130 941 #define REV_ID_MAJOR_TP9343 0x0150 942 #define REV_ID_MAJOR_QCA9561 0x1150 943 944 #define AR71XX_REV_ID_MINOR_MASK 0x3 945 #define AR71XX_REV_ID_MINOR_AR7130 0x0 946 #define AR71XX_REV_ID_MINOR_AR7141 0x1 947 #define AR71XX_REV_ID_MINOR_AR7161 0x2 948 #define AR913X_REV_ID_MINOR_AR9130 0x0 949 #define AR913X_REV_ID_MINOR_AR9132 0x1 950 951 #define AR71XX_REV_ID_REVISION_MASK 0x3 952 #define AR71XX_REV_ID_REVISION_SHIFT 2 953 #define AR71XX_REV_ID_REVISION2_MASK 0xf 954 955 /* 956 * RTC block 957 */ 958 #define AR933X_RTC_REG_RESET 0x40 959 #define AR933X_RTC_REG_STATUS 0x44 960 #define AR933X_RTC_REG_DERIVED 0x48 961 #define AR933X_RTC_REG_FORCE_WAKE 0x4c 962 #define AR933X_RTC_REG_INT_CAUSE 0x50 963 #define AR933X_RTC_REG_CAUSE_CLR 0x50 964 #define AR933X_RTC_REG_INT_ENABLE 0x54 965 #define AR933X_RTC_REG_INT_MASKE 0x58 966 967 #define QCA953X_RTC_REG_SYNC_RESET 0x40 968 #define QCA953X_RTC_REG_SYNC_STATUS 0x44 969 970 /* 971 * SPI block 972 */ 973 #define AR71XX_SPI_REG_FS 0x00 974 #define AR71XX_SPI_REG_CTRL 0x04 975 #define AR71XX_SPI_REG_IOC 0x08 976 #define AR71XX_SPI_REG_RDS 0x0c 977 978 #define AR71XX_SPI_FS_GPIO BIT(0) 979 980 #define AR71XX_SPI_CTRL_RD BIT(6) 981 #define AR71XX_SPI_CTRL_DIV_MASK 0x3f 982 983 #define AR71XX_SPI_IOC_DO BIT(0) 984 #define AR71XX_SPI_IOC_CLK BIT(8) 985 #define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) 986 #define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) 987 #define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) 988 #define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) 989 #define AR71XX_SPI_IOC_CS_ALL \ 990 (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | AR71XX_SPI_IOC_CS2) 991 992 /* 993 * GPIO block 994 */ 995 #define AR71XX_GPIO_REG_OE 0x00 996 #define AR71XX_GPIO_REG_IN 0x04 997 #define AR71XX_GPIO_REG_OUT 0x08 998 #define AR71XX_GPIO_REG_SET 0x0c 999 #define AR71XX_GPIO_REG_CLEAR 0x10 1000 #define AR71XX_GPIO_REG_INT_MODE 0x14 1001 #define AR71XX_GPIO_REG_INT_TYPE 0x18 1002 #define AR71XX_GPIO_REG_INT_POLARITY 0x1c 1003 #define AR71XX_GPIO_REG_INT_PENDING 0x20 1004 #define AR71XX_GPIO_REG_INT_ENABLE 0x24 1005 #define AR71XX_GPIO_REG_FUNC 0x28 1006 #define AR933X_GPIO_REG_FUNC 0x30 1007 1008 #define AR934X_GPIO_REG_OUT_FUNC0 0x2c 1009 #define AR934X_GPIO_REG_OUT_FUNC1 0x30 1010 #define AR934X_GPIO_REG_OUT_FUNC2 0x34 1011 #define AR934X_GPIO_REG_OUT_FUNC3 0x38 1012 #define AR934X_GPIO_REG_OUT_FUNC4 0x3c 1013 #define AR934X_GPIO_REG_OUT_FUNC5 0x40 1014 #define AR934X_GPIO_REG_FUNC 0x6c 1015 1016 #define QCA953X_GPIO_REG_OUT_FUNC0 0x2c 1017 #define QCA953X_GPIO_REG_OUT_FUNC1 0x30 1018 #define QCA953X_GPIO_REG_OUT_FUNC2 0x34 1019 #define QCA953X_GPIO_REG_OUT_FUNC3 0x38 1020 #define QCA953X_GPIO_REG_OUT_FUNC4 0x3c 1021 #define QCA953X_GPIO_REG_IN_ENABLE0 0x44 1022 #define QCA953X_GPIO_REG_FUNC 0x6c 1023 1024 #define QCA955X_GPIO_REG_OUT_FUNC0 0x2c 1025 #define QCA955X_GPIO_REG_OUT_FUNC1 0x30 1026 #define QCA955X_GPIO_REG_OUT_FUNC2 0x34 1027 #define QCA955X_GPIO_REG_OUT_FUNC3 0x38 1028 #define QCA955X_GPIO_REG_OUT_FUNC4 0x3c 1029 #define QCA955X_GPIO_REG_OUT_FUNC5 0x40 1030 #define QCA955X_GPIO_REG_FUNC 0x6c 1031 1032 #define QCA956X_GPIO_REG_OUT_FUNC0 0x2c 1033 #define QCA956X_GPIO_REG_OUT_FUNC1 0x30 1034 #define QCA956X_GPIO_REG_OUT_FUNC2 0x34 1035 #define QCA956X_GPIO_REG_OUT_FUNC3 0x38 1036 #define QCA956X_GPIO_REG_OUT_FUNC4 0x3c 1037 #define QCA956X_GPIO_REG_OUT_FUNC5 0x40 1038 #define QCA956X_GPIO_REG_IN_ENABLE0 0x44 1039 #define QCA956X_GPIO_REG_IN_ENABLE3 0x50 1040 #define QCA956X_GPIO_REG_FUNC 0x6c 1041 1042 #define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) 1043 #define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) 1044 #define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) 1045 #define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) 1046 #define AR71XX_GPIO_FUNC_UART_EN BIT(8) 1047 #define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) 1048 #define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) 1049 1050 #define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) 1051 #define AR724X_GPIO_FUNC_SPI_EN BIT(18) 1052 #define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) 1053 #define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) 1054 #define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) 1055 #define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) 1056 #define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) 1057 #define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) 1058 #define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) 1059 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) 1060 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) 1061 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) 1062 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) 1063 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) 1064 #define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) 1065 #define AR724X_GPIO_FUNC_UART_EN BIT(1) 1066 #define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) 1067 1068 #define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) 1069 #define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) 1070 #define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) 1071 #define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) 1072 #define AR913X_GPIO_FUNC_I2S1_EN BIT(18) 1073 #define AR913X_GPIO_FUNC_I2S0_EN BIT(17) 1074 #define AR913X_GPIO_FUNC_SLIC_EN BIT(16) 1075 #define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) 1076 #define AR913X_GPIO_FUNC_UART_EN BIT(8) 1077 #define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) 1078 1079 #define AR933X_GPIO(x) BIT(x) 1080 #define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) 1081 #define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) 1082 #define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) 1083 #define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) 1084 #define AR933X_GPIO_FUNC_I2SO_EN BIT(26) 1085 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) 1086 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) 1087 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) 1088 #define AR933X_GPIO_FUNC_SPI_EN BIT(18) 1089 #define AR933X_GPIO_FUNC_RES_TRUE BIT(15) 1090 #define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) 1091 #define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) 1092 #define AR933X_GPIO_FUNC_XLNA_EN BIT(12) 1093 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) 1094 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) 1095 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) 1096 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) 1097 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) 1098 #define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) 1099 #define AR933X_GPIO_FUNC_UART_EN BIT(1) 1100 #define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) 1101 1102 #define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9) 1103 #define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8) 1104 #define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7) 1105 #define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6) 1106 #define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5) 1107 #define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4) 1108 #define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3) 1109 #define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2) 1110 #define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1) 1111 1112 #define AR934X_GPIO_OUT_GPIO 0 1113 #define AR934X_GPIO_OUT_SPI_CS1 7 1114 #define AR934X_GPIO_OUT_LED_LINK0 41 1115 #define AR934X_GPIO_OUT_LED_LINK1 42 1116 #define AR934X_GPIO_OUT_LED_LINK2 43 1117 #define AR934X_GPIO_OUT_LED_LINK3 44 1118 #define AR934X_GPIO_OUT_LED_LINK4 45 1119 #define AR934X_GPIO_OUT_EXT_LNA0 46 1120 #define AR934X_GPIO_OUT_EXT_LNA1 47 1121 1122 #define QCA953X_GPIO(x) BIT(x) 1123 #define QCA953X_GPIO_MUX_MASK(x) (0xff << (x)) 1124 #define QCA953X_GPIO_OUT_MUX_SPI_CS1 10 1125 #define QCA953X_GPIO_OUT_MUX_SPI_CS2 11 1126 #define QCA953X_GPIO_OUT_MUX_SPI_CS0 9 1127 #define QCA953X_GPIO_OUT_MUX_SPI_CLK 8 1128 #define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12 1129 #define QCA953X_GPIO_OUT_MUX_UART0_SOUT 22 1130 #define QCA953X_GPIO_OUT_MUX_LED_LINK1 41 1131 #define QCA953X_GPIO_OUT_MUX_LED_LINK2 42 1132 #define QCA953X_GPIO_OUT_MUX_LED_LINK3 43 1133 #define QCA953X_GPIO_OUT_MUX_LED_LINK4 44 1134 #define QCA953X_GPIO_OUT_MUX_LED_LINK5 45 1135 1136 #define QCA953X_GPIO_IN_MUX_UART0_SIN 9 1137 #define QCA953X_GPIO_IN_MUX_SPI_DATA_IN 8 1138 1139 #define QCA956X_GPIO(x) BIT(x) 1140 #define QCA956X_GPIO_MUX_MASK(x) (0xff << (x)) 1141 #define QCA956X_GPIO_OUT_MUX_GE0_MDO 32 1142 #define QCA956X_GPIO_OUT_MUX_GE0_MDC 33 1143 #define QCA956X_GPIO_IN_MUX_UART0_SIN 0x12 1144 #define QCA956X_GPIO_OUT_MUX_UART0_SOUT 0x16 1145 1146 #define AR71XX_GPIO_COUNT 16 1147 #define AR7240_GPIO_COUNT 18 1148 #define AR7241_GPIO_COUNT 20 1149 #define AR913X_GPIO_COUNT 22 1150 #define AR933X_GPIO_COUNT 30 1151 #define AR934X_GPIO_COUNT 23 1152 #define QCA953X_GPIO_COUNT 18 1153 #define QCA955X_GPIO_COUNT 24 1154 #define QCA956X_GPIO_COUNT 23 1155 1156 /* 1157 * SRIF block 1158 */ 1159 #define AR933X_SRIF_DDR_DPLL1_REG 0x240 1160 #define AR933X_SRIF_DDR_DPLL2_REG 0x244 1161 #define AR933X_SRIF_DDR_DPLL3_REG 0x248 1162 #define AR933X_SRIF_DDR_DPLL4_REG 0x24c 1163 1164 #define AR934X_SRIF_CPU_DPLL1_REG 0x1c0 1165 #define AR934X_SRIF_CPU_DPLL2_REG 0x1c4 1166 #define AR934X_SRIF_CPU_DPLL3_REG 0x1c8 1167 #define AR934X_SRIF_CPU_DPLL4_REG 0x1cc 1168 1169 #define AR934X_SRIF_DDR_DPLL1_REG 0x240 1170 #define AR934X_SRIF_DDR_DPLL2_REG 0x244 1171 #define AR934X_SRIF_DDR_DPLL3_REG 0x248 1172 #define AR934X_SRIF_DDR_DPLL4_REG 0x24c 1173 1174 #define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27 1175 #define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f 1176 #define AR934X_SRIF_DPLL1_NINT_SHIFT 18 1177 #define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff 1178 #define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff 1179 1180 #define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30) 1181 #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 1182 #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 1183 1184 #define QCA953X_SRIF_BB_DPLL1_REG 0x180 1185 #define QCA953X_SRIF_BB_DPLL2_REG 0x184 1186 #define QCA953X_SRIF_BB_DPLL3_REG 0x188 1187 1188 #define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0 1189 #define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4 1190 #define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8 1191 1192 #define QCA953X_SRIF_DDR_DPLL1_REG 0x240 1193 #define QCA953X_SRIF_DDR_DPLL2_REG 0x244 1194 #define QCA953X_SRIF_DDR_DPLL3_REG 0x248 1195 1196 #define QCA953X_SRIF_PCIE_DPLL1_REG 0xc00 1197 #define QCA953X_SRIF_PCIE_DPLL2_REG 0xc04 1198 #define QCA953X_SRIF_PCIE_DPLL3_REG 0xc08 1199 1200 #define QCA953X_SRIF_PMU1_REG 0xc40 1201 #define QCA953X_SRIF_PMU2_REG 0xc44 1202 1203 #define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27 1204 #define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f 1205 1206 #define QCA953X_SRIF_DPLL1_NINT_SHIFT 18 1207 #define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff 1208 #define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff 1209 1210 #define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30) 1211 1212 #define QCA953X_SRIF_DPLL2_KI_SHIFT 29 1213 #define QCA953X_SRIF_DPLL2_KI_MASK 0x3 1214 1215 #define QCA953X_SRIF_DPLL2_KD_SHIFT 25 1216 #define QCA953X_SRIF_DPLL2_KD_MASK 0xf 1217 1218 #define QCA953X_SRIF_DPLL2_PWD BIT(22) 1219 1220 #define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13 1221 #define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7 1222 1223 #define QCA956X_SRIF_BB_DPLL1_REG 0x180 1224 #define QCA956X_SRIF_BB_DPLL2_REG 0x184 1225 #define QCA956X_SRIF_BB_DPLL3_REG 0x188 1226 1227 #define QCA956X_SRIF_CPU_DPLL1_REG 0xf00 1228 #define QCA956X_SRIF_CPU_DPLL2_REG 0xf04 1229 #define QCA956X_SRIF_CPU_DPLL3_REG 0xf08 1230 1231 #define QCA956X_SRIF_DDR_DPLL1_REG 0xec0 1232 #define QCA956X_SRIF_DDR_DPLL2_REG 0xec4 1233 #define QCA956X_SRIF_DDR_DPLL3_REG 0xec8 1234 1235 #define QCA956X_SRIF_PCIE_DPLL1_REG 0xc80 1236 #define QCA956X_SRIF_PCIE_DPLL2_REG 0xc84 1237 #define QCA956X_SRIF_PCIE_DPLL3_REG 0xc88 1238 1239 #define QCA956X_SRIF_PMU1_REG 0xcc0 1240 #define QCA956X_SRIF_PMU2_REG 0xcc4 1241 1242 /* 1243 * MII_CTRL block 1244 */ 1245 #define AR71XX_MII_REG_MII0_CTRL 0x00 1246 #define AR71XX_MII_REG_MII1_CTRL 0x04 1247 1248 #define AR71XX_MII_CTRL_IF_MASK 3 1249 #define AR71XX_MII_CTRL_SPEED_SHIFT 4 1250 #define AR71XX_MII_CTRL_SPEED_MASK 3 1251 #define AR71XX_MII_CTRL_SPEED_10 0 1252 #define AR71XX_MII_CTRL_SPEED_100 1 1253 #define AR71XX_MII_CTRL_SPEED_1000 2 1254 1255 #define AR71XX_MII0_CTRL_IF_GMII 0 1256 #define AR71XX_MII0_CTRL_IF_MII 1 1257 #define AR71XX_MII0_CTRL_IF_RGMII 2 1258 #define AR71XX_MII0_CTRL_IF_RMII 3 1259 1260 #define AR71XX_MII1_CTRL_IF_RGMII 0 1261 #define AR71XX_MII1_CTRL_IF_RMII 1 1262 1263 /* 1264 * AR933X GMAC interface 1265 */ 1266 #define AR933X_GMAC_REG_ETH_CFG 0x00 1267 1268 #define AR933X_ETH_CFG_RGMII_GE0 BIT(0) 1269 #define AR933X_ETH_CFG_MII_GE0 BIT(1) 1270 #define AR933X_ETH_CFG_GMII_GE0 BIT(2) 1271 #define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) 1272 #define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) 1273 #define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) 1274 #define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) 1275 #define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) 1276 #define AR933X_ETH_CFG_RMII_GE0 BIT(9) 1277 #define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 1278 #define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) 1279 1280 /* 1281 * AR934X GMAC Interface 1282 */ 1283 #define AR934X_GMAC_REG_ETH_CFG 0x00 1284 1285 #define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) 1286 #define AR934X_ETH_CFG_MII_GMAC0 BIT(1) 1287 #define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) 1288 #define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) 1289 #define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) 1290 #define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) 1291 #define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) 1292 #define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) 1293 #define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) 1294 #define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) 1295 #define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) 1296 #define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) 1297 #define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) 1298 #define AR934X_ETH_CFG_RXD_DELAY BIT(14) 1299 #define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3 1300 #define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14 1301 #define AR934X_ETH_CFG_RDV_DELAY BIT(16) 1302 #define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3 1303 #define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 1304 1305 /* 1306 * QCA953X GMAC Interface 1307 */ 1308 #define QCA953X_GMAC_REG_ETH_CFG 0x00 1309 1310 #define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6) 1311 #define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7) 1312 #define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9) 1313 #define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) 1314 1315 /* 1316 * QCA955X GMAC Interface 1317 */ 1318 1319 #define QCA955X_GMAC_REG_ETH_CFG 0x00 1320 1321 #define QCA955X_ETH_CFG_RGMII_EN BIT(0) 1322 #define QCA955X_ETH_CFG_GE0_SGMII BIT(6) 1323 1324 /* 1325 * QCA956X GMAC Interface 1326 */ 1327 1328 #define QCA956X_GMAC_REG_ETH_CFG 0x00 1329 #define QCA956X_GMAC_REG_SGMII_RESET 0x14 1330 #define QCA956X_GMAC_REG_SGMII_SERDES 0x18 1331 #define QCA956X_GMAC_REG_MR_AN_CTRL 0x1c 1332 #define QCA956X_GMAC_REG_SGMII_CONFIG 0x34 1333 #define QCA956X_GMAC_REG_SGMII_DEBUG 0x58 1334 1335 #define QCA956X_ETH_CFG_GE0_SGMII BIT(6) 1336 1337 #endif /* __ASM_AR71XX_H */ 1338