1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
4 * Based on Atheros LSDK/QSDK
5 */
6
7 #include <common.h>
8 #include <asm/io.h>
9 #include <asm/addrspace.h>
10 #include <asm/types.h>
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <mach/ar71xx_regs.h>
14 #include <mach/ath79.h>
15
16 #define DDR_CTRL_UPD_EMR3S BIT(5)
17 #define DDR_CTRL_UPD_EMR2S BIT(4)
18 #define DDR_CTRL_PRECHARGE BIT(3)
19 #define DDR_CTRL_AUTO_REFRESH BIT(2)
20 #define DDR_CTRL_UPD_EMRS BIT(1)
21 #define DDR_CTRL_UPD_MRS BIT(0)
22
23 #define DDR_REFRESH_EN BIT(14)
24 #define DDR_REFRESH_M 0x3ff
25 #define DDR_REFRESH(x) ((x) & DDR_REFRESH_M)
26 #define DDR_REFRESH_VAL (DDR_REFRESH_EN | DDR_REFRESH(312))
27
28 #define DDR_TRAS_S 0
29 #define DDR_TRAS_M 0x1f
30 #define DDR_TRAS(x) (((x) & DDR_TRAS_M) << DDR_TRAS_S)
31 #define DDR_TRCD_M 0xf
32 #define DDR_TRCD_S 5
33 #define DDR_TRCD(x) (((x) & DDR_TRCD_M) << DDR_TRCD_S)
34 #define DDR_TRP_M 0xf
35 #define DDR_TRP_S 9
36 #define DDR_TRP(x) (((x) & DDR_TRP_M) << DDR_TRP_S)
37 #define DDR_TRRD_M 0xf
38 #define DDR_TRRD_S 13
39 #define DDR_TRRD(x) (((x) & DDR_TRRD_M) << DDR_TRRD_S)
40 #define DDR_TRFC_M 0x7f
41 #define DDR_TRFC_S 17
42 #define DDR_TRFC(x) (((x) & DDR_TRFC_M) << DDR_TRFC_S)
43 #define DDR_TMRD_M 0xf
44 #define DDR_TMRD_S 23
45 #define DDR_TMRD(x) (((x) & DDR_TMRD_M) << DDR_TMRD_S)
46 #define DDR_CAS_L_M 0x17
47 #define DDR_CAS_L_S 27
48 #define DDR_CAS_L(x) (((x) & DDR_CAS_L_M) << DDR_CAS_L_S)
49 #define DDR_OPEN BIT(30)
50 #define DDR1_CONF_REG_VAL (DDR_TRAS(16) | DDR_TRCD(6) | \
51 DDR_TRP(6) | DDR_TRRD(4) | \
52 DDR_TRFC(7) | DDR_TMRD(5) | \
53 DDR_CAS_L(7) | DDR_OPEN)
54 #define DDR2_CONF_REG_VAL (DDR_TRAS(27) | DDR_TRCD(9) | \
55 DDR_TRP(9) | DDR_TRRD(7) | \
56 DDR_TRFC(21) | DDR_TMRD(15) | \
57 DDR_CAS_L(17) | DDR_OPEN)
58
59 #define DDR_BURST_LEN_S 0
60 #define DDR_BURST_LEN_M 0xf
61 #define DDR_BURST_LEN(x) ((x) << DDR_BURST_LEN_S)
62 #define DDR_BURST_TYPE BIT(4)
63 #define DDR_CNTL_OE_EN BIT(5)
64 #define DDR_PHASE_SEL BIT(6)
65 #define DDR_CKE BIT(7)
66 #define DDR_TWR_S 8
67 #define DDR_TWR_M 0xf
68 #define DDR_TWR(x) (((x) & DDR_TWR_M) << DDR_TWR_S)
69 #define DDR_TRTW_S 12
70 #define DDR_TRTW_M 0x1f
71 #define DDR_TRTW(x) (((x) & DDR_TRTW_M) << DDR_TRTW_S)
72 #define DDR_TRTP_S 17
73 #define DDR_TRTP_M 0xf
74 #define DDR_TRTP(x) (((x) & DDR_TRTP_M) << DDR_TRTP_S)
75 #define DDR_TWTR_S 21
76 #define DDR_TWTR_M 0x1f
77 #define DDR_TWTR(x) (((x) & DDR_TWTR_M) << DDR_TWTR_S)
78 #define DDR_G_OPEN_L_S 26
79 #define DDR_G_OPEN_L_M 0xf
80 #define DDR_G_OPEN_L(x) ((x) << DDR_G_OPEN_L_S)
81 #define DDR_HALF_WIDTH_LOW BIT(31)
82 #define DDR1_CONF2_REG_VAL (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \
83 DDR_CKE | DDR_TWR(13) | DDR_TRTW(14) | \
84 DDR_TRTP(8) | DDR_TWTR(14) | \
85 DDR_G_OPEN_L(6) | DDR_HALF_WIDTH_LOW)
86 #define DDR2_CONF2_REG_VAL (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \
87 DDR_CKE | DDR_TWR(1) | DDR_TRTW(14) | \
88 DDR_TRTP(9) | DDR_TWTR(21) | \
89 DDR_G_OPEN_L(8) | DDR_HALF_WIDTH_LOW)
90
91 #define DDR_TWR_MSB BIT(3)
92 #define DDR_TRAS_MSB BIT(2)
93 #define DDR_TRFC_MSB_M 0x3
94 #define DDR_TRFC_MSB(x) (x)
95 #define DDR1_CONF3_REG_VAL 0
96 #define DDR2_CONF3_REG_VAL (DDR_TWR_MSB | DDR_TRFC_MSB(2))
97
98 #define DDR_CTL_SRAM_TSEL BIT(30)
99 #define DDR_CTL_SRAM_GE0_SYNC BIT(20)
100 #define DDR_CTL_SRAM_GE1_SYNC BIT(19)
101 #define DDR_CTL_SRAM_USB_SYNC BIT(18)
102 #define DDR_CTL_SRAM_PCIE_SYNC BIT(17)
103 #define DDR_CTL_SRAM_WMAC_SYNC BIT(16)
104 #define DDR_CTL_SRAM_MISC1_SYNC BIT(15)
105 #define DDR_CTL_SRAM_MISC2_SYNC BIT(14)
106 #define DDR_CTL_PAD_DDR2_SEL BIT(6)
107 #define DDR_CTL_HALF_WIDTH BIT(1)
108 #define DDR_CTL_CONFIG_VAL (DDR_CTL_SRAM_TSEL | \
109 DDR_CTL_SRAM_GE0_SYNC | \
110 DDR_CTL_SRAM_GE1_SYNC | \
111 DDR_CTL_SRAM_USB_SYNC | \
112 DDR_CTL_SRAM_PCIE_SYNC | \
113 DDR_CTL_SRAM_WMAC_SYNC | \
114 DDR_CTL_HALF_WIDTH)
115
116 #define DDR_BURST_GE0_MAX_BL_S 0
117 #define DDR_BURST_GE0_MAX_BL_M 0xf
118 #define DDR_BURST_GE0_MAX_BL(x) \
119 (((x) & DDR_BURST_GE0_MAX_BL_M) << DDR_BURST_GE0_MAX_BL_S)
120 #define DDR_BURST_GE1_MAX_BL_S 4
121 #define DDR_BURST_GE1_MAX_BL_M 0xf
122 #define DDR_BURST_GE1_MAX_BL(x) \
123 (((x) & DDR_BURST_GE1_MAX_BL_M) << DDR_BURST_GE1_MAX_BL_S)
124 #define DDR_BURST_PCIE_MAX_BL_S 8
125 #define DDR_BURST_PCIE_MAX_BL_M 0xf
126 #define DDR_BURST_PCIE_MAX_BL(x) \
127 (((x) & DDR_BURST_PCIE_MAX_BL_M) << DDR_BURST_PCIE_MAX_BL_S)
128 #define DDR_BURST_USB_MAX_BL_S 12
129 #define DDR_BURST_USB_MAX_BL_M 0xf
130 #define DDR_BURST_USB_MAX_BL(x) \
131 (((x) & DDR_BURST_USB_MAX_BL_M) << DDR_BURST_USB_MAX_BL_S)
132 #define DDR_BURST_CPU_MAX_BL_S 16
133 #define DDR_BURST_CPU_MAX_BL_M 0xf
134 #define DDR_BURST_CPU_MAX_BL(x) \
135 (((x) & DDR_BURST_CPU_MAX_BL_M) << DDR_BURST_CPU_MAX_BL_S)
136 #define DDR_BURST_RD_MAX_BL_S 20
137 #define DDR_BURST_RD_MAX_BL_M 0xf
138 #define DDR_BURST_RD_MAX_BL(x) \
139 (((x) & DDR_BURST_RD_MAX_BL_M) << DDR_BURST_RD_MAX_BL_S)
140 #define DDR_BURST_WR_MAX_BL_S 24
141 #define DDR_BURST_WR_MAX_BL_M 0xf
142 #define DDR_BURST_WR_MAX_BL(x) \
143 (((x) & DDR_BURST_WR_MAX_BL_M) << DDR_BURST_WR_MAX_BL_S)
144 #define DDR_BURST_RWP_MASK_EN_S 28
145 #define DDR_BURST_RWP_MASK_EN_M 0x3
146 #define DDR_BURST_RWP_MASK_EN(x) \
147 (((x) & DDR_BURST_RWP_MASK_EN_M) << DDR_BURST_RWP_MASK_EN_S)
148 #define DDR_BURST_CPU_PRI_BE BIT(30)
149 #define DDR_BURST_CPU_PRI BIT(31)
150 #define DDR_BURST_VAL (DDR_BURST_CPU_PRI_BE | \
151 DDR_BURST_RWP_MASK_EN(3) | \
152 DDR_BURST_WR_MAX_BL(4) | \
153 DDR_BURST_RD_MAX_BL(4) | \
154 DDR_BURST_CPU_MAX_BL(4) | \
155 DDR_BURST_USB_MAX_BL(4) | \
156 DDR_BURST_PCIE_MAX_BL(4) | \
157 DDR_BURST_GE1_MAX_BL(4) | \
158 DDR_BURST_GE0_MAX_BL(4))
159
160 #define DDR_BURST_WMAC_MAX_BL_S 0
161 #define DDR_BURST_WMAC_MAX_BL_M 0xf
162 #define DDR_BURST_WMAC_MAX_BL(x) \
163 (((x) & DDR_BURST_WMAC_MAX_BL_M) << DDR_BURST_WMAC_MAX_BL_S)
164 #define DDR_BURST2_VAL DDR_BURST_WMAC_MAX_BL(4)
165
166 #define DDR2_CONF_TWL_S 10
167 #define DDR2_CONF_TWL_M 0xf
168 #define DDR2_CONF_TWL(x) \
169 (((x) & DDR2_CONF_TWL_M) << DDR2_CONF_TWL_S)
170 #define DDR2_CONF_ODT BIT(9)
171 #define DDR2_CONF_TFAW_S 2
172 #define DDR2_CONF_TFAW_M 0x3f
173 #define DDR2_CONF_TFAW(x) \
174 (((x) & DDR2_CONF_TFAW_M) << DDR2_CONF_TFAW_S)
175 #define DDR2_CONF_EN BIT(0)
176 #define DDR2_CONF_VAL (DDR2_CONF_TWL(5) | \
177 DDR2_CONF_TFAW(31) | \
178 DDR2_CONF_ODT | \
179 DDR2_CONF_EN)
180
181 #define DDR1_EXT_MODE_VAL 0
182 #define DDR2_EXT_MODE_VAL 0x402
183 #define DDR2_EXT_MODE_OCD_VAL 0x782
184 #define DDR1_MODE_DLL_VAL 0x133
185 #define DDR2_MODE_DLL_VAL 0x143
186 #define DDR1_MODE_VAL 0x33
187 #define DDR2_MODE_VAL 0x43
188 #define DDR1_TAP_VAL 0x20
189 #define DDR2_TAP_VAL 0x10
190
191 #define DDR_REG_BIST_MASK_ADDR_0 0x2c
192 #define DDR_REG_BIST_MASK_ADDR_1 0x30
193 #define DDR_REG_BIST_MASK_AHB_GE0_0 0x34
194 #define DDR_REG_BIST_COMP_AHB_GE0_0 0x38
195 #define DDR_REG_BIST_MASK_AHB_GE1_0 0x3c
196 #define DDR_REG_BIST_COMP_AHB_GE1_0 0x40
197 #define DDR_REG_BIST_COMP_ADDR_0 0x64
198 #define DDR_REG_BIST_COMP_ADDR_1 0x68
199 #define DDR_REG_BIST_MASK_AHB_GE0_1 0x6c
200 #define DDR_REG_BIST_COMP_AHB_GE0_1 0x70
201 #define DDR_REG_BIST_MASK_AHB_GE1_1 0x74
202 #define DDR_REG_BIST_COMP_AHB_GE1_1 0x78
203 #define DDR_REG_BIST 0x11c
204 #define DDR_REG_BIST_STATUS 0x120
205
206 #define DDR_BIST_COMP_CNT_S 1
207 #define DDR_BIST_COMP_CNT_M 0xff
208 #define DDR_BIST_COMP_CNT(x) \
209 (((x) & DDR_BIST_COMP_CNT_M) << DDR_BIST_COMP_CNT_S)
210 #define DDR_BIST_COMP_CNT_MASK \
211 (DDR_BIST_COMP_CNT_M << DDR_BIST_COMP_CNT_S)
212 #define DDR_BIST_TEST_START BIT(0)
213 #define DDR_BIST_STATUS_DONE BIT(0)
214
215 /* 4 Row Address Bits, 4 Column Address Bits, 2 BA bits */
216 #define DDR_BIST_MASK_ADDR_VAL 0xfa5de83f
217
218 #define DDR_TAP_MAGIC_VAL 0xaa55aa55
219 #define DDR_TAP_MAX_VAL 0x40
220
ddr_init(void)221 void ddr_init(void)
222 {
223 void __iomem *regs;
224 u32 val;
225
226 regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
227 MAP_NOCACHE);
228 val = ath79_get_bootstrap();
229 if (val & QCA953X_BOOTSTRAP_DDR1) {
230 writel(DDR_CTL_CONFIG_VAL, regs + QCA953X_DDR_REG_CTL_CONF);
231 udelay(10);
232
233 /* For 16-bit DDR */
234 writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE);
235 udelay(100);
236
237 /* Burst size */
238 writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST);
239 udelay(100);
240 writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2);
241 udelay(100);
242
243 /* AHB maximum timeout */
244 writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX);
245 udelay(100);
246
247 /* DRAM timing */
248 writel(DDR1_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
249 udelay(100);
250 writel(DDR1_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
251 udelay(100);
252 writel(DDR1_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3);
253 udelay(100);
254
255 /* Precharge All */
256 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
257 udelay(100);
258
259 /* ODT disable, Full strength, Enable DLL */
260 writel(DDR1_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
261 udelay(100);
262
263 /* Update Extended Mode Register Set (EMRS) */
264 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
265 udelay(100);
266
267 /* Reset DLL, CAS Latency 3, Burst Length 8 */
268 writel(DDR1_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
269 udelay(100);
270
271 /* Update Mode Register Set (MRS) */
272 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
273 udelay(100);
274
275 /* Precharge All */
276 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
277 udelay(100);
278
279 /* Auto Refresh */
280 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
281 udelay(100);
282 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
283 udelay(100);
284
285 /* Normal DLL, CAS Latency 3, Burst Length 8 */
286 writel(DDR1_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
287 udelay(100);
288
289 /* Update Mode Register Set (MRS) */
290 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
291 udelay(100);
292
293 /* Refresh time control */
294 writel(DDR_REFRESH_VAL, regs + AR71XX_DDR_REG_REFRESH);
295 udelay(100);
296
297 /* DQS 0 Tap Control */
298 writel(DDR1_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL0);
299
300 /* DQS 1 Tap Control */
301 writel(DDR1_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1);
302 } else {
303 writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
304 udelay(10);
305 writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
306 udelay(10);
307 writel(DDR_CTL_CONFIG_VAL | DDR_CTL_PAD_DDR2_SEL,
308 regs + QCA953X_DDR_REG_CTL_CONF);
309 udelay(10);
310
311 /* For 16-bit DDR */
312 writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE);
313 udelay(100);
314
315 /* Burst size */
316 writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST);
317 udelay(100);
318 writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2);
319 udelay(100);
320
321 /* AHB maximum timeout */
322 writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX);
323 udelay(100);
324
325 /* DRAM timing */
326 writel(DDR2_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
327 udelay(100);
328 writel(DDR2_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
329 udelay(100);
330 writel(DDR2_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3);
331 udelay(100);
332
333 /* Enable DDR2 */
334 writel(DDR2_CONF_VAL, regs + QCA953X_DDR_REG_DDR2_CONFIG);
335 udelay(100);
336
337 /* Precharge All */
338 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
339 udelay(100);
340
341 /* Update Extended Mode Register 2 Set (EMR2S) */
342 writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
343 udelay(100);
344
345 /* Update Extended Mode Register 3 Set (EMR3S) */
346 writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
347 udelay(100);
348
349 /* 150 ohm, Reduced strength, Enable DLL */
350 writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
351 udelay(100);
352
353 /* Update Extended Mode Register Set (EMRS) */
354 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
355 udelay(100);
356
357 /* Reset DLL, CAS Latency 4, Burst Length 8 */
358 writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
359 udelay(100);
360
361 /* Update Mode Register Set (MRS) */
362 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
363 udelay(100);
364
365 /* Precharge All */
366 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
367 udelay(100);
368
369 /* Auto Refresh */
370 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
371 udelay(100);
372 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
373 udelay(100);
374
375 /* Normal DLL, CAS Latency 4, Burst Length 8 */
376 writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
377 udelay(100);
378
379 /* Mode Register Set (MRS) */
380 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
381 udelay(100);
382
383 /* Enable OCD, Enable DLL, Reduced Drive Strength */
384 writel(DDR2_EXT_MODE_OCD_VAL, regs + AR71XX_DDR_REG_EMR);
385 udelay(100);
386
387 /* Update Extended Mode Register Set (EMRS) */
388 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
389 udelay(100);
390
391 /* OCD diable, Enable DLL, Reduced Drive Strength */
392 writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
393 udelay(100);
394
395 /* Update Extended Mode Register Set (EMRS) */
396 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
397 udelay(100);
398
399 /* Refresh time control */
400 writel(DDR_REFRESH_VAL, regs + AR71XX_DDR_REG_REFRESH);
401 udelay(100);
402
403 /* DQS 0 Tap Control */
404 writel(DDR2_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL0);
405
406 /* DQS 1 Tap Control */
407 writel(DDR2_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1);
408 }
409 }
410
ddr_tap_tuning(void)411 void ddr_tap_tuning(void)
412 {
413 void __iomem *regs;
414 u32 val, pass, tap, cnt, tap_val, last, first;
415
416 regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
417 MAP_NOCACHE);
418
419 tap_val = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
420 first = DDR_TAP_MAGIC_VAL;
421 last = 0;
422 cnt = 0;
423 tap = 0;
424
425 do {
426 writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL0);
427 writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL1);
428
429 writel(DDR_BIST_COMP_CNT(8), regs + DDR_REG_BIST_COMP_ADDR_1);
430 writel(DDR_BIST_MASK_ADDR_VAL, regs + DDR_REG_BIST_MASK_ADDR_0);
431 writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE0_1);
432 writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE1_0);
433 writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE1_1);
434 writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE0_0);
435 writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE0_1);
436 writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE1_0);
437 writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE1_1);
438 writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE0_0);
439
440 /* Start BIST test */
441 writel(DDR_BIST_TEST_START, regs + DDR_REG_BIST);
442
443 do {
444 val = readl(regs + DDR_REG_BIST_STATUS);
445 } while (!(val & DDR_BIST_STATUS_DONE));
446
447 /* Stop BIST test */
448 writel(0, regs + DDR_REG_BIST);
449
450 pass = val & DDR_BIST_COMP_CNT_MASK;
451 pass ^= DDR_BIST_COMP_CNT(8);
452 if (!pass) {
453 if (first != DDR_TAP_MAGIC_VAL) {
454 last = tap;
455 } else {
456 first = tap;
457 last = tap;
458 }
459 cnt++;
460 }
461 tap++;
462 } while (tap < DDR_TAP_MAX_VAL);
463
464 if (cnt) {
465 tap_val = (first + last) / 2;
466 tap_val %= DDR_TAP_MAX_VAL;
467 }
468
469 writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL0);
470 writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL1);
471 }
472