1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
4 */
5
6 /* Tegra vpr routines */
7
8 #include <common.h>
9 #include <log.h>
10 #include <asm/io.h>
11 #include <asm/arch/tegra.h>
12 #include <asm/arch/mc.h>
13 #include <asm/arch-tegra/ap.h>
14
15 #include <fdt_support.h>
16
17 static bool _configured;
18
tegra_gpu_config(void)19 void tegra_gpu_config(void)
20 {
21 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
22
23 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
24 if (!tegra_cpu_is_non_secure())
25 #endif
26 {
27 /* Turn VPR off */
28 writel(0, &mc->mc_video_protect_size_mb);
29 writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED,
30 &mc->mc_video_protect_reg_ctrl);
31 /* read back to ensure the write went through */
32 readl(&mc->mc_video_protect_reg_ctrl);
33 }
34
35 debug("configured VPR\n");
36
37 _configured = true;
38 }
39
40 #if defined(CONFIG_OF_LIBFDT)
41
tegra_gpu_enable_node(void * blob,const char * compat)42 int tegra_gpu_enable_node(void *blob, const char *compat)
43 {
44 int offset;
45
46 if (!_configured)
47 return 0;
48
49 offset = fdt_node_offset_by_compatible(blob, -1, compat);
50 while (offset != -FDT_ERR_NOTFOUND) {
51 fdt_status_okay(blob, offset);
52 offset = fdt_node_offset_by_compatible(blob, offset, compat);
53 }
54
55 return 0;
56 }
57
58 #endif
59