1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2013
4 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 *
6 * Based on:
7 * Copyright (c) 2011 IDS GmbH, Germany
8 * ids8313.c - ids8313 board support.
9 *
10 * Sergej Stepanov <ste@ids.de>
11 * Based on board/freescale/mpc8313erdb/mpc8313erdb.c
12 */
13
14 #include <common.h>
15 #include <fdt_support.h>
16 #include <init.h>
17 #include <mpc83xx.h>
18 #include <spi.h>
19 #include <asm/bitops.h>
20 #include <asm/global_data.h>
21 #include <linux/delay.h>
22 #include <linux/libfdt.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25 /** CPLD contains the info about:
26 * - board type: *pCpld & 0xF0
27 * - hw-revision: *pCpld & 0x0F
28 * - cpld-revision: *pCpld+1
29 */
checkboard(void)30 int checkboard(void)
31 {
32 char *pcpld = (char *)CONFIG_SYS_CPLD_BASE;
33 u8 u8Vers = readb(pcpld);
34 u8 u8Revs = readb(pcpld + 1);
35
36 printf("Board: ");
37 switch (u8Vers & 0xF0) {
38 case '\x40':
39 printf("CU73X");
40 break;
41 case '\x50':
42 printf("CC73X");
43 break;
44 default:
45 printf("unknown(0x%02X, 0x%02X)\n", u8Vers, u8Revs);
46 return 0;
47 }
48 printf("\nInfo: HW-Rev: %i, CPLD-Rev: %i\n",
49 u8Vers & 0x0F, u8Revs & 0xFF);
50 return 0;
51 }
52
53 /*
54 * fixed sdram init
55 */
fixed_sdram(unsigned long config)56 int fixed_sdram(unsigned long config)
57 {
58 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
59 u32 msize = CONFIG_SYS_DDR_SIZE << 20;
60
61 #ifndef CONFIG_SYS_RAMBOOT
62 u32 msize_log2 = __ilog2(msize);
63
64 out_be32(&im->sysconf.ddrlaw[0].bar,
65 (CONFIG_SYS_SDRAM_BASE & 0xfffff000));
66 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
67 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
68 sync();
69
70 /*
71 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
72 * or the DDR2 controller may fail to initialize correctly.
73 */
74 udelay(50000);
75
76 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
77 out_be32(&im->ddr.cs_config[0], config);
78
79 /* currently we use only one CS, so disable the other banks */
80 out_be32(&im->ddr.cs_config[1], 0);
81 out_be32(&im->ddr.cs_config[2], 0);
82 out_be32(&im->ddr.cs_config[3], 0);
83
84 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
85 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
86 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
87 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
88
89 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
90 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
91
92 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
93 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
94
95 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
96 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
97 sync();
98 udelay(300);
99
100 /* enable DDR controller */
101 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
102 /* now check the real size */
103 disable_addr_trans();
104 msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
105 enable_addr_trans();
106 #endif
107 return msize;
108 }
109
setup_sdram(void)110 static int setup_sdram(void)
111 {
112 u32 msize = CONFIG_SYS_DDR_SIZE << 20;
113 long int size_01, size_02;
114
115 size_01 = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
116 size_02 = fixed_sdram(CONFIG_SYS_DDR_CONFIG_256);
117
118 if (size_01 > size_02)
119 msize = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
120 else
121 msize = size_02;
122
123 return msize;
124 }
125
dram_init(void)126 int dram_init(void)
127 {
128 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
129 fsl_lbc_t *lbc = &im->im_lbc;
130 u32 msize = 0;
131
132 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
133 return -ENXIO;
134
135 msize = setup_sdram();
136
137 out_be32(&lbc->lbcr, (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF));
138 out_be32(&lbc->mrtpr, 0x20000000);
139 sync();
140
141 gd->ram_size = msize;
142
143 return 0;
144 }
145
146 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,struct bd_info * bd)147 int ft_board_setup(void *blob, struct bd_info *bd)
148 {
149 ft_cpu_setup(blob, bd);
150
151 return 0;
152 }
153 #endif
154
155 /* gpio mask for spi_cs */
156 #define IDSCPLD_SPI_CS_MASK 0x00000001
157 /* spi_cs multiplexed through cpld */
158 #define IDSCPLD_SPI_CS_BASE (CONFIG_SYS_CPLD_BASE + 0xf)
159
160 #if defined(CONFIG_MISC_INIT_R)
161 /* srp umcr mask for rts */
162 #define IDSUMCR_RTS_MASK 0x04
misc_init_r(void)163 int misc_init_r(void)
164 {
165 /*srp*/
166 duart83xx_t *uart1 = &((immap_t *)CONFIG_SYS_IMMR)->duart[0];
167 duart83xx_t *uart2 = &((immap_t *)CONFIG_SYS_IMMR)->duart[1];
168
169 gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
170 u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
171
172 /* deactivate spi_cs channels */
173 out_8(spi_base, 0);
174 /* deactivate the spi_cs */
175 setbits_be32(&iopd->dir, IDSCPLD_SPI_CS_MASK);
176 /*srp - deactivate rts*/
177 out_8(&uart1->umcr, IDSUMCR_RTS_MASK);
178 out_8(&uart2->umcr, IDSUMCR_RTS_MASK);
179
180
181 gd->fdt_blob = (void *)CONFIG_SYS_FLASH_BASE;
182 return 0;
183 }
184 #endif
185
186 #ifdef CONFIG_MPC8XXX_SPI
187 /*
188 * The following are used to control the SPI chip selects
189 */
spi_cs_is_valid(unsigned int bus,unsigned int cs)190 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
191 {
192 return bus == 0 && ((cs >= 0) && (cs <= 2));
193 }
194
spi_cs_activate(struct spi_slave * slave)195 void spi_cs_activate(struct spi_slave *slave)
196 {
197 gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
198 u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
199
200 /* select the spi_cs channel */
201 out_8(spi_base, 1 << slave->cs);
202 /* activate the spi_cs */
203 clrbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
204 }
205
spi_cs_deactivate(struct spi_slave * slave)206 void spi_cs_deactivate(struct spi_slave *slave)
207 {
208 gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
209 u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
210
211 /* select the spi_cs channel */
212 out_8(spi_base, 1 << slave->cs);
213 /* deactivate the spi_cs */
214 setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
215 }
216 #endif
217