1 /* SPDX-License-Identifier: GPL-2.0+ 2 * 3 * Copyright (C) 2016 Nexell Co., Ltd. 4 * 5 * Author: junghyun, kim <jhkim@nexell.co.kr> 6 */ 7 8 #ifndef _S5PXX18_SOC_DISPTOP_H_ 9 #define _S5PXX18_SOC_DISPTOP_H_ 10 11 #include "s5pxx18_soc_disptype.h" 12 13 #define NUMBER_OF_DISPTOP_MODULE 1 14 #define PHY_BASEADDR_DISPLAYTOP_MODULE 0xC0100000 15 #define PHY_BASEADDR_DISPTOP_LIST \ 16 { PHY_BASEADDR_DISPLAYTOP_MODULE } 17 18 #define HDMI_ADDR_OFFSET \ 19 (((PHY_BASEADDR_DISPLAYTOP_MODULE / 0x00100000) % 2) ? 0x100000 \ 20 : 0x000000) 21 #define OTHER_ADDR_OFFSET \ 22 (((PHY_BASEADDR_DISPLAYTOP_MODULE / 0x00100000) % 2) ? 0x000000 \ 23 : 0x100000) 24 #define PHY_BASEADDR_DISPLAYTOP_MODULE_OFFSET (OTHER_ADDR_OFFSET + 0x001000) 25 #define PHY_BASEADDR_DUALDISPLAY_MODULE \ 26 (PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x002000) 27 #define PHY_BASEADDR_RESCONV_MODULE \ 28 (PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x003000) 29 #define PHY_BASEADDR_LCDINTERFACE_MODULE \ 30 (PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x004000) 31 #define PHY_BASEADDR_HDMI_MODULE (PHY_BASEADDR_DISPLAYTOP_MODULE + 0x000000) 32 #define PHY_BASEADDR_LVDS_MODULE \ 33 (PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x00a000) 34 35 #define NUMBER_OF_DUALDISPLAY_MODULE 1 36 #define INTNUM_OF_DUALDISPLAY_MODULE_PRIMIRQ \ 37 INTNUM_OF_DISPLAYTOP_MODULE_DUALDISPLAY_PRIMIRQ 38 #define INTNUM_OF_DUALDISPLAY_MODULE_SECONDIRQ \ 39 INTNUM_OF_DISPLAYTOP_MODULE_DUALDISPLAY_SECONDIRQ 40 #define RESETINDEX_OF_DUALDISPLAY_MODULE_I_NRST \ 41 RESETINDEX_OF_DISPLAYTOP_MODULE_I_DUALDISPLAY_NRST 42 #define PADINDEX_OF_DUALDISPLAY_O_NCS \ 43 PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PADPRIMVCLK 44 #define PADINDEX_OF_DUALDISPLAY_O_NRD \ 45 PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_HSYNC 46 #define PADINDEX_OF_DUALDISPLAY_O_RS \ 47 PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_VSYNC 48 #define PADINDEX_OF_DUALDISPLAY_O_NWR \ 49 PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADDE 50 #define PADINDEX_OF_DUALDISPLAY_PADPRIMVCLK \ 51 PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PADPRIMVCLK 52 #define PADINDEX_OF_DUALDISPLAY_O_PRIM_PADN_HSYNC \ 53 PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_HSYNC 54 #define PADINDEX_OF_DUALDISPLAY_O_PRIM_PADN_VSYNC \ 55 PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_VSYNC 56 #define PADINDEX_OF_DUALDISPLAY_O_PRIM_PADDE \ 57 PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADDE 58 #define PADINDEX_OF_DUALDISPLAY_PRIM_0_ \ 59 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_0_ 60 #define PADINDEX_OF_DUALDISPLAY_PRIM_1_ \ 61 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_1_ 62 #define PADINDEX_OF_DUALDISPLAY_PRIM_2_ \ 63 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_2_ 64 #define PADINDEX_OF_DUALDISPLAY_PRIM_3_ \ 65 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_3_ 66 #define PADINDEX_OF_DUALDISPLAY_PRIM_4_ \ 67 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_4_ 68 #define PADINDEX_OF_DUALDISPLAY_PRIM_5_ \ 69 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_5_ 70 #define PADINDEX_OF_DUALDISPLAY_PRIM_6_ \ 71 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_6_ 72 #define PADINDEX_OF_DUALDISPLAY_PRIM_7_ \ 73 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_7_ 74 #define PADINDEX_OF_DUALDISPLAY_PRIM_8_ \ 75 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_8_ 76 #define PADINDEX_OF_DUALDISPLAY_PRIM_9_ \ 77 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_9_ 78 #define PADINDEX_OF_DUALDISPLAY_PRIM_10_ \ 79 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_10_ 80 #define PADINDEX_OF_DUALDISPLAY_PRIM_11_ \ 81 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_11_ 82 #define PADINDEX_OF_DUALDISPLAY_PRIM_12_ \ 83 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_12_ 84 #define PADINDEX_OF_DUALDISPLAY_PRIM_13_ \ 85 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_13_ 86 #define PADINDEX_OF_DUALDISPLAY_PRIM_14_ \ 87 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_14_ 88 #define PADINDEX_OF_DUALDISPLAY_PRIM_15_ \ 89 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_15_ 90 #define PADINDEX_OF_DUALDISPLAY_PRIM_16_ \ 91 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_16_ 92 #define PADINDEX_OF_DUALDISPLAY_PRIM_17_ \ 93 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_17_ 94 #define PADINDEX_OF_DUALDISPLAY_PRIM_18_ \ 95 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_18_ 96 #define PADINDEX_OF_DUALDISPLAY_PRIM_19_ \ 97 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_19_ 98 #define PADINDEX_OF_DUALDISPLAY_PRIM_20_ \ 99 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_20_ 100 #define PADINDEX_OF_DUALDISPLAY_PRIM_21_ \ 101 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_21_ 102 #define PADINDEX_OF_DUALDISPLAY_PRIM_22_ \ 103 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_22_ 104 #define PADINDEX_OF_DUALDISPLAY_PRIM_23_ \ 105 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_23_ 106 #define PADINDEX_OF_DUALDISPLAY_PADSECONDVCLK \ 107 PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PADPRIMVCLK 108 #define PADINDEX_OF_DUALDISPLAY_O_SECOND_PADN_HSYNC \ 109 PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_HSYNC 110 #define PADINDEX_OF_DUALDISPLAY_O_SECOND_PADN_VSYNC \ 111 PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_VSYNC 112 #define PADINDEX_OF_DUALDISPLAY_O_SECOND_PADDE \ 113 PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADDE 114 #define PADINDEX_OF_DUALDISPLAY_SECOND_0_ \ 115 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_0_ 116 #define PADINDEX_OF_DUALDISPLAY_SECOND_1_ \ 117 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_1_ 118 #define PADINDEX_OF_DUALDISPLAY_SECOND_2_ \ 119 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_2_ 120 #define PADINDEX_OF_DUALDISPLAY_SECOND_3_ \ 121 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_3_ 122 #define PADINDEX_OF_DUALDISPLAY_SECOND_4_ \ 123 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_4_ 124 #define PADINDEX_OF_DUALDISPLAY_SECOND_5_ \ 125 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_5_ 126 #define PADINDEX_OF_DUALDISPLAY_SECOND_6_ \ 127 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_6_ 128 #define PADINDEX_OF_DUALDISPLAY_SECOND_7_ \ 129 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_7_ 130 #define PADINDEX_OF_DUALDISPLAY_SECOND_8_ \ 131 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_8_ 132 #define PADINDEX_OF_DUALDISPLAY_SECOND_9_ \ 133 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_9_ 134 #define PADINDEX_OF_DUALDISPLAY_SECOND_10_ \ 135 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_10_ 136 #define PADINDEX_OF_DUALDISPLAY_SECOND_11_ \ 137 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_11_ 138 #define PADINDEX_OF_DUALDISPLAY_SECOND_12_ \ 139 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_12_ 140 #define PADINDEX_OF_DUALDISPLAY_SECOND_13_ \ 141 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_13_ 142 #define PADINDEX_OF_DUALDISPLAY_SECOND_14_ \ 143 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_14_ 144 #define PADINDEX_OF_DUALDISPLAY_SECOND_15_ \ 145 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_15_ 146 #define PADINDEX_OF_DUALDISPLAY_SECOND_16_ \ 147 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_16_ 148 #define PADINDEX_OF_DUALDISPLAY_SECOND_17_ \ 149 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_17_ 150 #define PADINDEX_OF_DUALDISPLAY_SECOND_18_ \ 151 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_18_ 152 #define PADINDEX_OF_DUALDISPLAY_SECOND_19_ \ 153 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_19_ 154 #define PADINDEX_OF_DUALDISPLAY_SECOND_20_ \ 155 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_20_ 156 #define PADINDEX_OF_DUALDISPLAY_SECOND_21_ \ 157 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_21_ 158 #define PADINDEX_OF_DUALDISPLAY_SECOND_22_ \ 159 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_22_ 160 #define PADINDEX_OF_DUALDISPLAY_SECOND_23_ \ 161 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_23_ 162 163 #define NUMBER_OF_RESCONV_MODULE 1 164 #define INTNUM_OF_RESCONV_MODULE INTNUM_OF_DISPLAYTOP_MODULE_RESCONV_IRQ 165 #define RESETINDEX_OF_RESCONV_MODULE_I_NRST \ 166 RESETINDEX_OF_DISPLAYTOP_MODULE_I_RESCONV_NRST 167 #define RESETINDEX_OF_RESCONV_MODULE RESETINDEX_OF_RESCONV_MODULE_I_NRST 168 #define NUMBER_OF_LCDINTERFACE_MODULE 1 169 #define RESETINDEX_OF_LCDINTERFACE_MODULE_I_NRST \ 170 RESETINDEX_OF_DISPLAYTOP_MODULE_I_LCDIF_NRST 171 #define PADINDEX_OF_LCDINTERFACE_O_VCLK \ 172 PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PADPRIMVCLK 173 #define PADINDEX_OF_LCDINTERFACE_O_NHSYNC \ 174 PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_HSYNC 175 #define PADINDEX_OF_LCDINTERFACE_O_NVSYNC \ 176 PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADN_VSYNC 177 #define PADINDEX_OF_LCDINTERFACE_O_DE \ 178 PADINDEX_OF_DISPLAYTOP_O_DUAL_DISPLAY_PRIM_PADDE 179 #define PADINDEX_OF_LCDINTERFACE_RGB24_0_ \ 180 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_0_ 181 #define PADINDEX_OF_LCDINTERFACE_RGB24_1_ \ 182 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_1_ 183 #define PADINDEX_OF_LCDINTERFACE_RGB24_2_ \ 184 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_2_ 185 #define PADINDEX_OF_LCDINTERFACE_RGB24_3_ \ 186 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_3_ 187 #define PADINDEX_OF_LCDINTERFACE_RGB24_4_ \ 188 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_4_ 189 #define PADINDEX_OF_LCDINTERFACE_RGB24_5_ \ 190 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_5_ 191 #define PADINDEX_OF_LCDINTERFACE_RGB24_6_ \ 192 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_6_ 193 #define PADINDEX_OF_LCDINTERFACE_RGB24_7_ \ 194 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_7_ 195 #define PADINDEX_OF_LCDINTERFACE_RGB24_8_ \ 196 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_8_ 197 #define PADINDEX_OF_LCDINTERFACE_RGB24_9_ \ 198 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_9_ 199 #define PADINDEX_OF_LCDINTERFACE_RGB24_10_ \ 200 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_10_ 201 #define PADINDEX_OF_LCDINTERFACE_RGB24_11_ \ 202 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_11_ 203 #define PADINDEX_OF_LCDINTERFACE_RGB24_12_ \ 204 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_12_ 205 #define PADINDEX_OF_LCDINTERFACE_RGB24_13_ \ 206 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_13_ 207 #define PADINDEX_OF_LCDINTERFACE_RGB24_14_ \ 208 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_14_ 209 #define PADINDEX_OF_LCDINTERFACE_RGB24_15_ \ 210 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_15_ 211 #define PADINDEX_OF_LCDINTERFACE_RGB24_16_ \ 212 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_16_ 213 #define PADINDEX_OF_LCDINTERFACE_RGB24_17_ \ 214 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_17_ 215 #define PADINDEX_OF_LCDINTERFACE_RGB24_18_ \ 216 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_18_ 217 #define PADINDEX_OF_LCDINTERFACE_RGB24_19_ \ 218 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_19_ 219 #define PADINDEX_OF_LCDINTERFACE_RGB24_20_ \ 220 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_20_ 221 #define PADINDEX_OF_LCDINTERFACE_RGB24_21_ \ 222 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_21_ 223 #define PADINDEX_OF_LCDINTERFACE_RGB24_22_ \ 224 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_22_ 225 #define PADINDEX_OF_LCDINTERFACE_RGB24_23_ \ 226 PADINDEX_OF_DISPLAYTOP_DUAL_DISPLAY_PRIM_23_ 227 228 #define NUMBER_OF_HDMI_MODULE 1 229 #define INTNUM_OF_HDMI_MODULE INTNUM_OF_DISPLAYTOP_MODULE_HDMI_IRQ 230 #define RESETINDEX_OF_HDMI_MODULE_I_NRST \ 231 RESETINDEX_OF_DISPLAYTOP_MODULE_I_HDMI_NRST 232 #define RESETINDEX_OF_HDMI_MODULE_I_NRST_VIDEO \ 233 RESETINDEX_OF_DISPLAYTOP_MODULE_I_HDMI_VIDEO_NRST 234 #define RESETINDEX_OF_HDMI_MODULE_I_NRST_SPDIF \ 235 RESETINDEX_OF_DISPLAYTOP_MODULE_I_HDMI_SPDIF_NRST 236 #define RESETINDEX_OF_HDMI_MODULE_I_NRST_TMDS \ 237 RESETINDEX_OF_DISPLAYTOP_MODULE_I_HDMI_TMDS_NRST 238 #define RESETINDEX_OF_HDMI_MODULE_I_NRST_PHY \ 239 RESETINDEX_OF_DISPLAYTOP_MODULE_I_HDMI_PHY_NRST 240 #define PADINDEX_OF_HDMI_I_PHY_CLKI PADINDEX_OF_DISPLAYTOP_I_HDMI_CLKI 241 #define PADINDEX_OF_HDMI_O_PHY_CLKO PADINDEX_OF_DISPLAYTOP_O_HDMI_CLKO 242 #define PADINDEX_OF_HDMI_IO_PHY_REXT PADINDEX_OF_DISPLAYTOP_IO_HDMI_REXT 243 #define PADINDEX_OF_HDMI_O_PHY_TX0P PADINDEX_OF_DISPLAYTOP_O_HDMI_TX0P 244 #define PADINDEX_OF_HDMI_O_PHY_TX0N PADINDEX_OF_DISPLAYTOP_O_HDMI_TX0N 245 #define PADINDEX_OF_HDMI_O_PHY_TX1P PADINDEX_OF_DISPLAYTOP_O_HDMI_TX1P 246 #define PADINDEX_OF_HDMI_O_PHY_TX1N PADINDEX_OF_DISPLAYTOP_O_HDMI_TX1N 247 #define PADINDEX_OF_HDMI_O_PHY_TX2P PADINDEX_OF_DISPLAYTOP_O_HDMI_TX2P 248 #define PADINDEX_OF_HDMI_O_PHY_TX2N PADINDEX_OF_DISPLAYTOP_O_HDMI_TX2N 249 #define PADINDEX_OF_HDMI_O_PHY_TXCP PADINDEX_OF_DISPLAYTOP_O_HDMI_TXCP 250 #define PADINDEX_OF_HDMI_O_PHY_TXCN PADINDEX_OF_DISPLAYTOP_O_HDMI_TXCN 251 #define PADINDEX_OF_HDMI_I_HOTPLUG PADINDEX_OF_DISPLAYTOP_I_HDMI_HOTPLUG_5V 252 #define PADINDEX_OF_HDMI_IO_PAD_CEC PADINDEX_OF_DISPLAYTOP_IO_HDMI_CEC 253 #define NUMBER_OF_LVDS_MODULE 1 254 255 #define RESETINDEX_OF_LVDS_MODULE_I_RESETN \ 256 RESETINDEX_OF_DISPLAYTOP_MODULE_I_LVDS_NRST 257 #define RESETINDEX_OF_LVDS_MODULE RESETINDEX_OF_LVDS_MODULE_I_RESETN 258 259 #define PADINDEX_OF_LVDS_TAP PADINDEX_OF_DISPLAYTOP_LVDS_TXP_A 260 #define PADINDEX_OF_LVDS_TAN PADINDEX_OF_DISPLAYTOP_LVDS_TXN_A 261 #define PADINDEX_OF_LVDS_TBP PADINDEX_OF_DISPLAYTOP_LVDS_TXP_B 262 #define PADINDEX_OF_LVDS_TBN PADINDEX_OF_DISPLAYTOP_LVDS_TXN_B 263 #define PADINDEX_OF_LVDS_TCP PADINDEX_OF_DISPLAYTOP_LVDS_TXP_C 264 #define PADINDEX_OF_LVDS_TCN PADINDEX_OF_DISPLAYTOP_LVDS_TXN_C 265 #define PADINDEX_OF_LVDS_TDP PADINDEX_OF_DISPLAYTOP_LVDS_TXP_D 266 #define PADINDEX_OF_LVDS_TDN PADINDEX_OF_DISPLAYTOP_LVDS_TXN_D 267 #define PADINDEX_OF_LVDS_TCLKP PADINDEX_OF_DISPLAYTOP_LVDS_TXP_CLK 268 #define PADINDEX_OF_LVDS_TCLKN PADINDEX_OF_DISPLAYTOP_LVDS_TXN_CLK 269 #define PADINDEX_OF_LVDS_ROUT PADINDEX_OF_DISPLAYTOP_LVDS_ROUT 270 #define PADINDEX_OF_LVDS_TEP PADINDEX_OF_DISPLAYTOP_LVDS_TXN_E 271 #define PADINDEX_OF_LVDS_TEN PADINDEX_OF_DISPLAYTOP_LVDS_TXN_E 272 #define NUMBER_OF_DISPTOP_CLKGEN_MODULE 5 273 274 enum disptop_clkgen_module_index { 275 res_conv_clkgen = 0, 276 lcdif_clkgen = 1, 277 to_mipi_clkgen = 2, 278 to_lvds_clkgen = 3, 279 hdmi_clkgen = 4, 280 }; 281 282 enum disptop_res_conv_iclk_cclk { 283 res_conv_iclk = 0, 284 res_conv_cclk = 1, 285 }; 286 287 enum disptop_res_conv_oclk { 288 res_conv_oclk = 1, 289 }; 290 291 enum disptop_lcdif_clk { 292 lcdif_pixel_clkx_n = 0, 293 lcdif_pixel_clk = 1, 294 }; 295 296 #define HDMI_SPDIF_CLKGEN 2 297 #define HDMI_SPDIF_CLKOUT 0 298 #define HDMI_I_VCLK_CLKOUT 0 299 #define PHY_BASEADDR_DISPTOP_CLKGEN0_MODULE \ 300 (PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x006000) 301 #define PHY_BASEADDR_DISPTOP_CLKGEN1_MODULE \ 302 (PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x007000) 303 #define PHY_BASEADDR_DISPTOP_CLKGEN2_MODULE \ 304 (PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x005000) 305 #define PHY_BASEADDR_DISPTOP_CLKGEN3_MODULE \ 306 (PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x008000) 307 #define PHY_BASEADDR_DISPTOP_CLKGEN4_MODULE \ 308 (PHY_BASEADDR_DISPLAYTOP_MODULE + OTHER_ADDR_OFFSET + 0x009000) 309 310 struct nx_disp_top_register_set { 311 u32 resconv_mux_ctrl; 312 u32 interconv_mux_ctrl; 313 u32 mipi_mux_ctrl; 314 u32 lvds_mux_ctrl; 315 u32 hdmifixctrl0; 316 u32 hdmisyncctrl0; 317 u32 hdmisyncctrl1; 318 u32 hdmisyncctrl2; 319 u32 hdmisyncctrl3; 320 u32 tftmpu_mux; 321 u32 hdmifieldctrl; 322 u32 greg0; 323 u32 greg1; 324 u32 greg2; 325 u32 greg3; 326 u32 greg4; 327 u32 greg5; 328 }; 329 330 int nx_disp_top_initialize(void); 331 u32 nx_disp_top_get_number_of_module(void); 332 333 u32 nx_disp_top_get_physical_address(void); 334 u32 nx_disp_top_get_size_of_register_set(void); 335 void nx_disp_top_set_base_address(void *base_address); 336 void *nx_disp_top_get_base_address(void); 337 int nx_disp_top_open_module(void); 338 int nx_disp_top_close_module(void); 339 int nx_disp_top_check_busy(void); 340 341 enum mux_index { 342 primary_mlc = 0, 343 secondary_mlc = 1, 344 resolution_conv = 2, 345 }; 346 347 enum prim_pad_mux_index { 348 padmux_primary_mlc = 0, 349 padmux_primary_mpu = 1, 350 padmux_secondary_mlc = 2, 351 padmux_resolution_conv = 3, 352 }; 353 354 void nx_disp_top_set_resconvmux(int benb, u32 sel); 355 void nx_disp_top_set_hdmimux(int benb, u32 sel); 356 void nx_disp_top_set_mipimux(int benb, u32 sel); 357 void nx_disp_top_set_lvdsmux(int benb, u32 sel); 358 void nx_disp_top_set_primary_mux(u32 sel); 359 void nx_disp_top_hdmi_set_vsync_start(u32 sel); 360 void nx_disp_top_hdmi_set_vsync_hsstart_end(u32 start, u32 end); 361 void nx_disp_top_hdmi_set_hactive_start(u32 sel); 362 void nx_disp_top_hdmi_set_hactive_end(u32 sel); 363 364 void nx_disp_top_set_hdmifield(u32 enable, u32 init_val, u32 vsynctoggle, 365 u32 hsynctoggle, u32 vsyncclr, u32 hsyncclr, 366 u32 field_use, u32 muxsel); 367 368 enum padclk_config { 369 padclk_clk = 0, 370 padclk_inv_clk = 1, 371 padclk_reserved_clk = 2, 372 padclk_reserved_inv_clk = 3, 373 padclk_clk_div2_0 = 4, 374 padclk_clk_div2_90 = 5, 375 padclk_clk_div2_180 = 6, 376 padclk_clk_div2_270 = 7, 377 }; 378 379 void nx_disp_top_set_padclock(u32 mux_index, u32 padclk_cfg); 380 void nx_disp_top_set_lcdif_enb(int enb); 381 void nx_disp_top_set_hdmifield(u32 enable, u32 init_val, u32 vsynctoggle, 382 u32 hsynctoggle, u32 vsyncclr, u32 hsyncclr, 383 u32 field_use, u32 muxsel); 384 385 #endif 386