1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019 Phytec Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
5 *
6 */
7
8/ {
9	model = "Phytec AM335x phyBOARD-REGOR";
10	compatible = "phytec,am335x-regor", "phytec,am335x-phycore-som", "ti,am33xx";
11
12	vcc3v3: fixedregulator@1 {
13		compatible = "regulator-fixed";
14		regulator-name = "vcc3v3";
15		regulator-min-microvolt = <3300000>;
16		regulator-max-microvolt = <3300000>;
17		regulator-boot-on;
18	};
19
20	/* User IO */
21	user_leds: user_leds {
22		compatible = "gpio-leds";
23		pinctrl-names = "default";
24		pinctrl-0 = <&user_leds_pins>;
25
26		run_stop-led {
27			gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
28			linux,default-trigger = "gpio";
29			default-state = "off";
30		};
31
32		error-led {
33			gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
34			linux,default-trigger = "gpio";
35			default-state = "off";
36		};
37	};
38};
39
40/* User Leds */
41&am33xx_pinmux {
42	user_leds_pins: pinmux_user_leds {
43		pinctrl-single,pins = <
44			AM33XX_IOPAD(0x8E0, PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* lcd_hsync.gpio2_22 */
45			AM33XX_IOPAD(0x994, PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* mcasp0_fsx.gpio3_15 */
46		>;
47	};
48};
49
50/* CAN Busses */
51&am33xx_pinmux {
52	dcan1_pins: pinmux_dcan1 {
53		pinctrl-single,pins = <
54			AM33XX_IOPAD(0x968, PIN_OUTPUT_PULLUP | MUX_MODE2)	/* uart0_ctsn.d_can1_tx */
55			AM33XX_IOPAD(0x96C, PIN_INPUT_PULLUP | MUX_MODE2)	/* uart0_rtsn.d_can1_rx */
56		>;
57	};
58};
59
60&dcan1 {
61	pinctrl-names = "default";
62	pinctrl-0 = <&dcan1_pins>;
63	status = "okay";
64};
65
66/* Ethernet */
67&am33xx_pinmux {
68	ethernet1_pins: pinmux_ethernet1 {
69		pinctrl-single,pins = <
70			AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a0.mii2_txen */
71			AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a1.mii2_rxdv */
72			AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a2.mii2_txd3 */
73			AM33XX_IOPAD(0x84C, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a3.mii2_txd2 */
74			AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a4.mii2_txd1 */
75			AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a5.mii2_txd0 */
76			AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a6.mii2_txclk */
77			AM33XX_IOPAD(0x85C, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a7.mii2_rxclk */
78			AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a8.mii2_rxd3 */
79			AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE1)	 /* gpmc_a9.mii2_rxd2 */
80			AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a10.mii2_rxd1 */
81			AM33XX_IOPAD(0x86C, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a11.mii2_rxd0 */
82			AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_wpn.mii2_rxerr */
83			AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ben1.mii2_col */
84		>;
85	};
86};
87
88&cpsw_emac1 {
89	phy-handle = <&phy1>;
90	phy-mode = "mii";
91	dual_emac_res_vlan = <2>;
92};
93
94&davinci_mdio {
95	phy1: ethernet-phy@1 {
96		reg = <1>;
97	};
98};
99
100&mac {
101	slaves = <2>;
102	pinctrl-names = "default";
103	pinctrl-0 = <&ethernet0_pins &ethernet1_pins>;
104	dual_emac = <1>;
105};
106
107/* GPIOs */
108&am33xx_pinmux {
109	pinctrl-names = "default";
110	pinctrl-0 = <&user_gpios_pins>;
111
112	user_gpios_pins: pinmux_user_gpios {
113		pinctrl-single,pins = <
114			/* DIGIN 1-4 */
115			AM33XX_IOPAD(0x82C, PIN_INPUT | MUX_MODE7)		/* gpmc_ad11.gpio0_27 */
116			AM33XX_IOPAD(0x828, PIN_INPUT | MUX_MODE7)		/* gpmc_ad10.gpio0_26 */
117			AM33XX_IOPAD(0x824, PIN_INPUT | MUX_MODE7)		/* gpmc_ad9.gpio0_23 */
118			AM33XX_IOPAD(0x820, PIN_INPUT | MUX_MODE7)		/* gpmc_ad8.gpio0_22 */
119			/* DIGOUT 1-4 */
120			AM33XX_IOPAD(0x83C, PIN_OUTPUT | MUX_MODE7)		/* gpmc_ad15.gpio1_15 */
121			AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE7)		/* gpmc_ad14.gpio1_14 */
122			AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE7)		/* gpmc_ad13.gpio1_13 */
123			AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE7)		/* gpmc_ad12.gpio1_12 */
124		>;
125	};
126};
127
128/* MMC */
129&am33xx_pinmux {
130	mmc1_pins: pinmux_mmc1 {
131		pinctrl-single,pins = <
132			AM33XX_IOPAD(0x8F0, PIN_INPUT_PULLUP | MUX_MODE0)
133			AM33XX_IOPAD(0x8F4, PIN_INPUT_PULLUP | MUX_MODE0)
134			AM33XX_IOPAD(0x8F8, PIN_INPUT_PULLUP | MUX_MODE0)
135			AM33XX_IOPAD(0x8FC, PIN_INPUT_PULLUP | MUX_MODE0)
136			AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)
137			AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)
138			AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE7)	/* spi0_cs1.mmc0_sdcd */
139		>;
140	};
141};
142
143&mmc1 {
144	vmmc-supply = <&vcc3v3>;
145	bus-width = <4>;
146	pinctrl-names = "default";
147	pinctrl-0 = <&mmc1_pins>;
148	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
149	status = "okay";
150};
151
152/* RTC */
153&i2c_rtc {
154	status = "okay";
155};
156
157/* UARTs */
158&am33xx_pinmux {
159	uart0_pins: pinmux_uart0 {
160		pinctrl-single,pins = <
161			AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)
162			AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
163		>;
164	};
165
166	uart2_pins: pinmux_uart2 {
167		pinctrl-single,pins = <
168			AM33XX_IOPAD(0x92C, PIN_INPUT_PULLUP | MUX_MODE1)	/* mii1_tx_clk.uart2_rxd */
169			AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_rx_clk.uart2_txd */
170		>;
171	};
172};
173
174&uart0 {
175	pinctrl-names = "default";
176	pinctrl-0 = <&uart0_pins>;
177	status = "okay";
178};
179
180&uart2 {
181	pinctrl-names = "default";
182	pinctrl-0 = <&uart2_pins>;
183	status = "okay";
184};
185
186/* RS485 - UART1 */
187&am33xx_pinmux {
188	uart1_rs485_pins: pinmux_uart1_rs485_pins {
189		pinctrl-single,pins = <
190			AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)
191			AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
192			AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLUP | MUX_MODE0)
193		>;
194	};
195};
196
197&uart1 {
198	pinctrl-names = "default";
199	pinctrl-0 = <&uart1_rs485_pins>;
200	status = "okay";
201	linux,rs485-enabled-at-boot-time;
202};
203