1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2018-2021 Marvell International Ltd. 4 */ 5 6#undef CP110_NAME 7#undef CP110_NUM 8#undef CP110_PCIE_MEM_SIZE 9#undef CP110_PCIEx_CPU_MEM_BASE 10#undef CP110_PCIEx_BUS_MEM_BASE 11 12/* CP110-1 Settings */ 13#define CP110_NAME cp1 14#define CP110_NUM 1 15#define CP110_PCIE_MEM_SIZE(iface) (0xf00000) 16#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) * 0x1000000) 17#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface)) 18 19#include "armada-cp110.dtsi" 20 21/ { 22 model = "Marvell CN9131 development board"; 23 compatible = "marvell,cn9131-db"; 24 25 aliases { 26 gpio3 = &cp1_gpio0; 27 gpio4 = &cp1_gpio1; 28 }; 29 30 cp1 { 31 config-space { 32 cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 { 33 compatible = "regulator-fixed"; 34 pinctrl-names = "default"; 35 pinctrl-0 = <&cp1_xhci0_vbus_pins>; 36 regulator-name = "cp1-xhci0-vbus"; 37 regulator-min-microvolt = <5000000>; 38 regulator-max-microvolt = <5000000>; 39 startup-delay-us = <100000>; 40 regulator-force-boot-off; 41 gpio = <&cp1_gpio0 3 GPIO_ACTIVE_HIGH>; 42 }; 43 cp1_reg_usb3_current_lim0: cp1_usb3_current_limiter@0 { 44 compatible = "regulator-fixed"; 45 regulator-min-microamp = <900000>; 46 regulator-max-microamp = <900000>; 47 regulator-force-boot-off; 48 gpio = <&cp1_gpio0 2 GPIO_ACTIVE_HIGH>; 49 }; 50 cp1_pcie_reset_pins: cp1-pcie-reset-pins { 51 marvell,pins = <0>; 52 marvell,function = <0>; 53 }; 54 }; 55 }; 56}; 57 58&cp1_i2c0 { 59 pinctrl-names = "default"; 60 pinctrl-0 = <&cp1_i2c0_pins>; 61 status = "okay"; 62 clock-frequency = <100000>; 63}; 64 65/* CON40 */ 66&cp1_pcie0 { 67 pinctrl-names = "default"; 68 pinctrl-0 = <&cp1_pcie_reset_pins>; 69 marvell,reset-gpio = <&cp1_gpio0 0 GPIO_ACTIVE_LOW>; 70 status = "okay"; 71 num-lanes = <2>; 72 /* non-prefetchable memory */ 73 ranges = <0x82000000 0 0xe2000000 0 0xe2000000 0 0xf00000>; 74}; 75 76&cp1_pinctl { 77 compatible = "marvell,mvebu-pinctrl", 78 "marvell,cp115-standalone-pinctrl"; 79 bank-name ="cp1-110"; 80 81 /* MPP Bus: 82 * [0-12] GPIO 83 * [13-16] SPI1 84 * [17-27] GPIO (Default) 85 * [28] SATA1_PRESENT_ACTIVEn 86 * [29-34] GPIO (Default) 87 * [35-36] xSMI 88 * [37-38] I2C0 89 * [39-62] GPIO 90 */ 91 /* 0 1 2 3 4 5 6 7 8 9 */ 92 pin-func = < 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 93 0x0 0x0 0x0 0x3 0x3 0x3 0x3 0x0 0x0 0x0 94 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9 0x0 95 0x0 0x0 0x0 0x0 0x0 0x7 0x7 0x2 0x2 0x0 96 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 97 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 98 0x0 0x0 0x0 >; 99 100 cp1_i2c0_pins: cp1-i2c-pins-0 { 101 marvell,pins = < 37 38 >; 102 marvell,function = <2>; 103 }; 104 cp1_spi0_pins: cp1-spi-pins-0 { 105 marvell,pins = < 13 14 15 16 >; 106 marvell,function = <3>; 107 }; 108 cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins { 109 marvell,pins = <3>; 110 marvell,function = <0>; 111 }; 112}; 113 114/* CON32 */ 115&cp1_sata0 { 116 status = "okay"; 117}; 118 119/* U24 */ 120&cp1_spi1 { 121 pinctrl-names = "default"; 122 pinctrl-0 = <&cp1_spi0_pins>; 123 reg = <0x700680 0x50>, /* control */ 124 <0x2000000 0x1000000>, /* CS0 */ 125 <0 0xffffffff>, /* CS1 */ 126 <0 0xffffffff>, /* CS2 */ 127 <0 0xffffffff>; /* CS3 */ 128 status = "okay"; 129 130 spi-flash@0 { 131 #address-cells = <0x1>; 132 #size-cells = <0x1>; 133 compatible = "jedec,spi-nor", "spi-flash"; 134 reg = <0x0>; 135 /* On-board MUX does not allow higher frequencies */ 136 spi-max-frequency = <40000000>; 137 138 partitions { 139 compatible = "fixed-partitions"; 140 #address-cells = <1>; 141 #size-cells = <1>; 142 143 partition@0 { 144 label = "U-Boot"; 145 reg = <0x0 0x200000>; 146 }; 147 148 partition@400000 { 149 label = "Filesystem"; 150 reg = <0x200000 0xe00000>; 151 }; 152 }; 153 }; 154}; 155 156/* CON58 */ 157&cp1_usb3_1 { 158 vbus-supply = <&cp1_reg_usb3_vbus0>; 159 current-limiter = <&cp1_reg_usb3_current_lim0>; 160 vbus-disable-delay = <500>; 161 status = "okay"; 162}; 163 164&cp1_utmi1 { 165 status = "okay"; 166}; 167