1// SPDX-License-Identifier: GPL-2.0+ 2// 3// Copyright (C) 2020 TQ-Systems GmbH 4 5/ { 6 aliases { 7 mmc1 = &usdhc2; 8 }; 9 10 chosen { 11 linux,stdout-path = &uart2; 12 stdout-path = &uart2; 13 }; 14 15 regulators { 16 reg_mba6_3p3v: regulator@1 { 17 compatible = "regulator-fixed"; 18 regulator-name = "supply-mba6-3p3v"; 19 reg = <1>; 20 regulator-min-microvolt = <3300000>; 21 regulator-max-microvolt = <3300000>; 22 regulator-always-on; 23 }; 24 25 reg_otgvbus: regulator@2 { 26 compatible = "regulator-fixed"; 27 reg = <2>; 28 pinctrl-names = "default"; 29 pinctrl-0 = <&pinctrl_reg_otgpwr>; 30 regulator-name = "otg-vbus-supply"; 31 regulator-min-microvolt = <5000000>; 32 regulator-max-microvolt = <5000000>; 33 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 34 enable-active-high; 35 vin_supply = <®_3p3v>; 36 }; 37 }; 38}; 39 40&fec { 41 phy-mode = "rgmii-id"; 42 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 43 phy-reset-duration = <1>; 44 phy-reset-post-delay = <100>; 45 phy-handle = <ðphy>; 46 status = "okay"; 47 48 mdio { 49 #address-cells = <1>; 50 #size-cells = <0>; 51 52 ethphy: ethernet-phy@3 { 53 compatible = "ethernet-phy-id0022.1622", 54 "ethernet-phy-ieee802.3-c22"; 55 reg = <3>; 56 force-master; 57 max-speed = <1000>; 58 interrupt-parent = <&gpio1>; 59 interrupts = <28 IRQ_TYPE_LEVEL_LOW>; 60 }; 61 }; 62}; 63 64&iomuxc { 65 pinctrl-names = "default"; 66 pinctrl-0 = <&pinctrl_hog>; 67 68 mba6 { 69 pinctrl_enet: enetgrp { 70 fsl,pins = < 71 /* FEC phy IRQ */ 72 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x00011008 73 /* FEC phy reset */ 74 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b099 75 /* DSE = 100, 100k up, SPEED = MED */ 76 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0xb0a0 77 MX6QDL_PAD_ENET_MDC__ENET_MDC 0xb0a0 78 /* DSE = 111, pull 100k up */ 79 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0xb038 80 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0xb038 81 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0xb038 82 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0xb038 83 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0xb038 84 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0xb038 85 /* DSE = 111, pull external */ 86 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x0038 87 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x0038 88 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x0038 89 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x0038 90 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x0038 91 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x0038 92 /* HYS = 1, DSE = 111, 100k up, SPEED = HIGH */ 93 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0f0 94 >; 95 }; 96 97 pinctrl_hog: hoggrp { 98 fsl,pins = < 99 MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x0001b099 /* LCD.PWR_EN */ 100 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0001b099 /* LCD.RESET */ 101 /* LCD.CONTRAST -> Rev 0100 only, not used on Rev.0200*/ 102 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099 103 104 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b099 105 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b099 106 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b099 107 108 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b099 109 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0001b099 110 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0001b099 111 MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0001b099 112 MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0001b099 113 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0001b099 114 MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0001b099 115 116 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0001b099 117 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0001b099 118 MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0001b099 119 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0001b099 120 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0001b099 121 122 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b099 123 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b099 124 MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b099 125 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x0001b099 126 127 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x0001b099 128 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x0001b099 129 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x0001b099 130 131 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b099 132 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001b099 133 >; 134 }; 135 136 pinctrl_reg_otgpwr: regotgpwrgrp { 137 fsl,pins = < 138 /* OTG_PWR */ 139 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b099 140 >; 141 }; 142 143 pinctrl_uart2: uart2grp { 144 fsl,pins = < 145 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099 146 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b099 147 >; 148 }; 149 150 pinctrl_usdhc2: usdhc2grp { 151 fsl,pins = < 152 /* CLK: 47k Pup SPD_LOW DSE 40Ohm SRE_FAST HYS */ 153 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00017071 154 /* SD2: 47k Pup SPD_LOW DSE 80Ohm SRE_FAST HYS */ 155 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017059 156 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017059 157 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017059 158 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017059 159 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017059 160 161 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b099 /* usdhc2 CD */ 162 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0001b099 /* usdhc2 WP */ 163 >; 164 }; 165 166 pinctrl_usbotg: usbotggrp { 167 fsl,pins = < 168 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0001b0b0 169 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x00017059 170 >; 171 }; 172 }; 173}; 174 175&uart2 { 176 pinctrl-names = "default"; 177 pinctrl-0 = <&pinctrl_uart2>; 178 status = "okay"; 179}; 180 181&usbh1 { 182 disable-over-current; 183 status = "okay"; 184}; 185 186&usbotg { 187 pinctrl-names = "default"; 188 pinctrl-0 = <&pinctrl_usbotg>; 189 dr_mode = "otg"; 190 vbus-supply = <®_otgvbus>; 191 status = "okay"; 192}; 193 194&usdhc2 { /* Baseboard Slot */ 195 pinctrl-names = "default"; 196 pinctrl-0 = <&pinctrl_usdhc2>; 197 vmmc-supply = <®_mba6_3p3v>; 198 bus-width = <4>; 199 no-1-8-v; 200 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; 201 wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 202 status = "okay"; 203}; 204 205&wdog1 { 206 status = "okay"; 207}; 208