1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 dmsc: dmsc@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 12 13 mbox-names = "rx", "tx"; 14 15 mboxes= <&secure_proxy_main 11>, 16 <&secure_proxy_main 13>; 17 18 reg-names = "debug_messages"; 19 reg = <0x00 0x44083000 0x0 0x1000>; 20 21 k3_pds: power-controller { 22 compatible = "ti,sci-pm-domain"; 23 #power-domain-cells = <2>; 24 }; 25 26 k3_clks: clocks { 27 compatible = "ti,k2g-sci-clk"; 28 #clock-cells = <2>; 29 }; 30 31 k3_reset: reset-controller { 32 compatible = "ti,sci-reset"; 33 #reset-cells = <2>; 34 }; 35 }; 36 37 mcu_conf: syscon@40f00000 { 38 compatible = "syscon", "simple-mfd"; 39 reg = <0x0 0x40f00000 0x0 0x20000>; 40 #address-cells = <1>; 41 #size-cells = <1>; 42 ranges = <0x0 0x0 0x40f00000 0x20000>; 43 44 phy_gmii_sel: phy@4040 { 45 compatible = "ti,am654-phy-gmii-sel"; 46 reg = <0x4040 0x4>; 47 #phy-cells = <1>; 48 }; 49 }; 50 51 chipid@43000014 { 52 compatible = "ti,am654-chipid"; 53 reg = <0x0 0x43000014 0x0 0x4>; 54 }; 55 56 wkup_pmx0: pinctrl@4301c000 { 57 compatible = "pinctrl-single"; 58 /* Proxy 0 addressing */ 59 reg = <0x00 0x4301c000 0x00 0x178>; 60 #pinctrl-cells = <1>; 61 pinctrl-single,register-width = <32>; 62 pinctrl-single,function-mask = <0xffffffff>; 63 }; 64 65 mcu_ram: sram@41c00000 { 66 compatible = "mmio-sram"; 67 reg = <0x00 0x41c00000 0x00 0x100000>; 68 ranges = <0x0 0x00 0x41c00000 0x100000>; 69 #address-cells = <1>; 70 #size-cells = <1>; 71 }; 72 73 wkup_uart0: serial@42300000 { 74 compatible = "ti,j721e-uart", "ti,am654-uart"; 75 reg = <0x00 0x42300000 0x00 0x100>; 76 reg-shift = <2>; 77 reg-io-width = <4>; 78 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 79 clock-frequency = <48000000>; 80 current-speed = <115200>; 81 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; 82 clocks = <&k3_clks 287 0>; 83 clock-names = "fclk"; 84 }; 85 86 mcu_uart0: serial@40a00000 { 87 compatible = "ti,j721e-uart", "ti,am654-uart"; 88 reg = <0x00 0x40a00000 0x00 0x100>; 89 reg-shift = <2>; 90 reg-io-width = <4>; 91 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 92 clock-frequency = <96000000>; 93 current-speed = <115200>; 94 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 95 clocks = <&k3_clks 149 0>; 96 clock-names = "fclk"; 97 }; 98 99 wkup_gpio_intr: interrupt-controller2 { 100 compatible = "ti,sci-intr"; 101 ti,intr-trigger-type = <1>; 102 interrupt-controller; 103 interrupt-parent = <&gic500>; 104 #interrupt-cells = <1>; 105 ti,sci = <&dmsc>; 106 ti,sci-dev-id = <137>; 107 ti,interrupt-ranges = <16 960 16>; 108 }; 109 110 wkup_gpio0: gpio@42110000 { 111 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 112 reg = <0x0 0x42110000 0x0 0x100>; 113 gpio-controller; 114 #gpio-cells = <2>; 115 interrupt-parent = <&wkup_gpio_intr>; 116 interrupts = <103>, <104>, <105>, <106>, <107>, <108>; 117 interrupt-controller; 118 #interrupt-cells = <2>; 119 ti,ngpio = <84>; 120 ti,davinci-gpio-unbanked = <0>; 121 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 122 clocks = <&k3_clks 113 0>; 123 clock-names = "gpio"; 124 }; 125 126 wkup_gpio1: gpio@42100000 { 127 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 128 reg = <0x0 0x42100000 0x0 0x100>; 129 gpio-controller; 130 #gpio-cells = <2>; 131 interrupt-parent = <&wkup_gpio_intr>; 132 interrupts = <112>, <113>, <114>, <115>, <116>, <117>; 133 interrupt-controller; 134 #interrupt-cells = <2>; 135 ti,ngpio = <84>; 136 ti,davinci-gpio-unbanked = <0>; 137 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 138 clocks = <&k3_clks 114 0>; 139 clock-names = "gpio"; 140 }; 141 142 mcu_i2c0: i2c@40b00000 { 143 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 144 reg = <0x0 0x40b00000 0x0 0x100>; 145 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 clock-names = "fck"; 149 clocks = <&k3_clks 194 0>; 150 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 151 }; 152 153 mcu_i2c1: i2c@40b10000 { 154 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 155 reg = <0x0 0x40b10000 0x0 0x100>; 156 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 157 #address-cells = <1>; 158 #size-cells = <0>; 159 clock-names = "fck"; 160 clocks = <&k3_clks 195 0>; 161 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 162 }; 163 164 wkup_i2c0: i2c@42120000 { 165 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 166 reg = <0x0 0x42120000 0x0 0x100>; 167 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 clock-names = "fck"; 171 clocks = <&k3_clks 197 0>; 172 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; 173 }; 174 175 fss: fss@47000000 { 176 compatible = "simple-bus"; 177 reg = <0x0 0x47000000 0x0 0x100>; 178 #address-cells = <2>; 179 #size-cells = <2>; 180 ranges; 181 182 hbmc_mux: hbmc-mux { 183 compatible = "mmio-mux"; 184 #mux-control-cells = <1>; 185 mux-reg-masks = <0x4 0x2>; /* HBMC select */ 186 }; 187 188 hbmc: hyperbus@47034000 { 189 compatible = "ti,j721e-hbmc", "ti,am654-hbmc"; 190 reg = <0x0 0x47034000 0x0 0x100>, 191 <0x5 0x00000000 0x1 0x0000000>; 192 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 193 #address-cells = <2>; 194 #size-cells = <1>; 195 mux-controls = <&hbmc_mux 0>; 196 assigned-clocks = <&k3_clks 102 0>; 197 assigned-clock-rates = <250000000>; 198 }; 199 200 ospi0: spi@47040000 { 201 compatible = "ti,am654-ospi"; 202 reg = <0x0 0x47040000 0x0 0x100>, 203 <0x5 0x00000000 0x1 0x0000000>; 204 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 205 cdns,fifo-depth = <256>; 206 cdns,fifo-width = <4>; 207 cdns,trigger-address = <0x0>; 208 clocks = <&k3_clks 103 0>; 209 assigned-clocks = <&k3_clks 103 0>; 210 assigned-clock-parents = <&k3_clks 103 2>; 211 assigned-clock-rates = <166666666>; 212 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 213 #address-cells = <1>; 214 #size-cells = <0>; 215 }; 216 217 ospi1: spi@47050000 { 218 compatible = "ti,am654-ospi"; 219 reg = <0x0 0x47050000 0x0 0x100>, 220 <0x7 0x00000000 0x1 0x00000000>; 221 interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; 222 cdns,fifo-depth = <256>; 223 cdns,fifo-width = <4>; 224 cdns,trigger-address = <0x0>; 225 clocks = <&k3_clks 104 0>; 226 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 227 #address-cells = <1>; 228 #size-cells = <0>; 229 }; 230 }; 231 232 tscadc0: tscadc@40200000 { 233 compatible = "ti,am3359-tscadc"; 234 reg = <0x0 0x40200000 0x0 0x1000>; 235 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 236 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 237 clocks = <&k3_clks 0 1>; 238 assigned-clocks = <&k3_clks 0 3>; 239 assigned-clock-rates = <60000000>; 240 clock-names = "adc_tsc_fck"; 241 dmas = <&main_udmap 0x7400>, 242 <&main_udmap 0x7401>; 243 dma-names = "fifo0", "fifo1"; 244 245 adc { 246 #io-channel-cells = <1>; 247 compatible = "ti,am3359-adc"; 248 }; 249 }; 250 251 tscadc1: tscadc@40210000 { 252 compatible = "ti,am3359-tscadc"; 253 reg = <0x0 0x40210000 0x0 0x1000>; 254 interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 255 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; 256 clocks = <&k3_clks 1 1>; 257 assigned-clocks = <&k3_clks 1 3>; 258 assigned-clock-rates = <60000000>; 259 clock-names = "adc_tsc_fck"; 260 dmas = <&main_udmap 0x7402>, 261 <&main_udmap 0x7403>; 262 dma-names = "fifo0", "fifo1"; 263 264 adc { 265 #io-channel-cells = <1>; 266 compatible = "ti,am3359-adc"; 267 }; 268 }; 269 270 mcu-navss { 271 compatible = "simple-mfd"; 272 #address-cells = <2>; 273 #size-cells = <2>; 274 ranges; 275 dma-coherent; 276 dma-ranges; 277 278 ti,sci-dev-id = <232>; 279 280 mcu_ringacc: ringacc@2b800000 { 281 compatible = "ti,am654-navss-ringacc"; 282 reg = <0x0 0x2b800000 0x0 0x400000>, 283 <0x0 0x2b000000 0x0 0x400000>, 284 <0x0 0x28590000 0x0 0x100>, 285 <0x0 0x2a500000 0x0 0x40000>; 286 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 287 ti,num-rings = <286>; 288 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 289 ti,sci = <&dmsc>; 290 ti,sci-dev-id = <235>; 291 msi-parent = <&main_udmass_inta>; 292 }; 293 294 mcu_udmap: dma-controller@285c0000 { 295 compatible = "ti,j721e-navss-mcu-udmap"; 296 reg = <0x0 0x285c0000 0x0 0x100>, 297 <0x0 0x2a800000 0x0 0x40000>, 298 <0x0 0x2aa00000 0x0 0x40000>; 299 reg-names = "gcfg", "rchanrt", "tchanrt"; 300 msi-parent = <&main_udmass_inta>; 301 #dma-cells = <1>; 302 303 ti,sci = <&dmsc>; 304 ti,sci-dev-id = <236>; 305 ti,ringacc = <&mcu_ringacc>; 306 307 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 308 <0x0f>; /* TX_HCHAN */ 309 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 310 <0x0b>; /* RX_HCHAN */ 311 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 312 }; 313 }; 314 315 mcu_cpsw: ethernet@46000000 { 316 compatible = "ti,j721e-cpsw-nuss"; 317 #address-cells = <2>; 318 #size-cells = <2>; 319 reg = <0x0 0x46000000 0x0 0x200000>; 320 reg-names = "cpsw_nuss"; 321 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; 322 dma-coherent; 323 clocks = <&k3_clks 18 22>; 324 clock-names = "fck"; 325 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; 326 327 dmas = <&mcu_udmap 0xf000>, 328 <&mcu_udmap 0xf001>, 329 <&mcu_udmap 0xf002>, 330 <&mcu_udmap 0xf003>, 331 <&mcu_udmap 0xf004>, 332 <&mcu_udmap 0xf005>, 333 <&mcu_udmap 0xf006>, 334 <&mcu_udmap 0xf007>, 335 <&mcu_udmap 0x7000>; 336 dma-names = "tx0", "tx1", "tx2", "tx3", 337 "tx4", "tx5", "tx6", "tx7", 338 "rx"; 339 340 ethernet-ports { 341 #address-cells = <1>; 342 #size-cells = <0>; 343 344 cpsw_port1: port@1 { 345 reg = <1>; 346 ti,mac-only; 347 label = "port1"; 348 ti,syscon-efuse = <&mcu_conf 0x200>; 349 phys = <&phy_gmii_sel 1>; 350 }; 351 }; 352 353 davinci_mdio: mdio@f00 { 354 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 355 reg = <0x0 0xf00 0x0 0x100>; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 clocks = <&k3_clks 18 22>; 359 clock-names = "fck"; 360 bus_freq = <1000000>; 361 }; 362 363 cpts@3d000 { 364 compatible = "ti,am65-cpts"; 365 reg = <0x0 0x3d000 0x0 0x400>; 366 clocks = <&k3_clks 18 2>; 367 clock-names = "cpts"; 368 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 369 interrupt-names = "cpts"; 370 ti,cpts-ext-ts-inputs = <4>; 371 ti,cpts-periodic-outputs = <2>; 372 }; 373 }; 374 375 mcu_r5fss0: r5fss@41000000 { 376 compatible = "ti,j721e-r5fss"; 377 ti,cluster-mode = <1>; 378 #address-cells = <1>; 379 #size-cells = <1>; 380 ranges = <0x41000000 0x00 0x41000000 0x20000>, 381 <0x41400000 0x00 0x41400000 0x20000>; 382 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 383 384 mcu_r5fss0_core0: r5f@41000000 { 385 compatible = "ti,j721e-r5f"; 386 reg = <0x41000000 0x00008000>, 387 <0x41010000 0x00008000>; 388 reg-names = "atcm", "btcm"; 389 ti,sci = <&dmsc>; 390 ti,sci-dev-id = <250>; 391 ti,sci-proc-ids = <0x01 0xff>; 392 resets = <&k3_reset 250 1>; 393 firmware-name = "j7-mcu-r5f0_0-fw"; 394 ti,atcm-enable = <1>; 395 ti,btcm-enable = <1>; 396 ti,loczrama = <1>; 397 }; 398 399 mcu_r5fss0_core1: r5f@41400000 { 400 compatible = "ti,j721e-r5f"; 401 reg = <0x41400000 0x00008000>, 402 <0x41410000 0x00008000>; 403 reg-names = "atcm", "btcm"; 404 ti,sci = <&dmsc>; 405 ti,sci-dev-id = <251>; 406 ti,sci-proc-ids = <0x02 0xff>; 407 resets = <&k3_reset 251 1>; 408 firmware-name = "j7-mcu-r5f0_1-fw"; 409 ti,atcm-enable = <1>; 410 ti,btcm-enable = <1>; 411 ti,loczrama = <1>; 412 }; 413 }; 414}; 415