1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for KV260 revA Carrier Card
4 *
5 * (C) Copyright 2020, Xilinx, Inc.
6 *
7 * SD level shifter:
8 * "A" – A01 board un-modified (NXP)
9 * "Y" – A01 board modified with legacy interposer (Nexperia)
10 * "Z" – A01 board modified with Diode interposer
11 *
12 * Michal Simek <michal.simek@xilinx.com>
13 */
14
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/net/ti-dp83867.h>
17 #include <dt-bindings/phy/phy.h>
18 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19
20/dts-v1/;
21/plugin/;
22
23/{
24	compatible = "xlnx,zynqmp-sk-kv260-revA",
25		     "xlnx,zynqmp-sk-kv260-revY",
26		     "xlnx,zynqmp-sk-kv260-revZ",
27		     "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
28
29	fragment1 {
30		target = <&i2c1>; /* I2C_SCK C23/C24 - MIO from SOM */
31
32		__overlay__ {
33			#address-cells = <1>;
34			#size-cells = <0>;
35			pinctrl-names = "default", "gpio";
36			pinctrl-0 = <&pinctrl_i2c1_default>;
37			pinctrl-1 = <&pinctrl_i2c1_gpio>;
38			scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
39			sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
40
41			u14: ina260@40 { /* u14 */
42				compatible = "ti,ina260";
43				#io-channel-cells = <1>;
44				label = "ina260-u14";
45				reg = <0x40>;
46			};
47			/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
48		};
49	};
50
51	fragment1a {
52		target = <&amba>;
53		__overlay__ {
54			ina260-u14 {
55				compatible = "iio-hwmon";
56				io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
57			};
58
59			si5332_0: si5332_0 { /* u17 */
60				compatible = "fixed-clock";
61				#clock-cells = <0>;
62				clock-frequency = <125000000>;
63			};
64
65			si5332_1: si5332_1 { /* u17 */
66				compatible = "fixed-clock";
67				#clock-cells = <0>;
68				clock-frequency = <25000000>;
69			};
70
71			si5332_2: si5332_2 { /* u17 */
72				compatible = "fixed-clock";
73				#clock-cells = <0>;
74				clock-frequency = <48000000>;
75			};
76
77			si5332_3: si5332_3 { /* u17 */
78				compatible = "fixed-clock";
79				#clock-cells = <0>;
80				clock-frequency = <24000000>;
81			};
82
83			si5332_4: si5332_4 { /* u17 */
84				compatible = "fixed-clock";
85				#clock-cells = <0>;
86				clock-frequency = <26000000>;
87			};
88
89			si5332_5: si5332_5 { /* u17 */
90				compatible = "fixed-clock";
91				#clock-cells = <0>;
92				clock-frequency = <27000000>;
93			};
94		};
95	};
96
97/* DP/USB 3.0 and SATA */
98	fragment2 {
99		target = <&psgtr>;
100		__overlay__ {
101			status = "okay";
102			/* pcie, usb3, sata */
103			clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
104			clock-names = "ref0", "ref1", "ref2";
105		};
106	};
107
108	fragment3 {
109		target = <&sata>;
110		__overlay__ {
111			status = "okay";
112			/* SATA OOB timing settings */
113			ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
114			ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
115			ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
116			ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
117			ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
118			ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
119			ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
120			ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
121			phy-names = "sata-phy";
122			phys = <&psgtr 3 PHY_TYPE_SATA 1 2>;
123		};
124	};
125
126	fragment4 {
127		target = <&zynqmp_dpsub>;
128		__overlay__ {
129			status = "disabled";
130			phy-names = "dp-phy0", "dp-phy1";
131			phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
132		};
133	};
134
135	fragment9 {
136		target = <&zynqmp_dpdma>;
137		__overlay__ {
138			status = "okay";
139		};
140	};
141
142	fragment10 {
143		target = <&usb0>;
144		__overlay__ {
145			status = "okay";
146			pinctrl-names = "default";
147			pinctrl-0 = <&pinctrl_usb0_default>;
148			usbhub: usb5744 { /* u43 */
149				compatible = "microchip,usb5744";
150				reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
151			};
152		};
153	};
154
155	fragment11 {
156		target = <&dwc3_0>;
157		__overlay__ {
158			status = "okay";
159			dr_mode = "host";
160			snps,usb3_lpm_capable;
161			phy-names = "usb3-phy";
162			phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
163			maximum-speed = "super-speed";
164		};
165	};
166
167	fragment12 {
168		target = <&sdhci1>; /* on CC with tuned parameters */
169		__overlay__ {
170			status = "okay";
171			pinctrl-names = "default";
172			pinctrl-0 = <&pinctrl_sdhci1_default>;
173			/*
174			 * SD 3.0 requires level shifter and this property
175			 * should be removed if the board has level shifter and
176			 * need to work in UHS mode
177			 */
178			no-1-8-v;
179			disable-wp;
180			xlnx,mio-bank = <1>;
181		};
182	};
183
184	fragment13 {
185		target = <&gem3>; /* required by spec */
186		__overlay__ {
187			#address-cells = <1>;
188			#size-cells = <0>;
189			status = "okay";
190			pinctrl-names = "default";
191			pinctrl-0 = <&pinctrl_gem3_default>;
192			phy-handle = <&phy0>;
193			phy-mode = "rgmii-id";
194
195			mdio: mdio {
196				#address-cells = <1>;
197				#size-cells = <0>;
198				reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
199				reset-delay-us = <2>;
200
201				phy0: ethernet-phy@1 {
202					#phy-cells = <1>;
203					reg = <1>;
204					ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
205					ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
206					ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
207					ti,dp83867-rxctrl-strap-quirk;
208				};
209			};
210		};
211	};
212
213	fragment14 {
214		target = <&pinctrl0>; /* required by spec */
215		__overlay__ {
216			status = "okay";
217
218			pinctrl_uart1_default: uart1-default {
219				conf {
220					groups = "uart1_9_grp";
221					slew-rate = <SLEW_RATE_SLOW>;
222					power-source = <IO_STANDARD_LVCMOS18>;
223					drive-strength = <12>;
224				};
225
226				conf-rx {
227					pins = "MIO37";
228					bias-high-impedance;
229				};
230
231				conf-tx {
232					pins = "MIO36";
233					bias-disable;
234				};
235
236				mux {
237					groups = "uart1_9_grp";
238					function = "uart1";
239				};
240			};
241
242			pinctrl_i2c1_default: i2c1-default {
243				conf {
244					groups = "i2c1_6_grp";
245					bias-pull-up;
246					slew-rate = <SLEW_RATE_SLOW>;
247					power-source = <IO_STANDARD_LVCMOS18>;
248				};
249
250				mux {
251					groups = "i2c1_6_grp";
252					function = "i2c1";
253				};
254			};
255
256			pinctrl_i2c1_gpio: i2c1-gpio {
257				conf {
258					groups = "gpio0_24_grp", "gpio0_25_grp";
259					slew-rate = <SLEW_RATE_SLOW>;
260					power-source = <IO_STANDARD_LVCMOS18>;
261				};
262
263				mux {
264					groups = "gpio0_24_grp", "gpio0_25_grp";
265					function = "gpio0";
266				};
267			};
268
269			pinctrl_gem3_default: gem3-default {
270				conf {
271					groups = "ethernet3_0_grp";
272					slew-rate = <SLEW_RATE_SLOW>;
273					power-source = <IO_STANDARD_LVCMOS18>;
274				};
275
276				conf-rx {
277					pins = "MIO70", "MIO72", "MIO74";
278					bias-high-impedance;
279					low-power-disable;
280				};
281
282				conf-bootstrap {
283					pins = "MIO71", "MIO73", "MIO75";
284					bias-disable;
285					low-power-disable;
286				};
287
288				conf-tx {
289					pins = "MIO64", "MIO65", "MIO66",
290					       "MIO67", "MIO68", "MIO69";
291					bias-disable;
292					low-power-enable;
293				};
294
295				conf-mdio {
296					groups = "mdio3_0_grp";
297					slew-rate = <SLEW_RATE_SLOW>;
298					power-source = <IO_STANDARD_LVCMOS18>;
299					bias-disable;
300				};
301
302				mux-mdio {
303					function = "mdio3";
304					groups = "mdio3_0_grp";
305				};
306
307				mux {
308					function = "ethernet3";
309					groups = "ethernet3_0_grp";
310				};
311			};
312
313			pinctrl_usb0_default: usb0-default {
314				conf {
315					groups = "usb0_0_grp";
316					slew-rate = <SLEW_RATE_SLOW>;
317					power-source = <IO_STANDARD_LVCMOS18>;
318				};
319
320				conf-rx {
321					pins = "MIO52", "MIO53", "MIO55";
322					bias-high-impedance;
323				};
324
325				conf-tx {
326					pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
327					"MIO60", "MIO61", "MIO62", "MIO63";
328					bias-disable;
329				};
330
331				mux {
332					groups = "usb0_0_grp";
333					function = "usb0";
334				};
335			};
336
337			pinctrl_sdhci1_default: sdhci1-default {
338				conf {
339					groups = "sdio1_0_grp";
340					slew-rate = <SLEW_RATE_SLOW>;
341					power-source = <IO_STANDARD_LVCMOS18>;
342					bias-disable;
343				};
344
345				conf-cd {
346					groups = "sdio1_cd_0_grp";
347					bias-high-impedance;
348					bias-pull-up;
349					slew-rate = <SLEW_RATE_SLOW>;
350					power-source = <IO_STANDARD_LVCMOS18>;
351				};
352
353				mux-cd {
354					groups = "sdio1_cd_0_grp";
355					function = "sdio1_cd";
356				};
357
358				mux {
359					groups = "sdio1_0_grp";
360					function = "sdio1";
361				};
362			};
363		};
364	};
365	fragment15 {
366		target = <&uart1>;
367		__overlay__ {
368			status = "okay";
369			pinctrl-names = "default";
370			pinctrl-0 = <&pinctrl_uart1_default>;
371		};
372	};
373};
374