1if ARCH_STM32MP 2 3config SPL 4 select SPL_BOARD_INIT 5 select SPL_CLK 6 select SPL_DM 7 select SPL_DM_SEQ_ALIAS 8 select SPL_DRIVERS_MISC_SUPPORT 9 select SPL_FRAMEWORK 10 select SPL_GPIO_SUPPORT 11 select SPL_LIBCOMMON_SUPPORT 12 select SPL_LIBGENERIC_SUPPORT 13 select SPL_OF_CONTROL 14 select SPL_OF_TRANSLATE 15 select SPL_PINCTRL 16 select SPL_REGMAP 17 select SPL_DM_RESET 18 select SPL_SERIAL_SUPPORT 19 select SPL_SYSCON 20 select SPL_WATCHDOG_SUPPORT if WATCHDOG 21 imply BOOTSTAGE_STASH if SPL_BOOTSTAGE 22 imply SPL_BOOTSTAGE if BOOTSTAGE 23 imply SPL_DISPLAY_PRINT 24 imply SPL_LIBDISK_SUPPORT 25 imply SPL_SPI_LOAD if SPL_SPI_SUPPORT 26 27config SYS_SOC 28 default "stm32mp" 29 30config SYS_MALLOC_LEN 31 default 0x2000000 32 33config ENV_SIZE 34 default 0x2000 35 36config STM32MP15x 37 bool "Support STMicroelectronics STM32MP15x Soc" 38 select ARCH_SUPPORT_PSCI if !TFABOOT 39 select ARM_SMCCC if TFABOOT 40 select CPU_V7A 41 select CPU_V7_HAS_NONSEC if !TFABOOT 42 select CPU_V7_HAS_VIRT 43 select OF_BOARD_SETUP 44 select PINCTRL_STM32 45 select STM32_RCC 46 select STM32_RESET 47 select STM32_SERIAL 48 select SYS_ARCH_TIMER 49 imply CMD_NVEDIT_INFO 50 imply SYSRESET_PSCI if TFABOOT 51 imply SYSRESET_SYSCON if !TFABOOT 52 help 53 support of STMicroelectronics SOC STM32MP15x family 54 STM32MP157, STM32MP153 or STM32MP151 55 STMicroelectronics MPU with core ARMv7 56 dual core A7 for STM32MP157/3, monocore for STM32MP151 57 target all the STMicroelectronics board with SOC STM32MP1 family 58 59choice 60 prompt "STM32MP15x board select" 61 optional 62 63config TARGET_ST_STM32MP15x 64 bool "STMicroelectronics STM32MP15x boards" 65 select STM32MP15x 66 imply BOOTCOUNT_LIMIT 67 imply BOOTSTAGE 68 imply CMD_BOOTCOUNT 69 imply CMD_BOOTSTAGE 70 imply CMD_CLS if CMD_BMP 71 imply DISABLE_CONSOLE 72 imply PRE_CONSOLE_BUFFER 73 imply SILENT_CONSOLE 74 help 75 target the STMicroelectronics board with SOC STM32MP15x 76 managed by board/st/stm32mp1: 77 Evalulation board (EV1) or Discovery board (DK1 and DK2). 78 The difference between board are managed with devicetree 79 80config TARGET_MICROGEA_STM32MP1 81 bool "Engicam MicroGEA STM32MP1 SOM" 82 select STM32MP15x 83 imply BOOTCOUNT_LIMIT 84 imply BOOTSTAGE 85 imply CMD_BOOTCOUNT 86 imply CMD_BOOTSTAGE 87 imply CMD_CLS if CMD_BMP 88 imply DISABLE_CONSOLE 89 imply PRE_CONSOLE_BUFFER 90 imply SILENT_CONSOLE 91 help 92 MicroGEA STM32MP1 is a STM32MP157A based Micro SOM. 93 94 MicroGEA STM32MP1 MicroDev 2.0: 95 * MicroDev 2.0 is a general purpose miniature carrier board with CAN, 96 LTE and LVDS panel interfaces. 97 * MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board 98 for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board. 99 100 MicroGEA STM32MP1 MicroDev 2.0 7" OF: 101 * 7" OF is a capacitive touch 7" Open Frame panel solutions with LVDS 102 panel and toucscreen. 103 * MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with 104 pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0 7" 105 Open Frame Solution board. 106 107config TARGET_ICORE_STM32MP1 108 bool "Engicam i.Core STM32MP1 SOM" 109 select STM32MP15x 110 imply BOOTCOUNT_LIMIT 111 imply BOOTSTAGE 112 imply CMD_BOOTCOUNT 113 imply CMD_BOOTSTAGE 114 imply CMD_CLS if CMD_BMP 115 imply DISABLE_CONSOLE 116 imply PRE_CONSOLE_BUFFER 117 imply SILENT_CONSOLE 118 help 119 i.Core STM32MP1 is an EDIMM SOM based on STM32MP157A. 120 121 i.Core STM32MP1 EDIMM2.2: 122 * EDIMM2.2 is a Form Factor Capacitive Evaluation Board. 123 * i.Core STM32MP1 needs to mount on top of EDIMM2.2 for 124 creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit. 125 126 i.Core STM32MP1 C.TOUCH 2.0 127 * C.TOUCH 2.0 is a general purpose Carrier board. 128 * i.Core STM32MP1 needs to mount on top of this Carrier board 129 for creating complete i.Core STM32MP1 C.TOUCH 2.0 board. 130 131config TARGET_DH_STM32MP1_PDK2 132 bool "DH STM32MP1 PDK2" 133 select STM32MP15x 134 imply BOOTCOUNT_LIMIT 135 imply CMD_BOOTCOUNT 136 help 137 Target the DH PDK2 development kit with STM32MP15x SoM. 138 139endchoice 140 141config SYS_TEXT_BASE 142 default 0xC0100000 143 144config NR_DRAM_BANKS 145 default 1 146 147config DDR_CACHEABLE_SIZE 148 hex "Size of the DDR marked cacheable in pre-reloc stage" 149 default 0x10000000 if TFABOOT 150 default 0x40000000 151 help 152 Define the size of the DDR marked as cacheable in U-Boot 153 pre-reloc stage. 154 This option can be useful to avoid speculatif access 155 to secured area of DDR used by TF-A or OP-TEE before U-Boot 156 initialization. 157 The areas marked "no-map" in device tree should be located 158 before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE. 159 160config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 161 hex "Partition on MMC2 to use to load U-Boot from" 162 depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION 163 default 1 164 help 165 Partition on the second MMC to load U-Boot from when the MMC is being 166 used in raw mode 167 168config STM32_ETZPC 169 bool "STM32 Extended TrustZone Protection" 170 depends on STM32MP15x 171 default y 172 help 173 Say y to enable STM32 Extended TrustZone Protection 174 175config CMD_STM32KEY 176 bool "command stm32key to fuse public key hash" 177 default y 178 help 179 fuse public key hash in corresponding fuse used to authenticate 180 binary. 181 182config PRE_CON_BUF_ADDR 183 default 0xC02FF000 184 185config PRE_CON_BUF_SZ 186 default 4096 187 188config BOOTSTAGE_STASH_ADDR 189 default 0xC3000000 190 191if BOOTCOUNT_LIMIT 192config SYS_BOOTCOUNT_SINGLEWORD 193 default y 194 195# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21) 196config SYS_BOOTCOUNT_ADDR 197 default 0x5C00A154 198endif 199 200if DEBUG_UART 201 202config DEBUG_UART_BOARD_INIT 203 default y 204 205# debug on UART4 by default 206config DEBUG_UART_BASE 207 default 0x40010000 208 209# clock source is HSI on reset 210config DEBUG_UART_CLOCK 211 default 64000000 212endif 213 214source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig" 215source "board/dhelectronics/dh_stm32mp1/Kconfig" 216source "board/engicam/stm32mp1/Kconfig" 217source "board/st/stm32mp1/Kconfig" 218 219endif 220