1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 /*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 */
5
6 #define LOG_CATEGORY LOGC_ARCH
7
8 #include <common.h>
9 #include <clk.h>
10 #include <cpu_func.h>
11 #include <debug_uart.h>
12 #include <env.h>
13 #include <init.h>
14 #include <log.h>
15 #include <misc.h>
16 #include <net.h>
17 #include <asm/io.h>
18 #include <asm/arch/bsec.h>
19 #include <asm/arch/stm32.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/global_data.h>
22 #include <dm/device.h>
23 #include <dm/uclass.h>
24 #include <linux/bitops.h>
25
26 /* RCC register */
27 #define RCC_TZCR (STM32_RCC_BASE + 0x00)
28 #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
29 #define RCC_BDCR (STM32_RCC_BASE + 0x0140)
30 #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
31 #define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210)
32 #define RCC_BDCR_VSWRST BIT(31)
33 #define RCC_BDCR_RTCSRC GENMASK(17, 16)
34 #define RCC_DBGCFGR_DBGCKEN BIT(8)
35
36 /* Security register */
37 #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
38 #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
39
40 #define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
41 #define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
42 #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
43
44 #define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
45
46 #define PWR_CR1 (STM32_PWR_BASE + 0x00)
47 #define PWR_MCUCR (STM32_PWR_BASE + 0x14)
48 #define PWR_CR1_DBP BIT(8)
49 #define PWR_MCUCR_SBF BIT(6)
50
51 /* DBGMCU register */
52 #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
53 #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
54 #define DBGMCU_APB4FZ1_IWDG2 BIT(2)
55 #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
56 #define DBGMCU_IDC_DEV_ID_SHIFT 0
57 #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
58 #define DBGMCU_IDC_REV_ID_SHIFT 16
59
60 /* GPIOZ registers */
61 #define GPIOZ_SECCFGR 0x54004030
62
63 /* boot interface from Bootrom
64 * - boot instance = bit 31:16
65 * - boot device = bit 15:0
66 */
67 #define BOOTROM_PARAM_ADDR 0x2FFC0078
68 #define BOOTROM_MODE_MASK GENMASK(15, 0)
69 #define BOOTROM_MODE_SHIFT 0
70 #define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
71 #define BOOTROM_INSTANCE_SHIFT 16
72
73 /* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
74 #define RPN_SHIFT 0
75 #define RPN_MASK GENMASK(7, 0)
76
77 /* Package = bit 27:29 of OTP16
78 * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
79 * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
80 * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm
81 * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm
82 * - others: Reserved
83 */
84 #define PKG_SHIFT 27
85 #define PKG_MASK GENMASK(2, 0)
86
87 /*
88 * early TLB into the .data section so that it not get cleared
89 * with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
90 */
91 u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
92
93 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
94 #ifndef CONFIG_TFABOOT
security_init(void)95 static void security_init(void)
96 {
97 /* Disable the backup domain write protection */
98 /* the protection is enable at each reset by hardware */
99 /* And must be disable by software */
100 setbits_le32(PWR_CR1, PWR_CR1_DBP);
101
102 while (!(readl(PWR_CR1) & PWR_CR1_DBP))
103 ;
104
105 /* If RTC clock isn't enable so this is a cold boot then we need
106 * to reset the backup domain
107 */
108 if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
109 setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
110 while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
111 ;
112 clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
113 }
114
115 /* allow non secure access in Write/Read for all peripheral */
116 writel(GENMASK(25, 0), ETZPC_DECPROT0);
117
118 /* Open SYSRAM for no secure access */
119 writel(0x0, ETZPC_TZMA1_SIZE);
120
121 /* enable TZC1 TZC2 clock */
122 writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
123
124 /* Region 0 set to no access by default */
125 /* bit 0 / 16 => nsaid0 read/write Enable
126 * bit 1 / 17 => nsaid1 read/write Enable
127 * ...
128 * bit 15 / 31 => nsaid15 read/write Enable
129 */
130 writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
131 /* bit 30 / 31 => Secure Global Enable : write/read */
132 /* bit 0 / 1 => Region Enable for filter 0/1 */
133 writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
134
135 /* Enable Filter 0 and 1 */
136 setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
137
138 /* RCC trust zone deactivated */
139 writel(0x0, RCC_TZCR);
140
141 /* TAMP: deactivate the internal tamper
142 * Bit 23 ITAMP8E: monotonic counter overflow
143 * Bit 20 ITAMP5E: RTC calendar overflow
144 * Bit 19 ITAMP4E: HSE monitoring
145 * Bit 18 ITAMP3E: LSE monitoring
146 * Bit 16 ITAMP1E: RTC power domain supply monitoring
147 */
148 writel(0x0, TAMP_CR1);
149
150 /* GPIOZ: deactivate the security */
151 writel(BIT(0), RCC_MP_AHB5ENSETR);
152 writel(0x0, GPIOZ_SECCFGR);
153 }
154 #endif /* CONFIG_TFABOOT */
155
156 /*
157 * Debug init
158 */
dbgmcu_init(void)159 static void dbgmcu_init(void)
160 {
161 /*
162 * Freeze IWDG2 if Cortex-A7 is in debug mode
163 * done in TF-A for TRUSTED boot and
164 * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE
165 */
166 if (!IS_ENABLED(CONFIG_TFABOOT) && bsec_dbgswenable()) {
167 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
168 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
169 }
170 }
171
spl_board_init(void)172 void spl_board_init(void)
173 {
174 dbgmcu_init();
175 }
176 #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
177
178 #if !defined(CONFIG_TFABOOT) && \
179 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
180 /* get bootmode from ROM code boot context: saved in TAMP register */
update_bootmode(void)181 static void update_bootmode(void)
182 {
183 u32 boot_mode;
184 u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
185 u32 bootrom_device, bootrom_instance;
186
187 /* enable TAMP clock = RTCAPBEN */
188 writel(BIT(8), RCC_MP_APB5ENSETR);
189
190 /* read bootrom context */
191 bootrom_device =
192 (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
193 bootrom_instance =
194 (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
195 boot_mode =
196 ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
197 ((bootrom_instance << BOOT_INSTANCE_SHIFT) &
198 BOOT_INSTANCE_MASK);
199
200 /* save the boot mode in TAMP backup register */
201 clrsetbits_le32(TAMP_BOOT_CONTEXT,
202 TAMP_BOOT_MODE_MASK,
203 boot_mode << TAMP_BOOT_MODE_SHIFT);
204 }
205 #endif
206
get_bootmode(void)207 u32 get_bootmode(void)
208 {
209 /* read bootmode from TAMP backup register */
210 return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
211 TAMP_BOOT_MODE_SHIFT;
212 }
213
214 /*
215 * weak function overidde: set the DDR/SYSRAM executable before to enable the
216 * MMU and configure DACR, for early early_enable_caches (SPL or pre-reloc)
217 */
dram_bank_mmu_setup(int bank)218 void dram_bank_mmu_setup(int bank)
219 {
220 struct bd_info *bd = gd->bd;
221 int i;
222 phys_addr_t start;
223 phys_size_t size;
224
225 if (IS_ENABLED(CONFIG_SPL_BUILD)) {
226 start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE);
227 size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE);
228 } else if (gd->flags & GD_FLG_RELOC) {
229 /* bd->bi_dram is available only after relocation */
230 start = bd->bi_dram[bank].start;
231 size = bd->bi_dram[bank].size;
232 } else {
233 /* mark cacheable and executable the beggining of the DDR */
234 start = STM32_DDR_BASE;
235 size = CONFIG_DDR_CACHEABLE_SIZE;
236 }
237
238 for (i = start >> MMU_SECTION_SHIFT;
239 i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
240 i++)
241 set_section_dcache(i, DCACHE_DEFAULT_OPTION);
242 }
243 /*
244 * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
245 * MMU/TLB is updated in enable_caches() for U-Boot after relocation
246 * or is deactivated in U-Boot entry function start.S::cpu_init_cp15
247 */
early_enable_caches(void)248 static void early_enable_caches(void)
249 {
250 /* I-cache is already enabled in start.S: cpu_init_cp15 */
251
252 if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
253 return;
254
255 if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) {
256 gd->arch.tlb_size = PGTABLE_SIZE;
257 gd->arch.tlb_addr = (unsigned long)&early_tlb;
258 }
259
260 /* enable MMU (default configuration) */
261 dcache_enable();
262 }
263
264 /*
265 * Early system init
266 */
arch_cpu_init(void)267 int arch_cpu_init(void)
268 {
269 u32 boot_mode;
270
271 early_enable_caches();
272
273 /* early armv7 timer init: needed for polling */
274 timer_init();
275
276 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
277 #ifndef CONFIG_TFABOOT
278 security_init();
279 update_bootmode();
280 #endif
281 /* Reset Coprocessor state unless it wakes up from Standby power mode */
282 if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) {
283 writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE);
284 writel(0, TAMP_COPRO_RSC_TBL_ADDRESS);
285 }
286 #endif
287
288 boot_mode = get_bootmode();
289
290 if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) &&
291 (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
292 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
293 #if defined(CONFIG_DEBUG_UART) && \
294 !defined(CONFIG_TFABOOT) && \
295 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
296 else
297 debug_uart_init();
298 #endif
299
300 return 0;
301 }
302
enable_caches(void)303 void enable_caches(void)
304 {
305 /* I-cache is already enabled in start.S: icache_enable() not needed */
306
307 /* deactivate the data cache, early enabled in arch_cpu_init() */
308 dcache_disable();
309 /*
310 * update MMU after relocation and enable the data cache
311 * warning: the TLB location udpated in board_f.c::reserve_mmu
312 */
313 dcache_enable();
314 }
315
read_idc(void)316 static u32 read_idc(void)
317 {
318 /* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */
319 if (bsec_dbgswenable()) {
320 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
321
322 return readl(DBGMCU_IDC);
323 }
324
325 if (CONFIG_IS_ENABLED(STM32MP15x))
326 return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */
327 else
328 return 0x0;
329 }
330
get_cpu_dev(void)331 u32 get_cpu_dev(void)
332 {
333 return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
334 }
335
get_cpu_rev(void)336 u32 get_cpu_rev(void)
337 {
338 return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
339 }
340
get_otp(int index,int shift,int mask)341 static u32 get_otp(int index, int shift, int mask)
342 {
343 int ret;
344 struct udevice *dev;
345 u32 otp = 0;
346
347 ret = uclass_get_device_by_driver(UCLASS_MISC,
348 DM_DRIVER_GET(stm32mp_bsec),
349 &dev);
350
351 if (!ret)
352 ret = misc_read(dev, STM32_BSEC_SHADOW(index),
353 &otp, sizeof(otp));
354
355 return (otp >> shift) & mask;
356 }
357
358 /* Get Device Part Number (RPN) from OTP */
get_cpu_rpn(void)359 static u32 get_cpu_rpn(void)
360 {
361 return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
362 }
363
get_cpu_type(void)364 u32 get_cpu_type(void)
365 {
366 return (get_cpu_dev() << 16) | get_cpu_rpn();
367 }
368
369 /* Get Package options from OTP */
get_cpu_package(void)370 u32 get_cpu_package(void)
371 {
372 return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
373 }
374
375 static const char * const soc_type[] = {
376 "????",
377 "151C", "151A", "151F", "151D",
378 "153C", "153A", "153F", "153D",
379 "157C", "157A", "157F", "157D"
380 };
381
382 static const char * const soc_pkg[] = { "??", "AD", "AC", "AB", "AA" };
383 static const char * const soc_rev[] = { "?", "A", "B", "Z" };
384
get_cpu_string_offsets(unsigned int * type,unsigned int * pkg,unsigned int * rev)385 static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg,
386 unsigned int *rev)
387 {
388 u32 cpu_type = get_cpu_type();
389 u32 ct = cpu_type & ~(BIT(7) | BIT(0));
390 u32 cm = ((cpu_type & BIT(7)) >> 6) | (cpu_type & BIT(0));
391 u32 cp = get_cpu_package();
392
393 /* Bits 0 and 7 are the ACDF, 00:C 01:A 10:F 11:D */
394 switch (ct) {
395 case CPU_STM32MP151Cxx:
396 *type = cm + 1;
397 break;
398 case CPU_STM32MP153Cxx:
399 *type = cm + 5;
400 break;
401 case CPU_STM32MP157Cxx:
402 *type = cm + 9;
403 break;
404 default:
405 *type = 0;
406 break;
407 }
408
409 /* Package */
410 switch (cp) {
411 case PKG_AA_LBGA448:
412 case PKG_AB_LBGA354:
413 case PKG_AC_TFBGA361:
414 case PKG_AD_TFBGA257:
415 *pkg = cp;
416 break;
417 default:
418 *pkg = 0;
419 break;
420 }
421
422 /* Revision */
423 switch (get_cpu_rev()) {
424 case CPU_REVA:
425 *rev = 1;
426 break;
427 case CPU_REVB:
428 *rev = 2;
429 break;
430 case CPU_REVZ:
431 *rev = 3;
432 break;
433 default:
434 *rev = 0;
435 break;
436 }
437 }
438
get_soc_name(char name[SOC_NAME_SIZE])439 void get_soc_name(char name[SOC_NAME_SIZE])
440 {
441 unsigned int type, pkg, rev;
442
443 get_cpu_string_offsets(&type, &pkg, &rev);
444
445 snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s",
446 soc_type[type], soc_pkg[pkg], soc_rev[rev]);
447 }
448
449 #if defined(CONFIG_DISPLAY_CPUINFO)
print_cpuinfo(void)450 int print_cpuinfo(void)
451 {
452 char name[SOC_NAME_SIZE];
453
454 get_soc_name(name);
455 printf("CPU: %s\n", name);
456
457 return 0;
458 }
459 #endif /* CONFIG_DISPLAY_CPUINFO */
460
setup_boot_mode(void)461 static void setup_boot_mode(void)
462 {
463 const u32 serial_addr[] = {
464 STM32_USART1_BASE,
465 STM32_USART2_BASE,
466 STM32_USART3_BASE,
467 STM32_UART4_BASE,
468 STM32_UART5_BASE,
469 STM32_USART6_BASE,
470 STM32_UART7_BASE,
471 STM32_UART8_BASE
472 };
473 char cmd[60];
474 u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
475 u32 boot_mode =
476 (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
477 unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
478 u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
479 struct udevice *dev;
480
481 log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
482 __func__, boot_ctx, boot_mode, instance, forced_mode);
483 switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
484 case BOOT_SERIAL_UART:
485 if (instance > ARRAY_SIZE(serial_addr))
486 break;
487 /* serial : search associated node in devicetree */
488 sprintf(cmd, "serial@%x", serial_addr[instance]);
489 if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) {
490 /* restore console on error */
491 if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL))
492 gd->flags &= ~(GD_FLG_SILENT |
493 GD_FLG_DISABLE_CONSOLE);
494 log_err("uart%d = %s not found in device tree!\n",
495 instance + 1, cmd);
496 break;
497 }
498 sprintf(cmd, "%d", dev_seq(dev));
499 env_set("boot_device", "serial");
500 env_set("boot_instance", cmd);
501
502 /* restore console on uart when not used */
503 if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && gd->cur_serial_dev != dev) {
504 gd->flags &= ~(GD_FLG_SILENT |
505 GD_FLG_DISABLE_CONSOLE);
506 log_info("serial boot with console enabled!\n");
507 }
508 break;
509 case BOOT_SERIAL_USB:
510 env_set("boot_device", "usb");
511 env_set("boot_instance", "0");
512 break;
513 case BOOT_FLASH_SD:
514 case BOOT_FLASH_EMMC:
515 sprintf(cmd, "%d", instance);
516 env_set("boot_device", "mmc");
517 env_set("boot_instance", cmd);
518 break;
519 case BOOT_FLASH_NAND:
520 env_set("boot_device", "nand");
521 env_set("boot_instance", "0");
522 break;
523 case BOOT_FLASH_SPINAND:
524 env_set("boot_device", "spi-nand");
525 env_set("boot_instance", "0");
526 break;
527 case BOOT_FLASH_NOR:
528 env_set("boot_device", "nor");
529 env_set("boot_instance", "0");
530 break;
531 default:
532 log_debug("unexpected boot mode = %x\n", boot_mode);
533 break;
534 }
535
536 switch (forced_mode) {
537 case BOOT_FASTBOOT:
538 log_info("Enter fastboot!\n");
539 env_set("preboot", "env set preboot; fastboot 0");
540 break;
541 case BOOT_STM32PROG:
542 env_set("boot_device", "usb");
543 env_set("boot_instance", "0");
544 break;
545 case BOOT_UMS_MMC0:
546 case BOOT_UMS_MMC1:
547 case BOOT_UMS_MMC2:
548 log_info("Enter UMS!\n");
549 instance = forced_mode - BOOT_UMS_MMC0;
550 sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
551 env_set("preboot", cmd);
552 break;
553 case BOOT_RECOVERY:
554 env_set("preboot", "env set preboot; run altbootcmd");
555 break;
556 case BOOT_NORMAL:
557 break;
558 default:
559 log_debug("unexpected forced boot mode = %x\n", forced_mode);
560 break;
561 }
562
563 /* clear TAMP for next reboot */
564 clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
565 }
566
567 /*
568 * If there is no MAC address in the environment, then it will be initialized
569 * (silently) from the value in the OTP.
570 */
setup_mac_address(void)571 __weak int setup_mac_address(void)
572 {
573 #if defined(CONFIG_NET)
574 int ret;
575 int i;
576 u32 otp[2];
577 uchar enetaddr[6];
578 struct udevice *dev;
579
580 /* MAC already in environment */
581 if (eth_env_get_enetaddr("ethaddr", enetaddr))
582 return 0;
583
584 ret = uclass_get_device_by_driver(UCLASS_MISC,
585 DM_DRIVER_GET(stm32mp_bsec),
586 &dev);
587 if (ret)
588 return ret;
589
590 ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC),
591 otp, sizeof(otp));
592 if (ret < 0)
593 return ret;
594
595 for (i = 0; i < 6; i++)
596 enetaddr[i] = ((uint8_t *)&otp)[i];
597
598 if (!is_valid_ethaddr(enetaddr)) {
599 log_err("invalid MAC address in OTP %pM\n", enetaddr);
600 return -EINVAL;
601 }
602 log_debug("OTP MAC address = %pM\n", enetaddr);
603 ret = eth_env_set_enetaddr("ethaddr", enetaddr);
604 if (ret)
605 log_err("Failed to set mac address %pM from OTP: %d\n", enetaddr, ret);
606 #endif
607
608 return 0;
609 }
610
setup_serial_number(void)611 static int setup_serial_number(void)
612 {
613 char serial_string[25];
614 u32 otp[3] = {0, 0, 0 };
615 struct udevice *dev;
616 int ret;
617
618 if (env_get("serial#"))
619 return 0;
620
621 ret = uclass_get_device_by_driver(UCLASS_MISC,
622 DM_DRIVER_GET(stm32mp_bsec),
623 &dev);
624 if (ret)
625 return ret;
626
627 ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL),
628 otp, sizeof(otp));
629 if (ret < 0)
630 return ret;
631
632 sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]);
633 env_set("serial#", serial_string);
634
635 return 0;
636 }
637
setup_soc_type_pkg_rev(void)638 static void setup_soc_type_pkg_rev(void)
639 {
640 unsigned int type, pkg, rev;
641
642 get_cpu_string_offsets(&type, &pkg, &rev);
643
644 env_set("soc_type", soc_type[type]);
645 env_set("soc_pkg", soc_pkg[pkg]);
646 env_set("soc_rev", soc_rev[rev]);
647 }
648
arch_misc_init(void)649 int arch_misc_init(void)
650 {
651 setup_boot_mode();
652 setup_mac_address();
653 setup_serial_number();
654 setup_soc_type_pkg_rev();
655
656 return 0;
657 }
658