1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
4 * Copyright (C) Jasbir Matharu
5 * Copyright (C) UDOO Team
6 *
7 * Author: Breno Lima <breno.lima@nxp.com>
8 * Author: Francesco Montefoschi <francesco.monte@gmail.com>
9 */
10
11 #include <init.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/crm_regs.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/iomux.h>
16 #include <asm/arch/mx6-pins.h>
17 #include <asm/global_data.h>
18 #include <asm/gpio.h>
19 #include <asm/mach-imx/iomux-v3.h>
20 #include <dm.h>
21 #include <env.h>
22 #include <asm/arch/crm_regs.h>
23 #include <asm/io.h>
24 #include <asm/mach-imx/mxc_i2c.h>
25 #include <asm/arch/sys_proto.h>
26 #include <spl.h>
27 #include <linux/delay.h>
28 #include <linux/sizes.h>
29 #include <common.h>
30 #include <i2c.h>
31 #include <power/pmic.h>
32 #include <power/pfuze3000_pmic.h>
33 #include <malloc.h>
34
35 DECLARE_GLOBAL_DATA_PTR;
36
37 enum {
38 UDOO_NEO_TYPE_BASIC,
39 UDOO_NEO_TYPE_BASIC_KS,
40 UDOO_NEO_TYPE_FULL,
41 UDOO_NEO_TYPE_EXTENDED,
42 };
43
44 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
45 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
46 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
47
48 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
49 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
50 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
51
52 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
53 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
54 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
55 PAD_CTL_ODE)
56
57 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
58 PAD_CTL_SPEED_MED | \
59 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
60
61 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
62 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
63
64 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
65 PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST)
66
67 #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
68 PAD_CTL_DSE_40ohm)
69
70 #define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
71 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
72 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
73 #define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) | \
74 MUX_MODE_SION)
75
dram_init(void)76 int dram_init(void)
77 {
78 gd->ram_size = imx_ddr_size();
79 return 0;
80 }
81
82 #ifdef CONFIG_SYS_I2C_MXC
83 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
84 /* I2C1 for PMIC */
85 static struct i2c_pads_info i2c_pad_info1 = {
86 .scl = {
87 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
88 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
89 .gp = IMX_GPIO_NR(1, 0),
90 },
91 .sda = {
92 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
93 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
94 .gp = IMX_GPIO_NR(1, 1),
95 },
96 };
97 #endif
98
99 #ifdef CONFIG_POWER
power_init_board(void)100 int power_init_board(void)
101 {
102 struct pmic *p;
103 int ret;
104 unsigned int reg, rev_id;
105
106 ret = power_pfuze3000_init(PFUZE3000_I2C_BUS);
107 if (ret)
108 return ret;
109
110 p = pmic_get("PFUZE3000");
111 ret = pmic_probe(p);
112 if (ret)
113 return ret;
114
115 pmic_reg_read(p, PFUZE3000_DEVICEID, ®);
116 pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
117 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
118
119 /* disable Low Power Mode during standby mode */
120 pmic_reg_read(p, PFUZE3000_LDOGCTL, ®);
121 reg |= 0x1;
122 ret = pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
123 if (ret)
124 return ret;
125
126 ret = pmic_reg_write(p, PFUZE3000_SW1AMODE, 0xc);
127 if (ret)
128 return ret;
129
130 ret = pmic_reg_write(p, PFUZE3000_SW1BMODE, 0xc);
131 if (ret)
132 return ret;
133
134 ret = pmic_reg_write(p, PFUZE3000_SW2MODE, 0xc);
135 if (ret)
136 return ret;
137
138 ret = pmic_reg_write(p, PFUZE3000_SW3MODE, 0xc);
139 if (ret)
140 return ret;
141
142 /* set SW1A standby voltage 0.975V */
143 pmic_reg_read(p, PFUZE3000_SW1ASTBY, ®);
144 reg &= ~0x3f;
145 reg |= PFUZE3000_SW1AB_SETP(9750);
146 ret = pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
147 if (ret)
148 return ret;
149
150 /* set SW1B standby voltage 0.975V */
151 pmic_reg_read(p, PFUZE3000_SW1BSTBY, ®);
152 reg &= ~0x3f;
153 reg |= PFUZE3000_SW1AB_SETP(9750);
154 ret = pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
155 if (ret)
156 return ret;
157
158 /* set SW1A/VDD_ARM_IN step ramp up time from 16us to 4us/25mV */
159 pmic_reg_read(p, PFUZE3000_SW1ACONF, ®);
160 reg &= ~0xc0;
161 reg |= 0x40;
162 ret = pmic_reg_write(p, PFUZE3000_SW1ACONF, reg);
163 if (ret)
164 return ret;
165
166 /* set SW1B/VDD_SOC_IN step ramp up time from 16us to 4us/25mV */
167 pmic_reg_read(p, PFUZE3000_SW1BCONF, ®);
168 reg &= ~0xc0;
169 reg |= 0x40;
170 ret = pmic_reg_write(p, PFUZE3000_SW1BCONF, reg);
171 if (ret)
172 return ret;
173
174 /* set VDD_ARM_IN to 1.350V */
175 pmic_reg_read(p, PFUZE3000_SW1AVOLT, ®);
176 reg &= ~0x3f;
177 reg |= PFUZE3000_SW1AB_SETP(13500);
178 ret = pmic_reg_write(p, PFUZE3000_SW1AVOLT, reg);
179 if (ret)
180 return ret;
181
182 /* set VDD_SOC_IN to 1.350V */
183 pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®);
184 reg &= ~0x3f;
185 reg |= PFUZE3000_SW1AB_SETP(13500);
186 ret = pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
187 if (ret)
188 return ret;
189
190 /* set DDR_1_5V to 1.350V */
191 pmic_reg_read(p, PFUZE3000_SW3VOLT, ®);
192 reg &= ~0x0f;
193 reg |= PFUZE3000_SW3_SETP(13500);
194 ret = pmic_reg_write(p, PFUZE3000_SW3VOLT, reg);
195 if (ret)
196 return ret;
197
198 /* set VGEN2_1V5 to 1.5V */
199 pmic_reg_read(p, PFUZE3000_VLDO2CTL, ®);
200 reg &= ~0x0f;
201 reg |= PFUZE3000_VLDO_SETP(15000);
202 /* enable */
203 reg |= 0x10;
204 ret = pmic_reg_write(p, PFUZE3000_VLDO2CTL, reg);
205 if (ret)
206 return ret;
207
208 return 0;
209 }
210 #endif
211
212 static iomux_v3_cfg_t const uart1_pads[] = {
213 MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
214 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
215 };
216
217 static iomux_v3_cfg_t const phy_control_pads[] = {
218 /* 25MHz Ethernet PHY Clock */
219 MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M |
220 MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
221 };
222
223 static iomux_v3_cfg_t const board_recognition_pads[] = {
224 /*Connected to R184*/
225 MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG,
226 /*Connected to R185*/
227 MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG,
228 };
229
230 static iomux_v3_cfg_t const wdog_b_pad = {
231 MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
232 };
233
234 static iomux_v3_cfg_t const peri_3v3_pads[] = {
235 MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
236 };
237
setup_iomux_uart(void)238 static void setup_iomux_uart(void)
239 {
240 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
241 }
242
setup_fec(void)243 static int setup_fec(void)
244 {
245 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
246 int reg;
247
248 imx_iomux_v3_setup_multiple_pads(phy_control_pads,
249 ARRAY_SIZE(phy_control_pads));
250
251 /* Reset PHY */
252 gpio_direction_output(IMX_GPIO_NR(2, 1) , 0);
253 udelay(10000);
254 gpio_set_value(IMX_GPIO_NR(2, 1), 1);
255 udelay(100);
256
257 reg = readl(&anatop->pll_enet);
258 reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
259 writel(reg, &anatop->pll_enet);
260
261 return enable_fec_anatop_clock(0, ENET_25MHZ);
262 }
263
board_init(void)264 int board_init(void)
265 {
266 /* Address of boot parameters */
267 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
268
269 /*
270 * Because kernel set WDOG_B mux before pad with the commone pinctrl
271 * framwork now and wdog reset will be triggered once set WDOG_B mux
272 * with default pad setting, we set pad setting here to workaround this.
273 * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
274 * as GPIO mux firstly here to workaround it.
275 */
276 imx_iomux_v3_setup_pad(wdog_b_pad);
277
278 /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
279 imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
280 ARRAY_SIZE(peri_3v3_pads));
281
282 /* Active high for ncp692 */
283 gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
284
285 #ifdef CONFIG_SYS_I2C_MXC
286 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
287 #endif
288
289 return 0;
290 }
291
get_board_value(void)292 static int get_board_value(void)
293 {
294 int r184, r185;
295
296 imx_iomux_v3_setup_multiple_pads(board_recognition_pads,
297 ARRAY_SIZE(board_recognition_pads));
298
299 gpio_direction_input(IMX_GPIO_NR(4, 13));
300 gpio_direction_input(IMX_GPIO_NR(4, 0));
301
302 r184 = gpio_get_value(IMX_GPIO_NR(4, 13));
303 r185 = gpio_get_value(IMX_GPIO_NR(4, 0));
304
305 /*
306 * Machine selection -
307 * Machine r184, r185
308 * ---------------------------------
309 * Basic 0 0
310 * Basic Ks 0 1
311 * Full 1 0
312 * Extended 1 1
313 */
314
315 return (r184 << 1) + r185;
316 }
317
board_early_init_f(void)318 int board_early_init_f(void)
319 {
320 setup_iomux_uart();
321 setup_fec();
322
323 return 0;
324 }
325
board_string(void)326 static char *board_string(void)
327 {
328 switch (get_board_value()) {
329 case UDOO_NEO_TYPE_BASIC:
330 return "BASIC";
331 case UDOO_NEO_TYPE_BASIC_KS:
332 return "BASICKS";
333 case UDOO_NEO_TYPE_FULL:
334 return "FULL";
335 case UDOO_NEO_TYPE_EXTENDED:
336 return "EXTENDED";
337 }
338 return "UNDEFINED";
339 }
340
checkboard(void)341 int checkboard(void)
342 {
343 printf("Board: UDOO Neo %s\n", board_string());
344 return 0;
345 }
346
board_late_init(void)347 int board_late_init(void)
348 {
349 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
350 env_set("board_name", board_string());
351 #endif
352
353 return 0;
354 }
355
356 #ifdef CONFIG_SPL_BUILD
357
358 #include <linux/libfdt.h>
359 #include <asm/arch/mx6-ddr.h>
360
361 static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
362 .dram_dqm0 = 0x00000028,
363 .dram_dqm1 = 0x00000028,
364 .dram_dqm2 = 0x00000028,
365 .dram_dqm3 = 0x00000028,
366 .dram_ras = 0x00000020,
367 .dram_cas = 0x00000020,
368 .dram_odt0 = 0x00000020,
369 .dram_odt1 = 0x00000020,
370 .dram_sdba2 = 0x00000000,
371 .dram_sdcke0 = 0x00003000,
372 .dram_sdcke1 = 0x00003000,
373 .dram_sdclk_0 = 0x00000030,
374 .dram_sdqs0 = 0x00000028,
375 .dram_sdqs1 = 0x00000028,
376 .dram_sdqs2 = 0x00000028,
377 .dram_sdqs3 = 0x00000028,
378 .dram_reset = 0x00000020,
379 };
380
381 static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
382 .grp_addds = 0x00000020,
383 .grp_ddrmode_ctl = 0x00020000,
384 .grp_ddrpke = 0x00000000,
385 .grp_ddrmode = 0x00020000,
386 .grp_b0ds = 0x00000028,
387 .grp_b1ds = 0x00000028,
388 .grp_ctlds = 0x00000020,
389 .grp_ddr_type = 0x000c0000,
390 .grp_b2ds = 0x00000028,
391 .grp_b3ds = 0x00000028,
392 };
393
394 static const struct mx6_mmdc_calibration neo_mmcd_calib = {
395 .p0_mpwldectrl0 = 0x000E000B,
396 .p0_mpwldectrl1 = 0x000E0010,
397 .p0_mpdgctrl0 = 0x41600158,
398 .p0_mpdgctrl1 = 0x01500140,
399 .p0_mprddlctl = 0x3A383E3E,
400 .p0_mpwrdlctl = 0x3A383C38,
401 };
402
403 static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = {
404 .p0_mpwldectrl0 = 0x001E0022,
405 .p0_mpwldectrl1 = 0x001C0019,
406 .p0_mpdgctrl0 = 0x41540150,
407 .p0_mpdgctrl1 = 0x01440138,
408 .p0_mprddlctl = 0x403E4644,
409 .p0_mpwrdlctl = 0x3C3A4038,
410 };
411
412 /* MT41K256M16 */
413 static struct mx6_ddr3_cfg neo_mem_ddr = {
414 .mem_speed = 1600,
415 .density = 4,
416 .width = 16,
417 .banks = 8,
418 .rowaddr = 15,
419 .coladdr = 10,
420 .pagesz = 2,
421 .trcd = 1375,
422 .trcmin = 4875,
423 .trasmin = 3500,
424 };
425
426 /* MT41K128M16 */
427 static struct mx6_ddr3_cfg neo_basic_mem_ddr = {
428 .mem_speed = 1600,
429 .density = 2,
430 .width = 16,
431 .banks = 8,
432 .rowaddr = 14,
433 .coladdr = 10,
434 .pagesz = 2,
435 .trcd = 1375,
436 .trcmin = 4875,
437 .trasmin = 3500,
438 };
439
ccgr_init(void)440 static void ccgr_init(void)
441 {
442 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
443
444 writel(0xFFFFFFFF, &ccm->CCGR0);
445 writel(0xFFFFFFFF, &ccm->CCGR1);
446 writel(0xFFFFFFFF, &ccm->CCGR2);
447 writel(0xFFFFFFFF, &ccm->CCGR3);
448 writel(0xFFFFFFFF, &ccm->CCGR4);
449 writel(0xFFFFFFFF, &ccm->CCGR5);
450 writel(0xFFFFFFFF, &ccm->CCGR6);
451 writel(0xFFFFFFFF, &ccm->CCGR7);
452 }
453
spl_dram_init(void)454 static void spl_dram_init(void)
455 {
456 int board = get_board_value();
457
458 struct mx6_ddr_sysinfo sysinfo = {
459 .dsize = 1, /* width of data bus: 1 = 32 bits */
460 .cs_density = 24,
461 .ncs = 1,
462 .cs1_mirror = 0,
463 .rtt_wr = 2,
464 .rtt_nom = 2, /* RTT_Nom = RZQ/2 */
465 .walat = 1, /* Write additional latency */
466 .ralat = 5, /* Read additional latency */
467 .mif3_mode = 3, /* Command prediction working mode */
468 .bi_on = 1, /* Bank interleaving enabled */
469 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
470 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
471 };
472
473 mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
474 if (board == UDOO_NEO_TYPE_BASIC || board == UDOO_NEO_TYPE_BASIC_KS)
475 mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib,
476 &neo_basic_mem_ddr);
477 else
478 mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr);
479 }
480
board_init_f(ulong dummy)481 void board_init_f(ulong dummy)
482 {
483 ccgr_init();
484
485 /* setup AIPS and disable watchdog */
486 arch_cpu_init();
487
488 board_early_init_f();
489
490 /* setup GP timer */
491 timer_init();
492
493 /* UART clocks enabled and gd valid - init serial console */
494 preloader_console_init();
495
496 /* DDR initialization */
497 spl_dram_init();
498
499 /* Clear the BSS. */
500 memset(__bss_start, 0, __bss_end - __bss_start);
501
502 /* load/boot image from boot device */
503 board_init_r(NULL, 0);
504 }
505
506 #endif
507