1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Pin Control driver for SuperH Pin Function Controller.
4 *
5 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
6 *
7 * Copyright (C) 2008 Magnus Damm
8 * Copyright (C) 2009 - 2012 Paul Mundt
9 * Copyright (C) 2017 Marek Vasut
10 */
11
12 #define DRV_NAME "sh-pfc"
13
14 #include <common.h>
15 #include <dm.h>
16 #include <errno.h>
17 #include <dm/device_compat.h>
18 #include <dm/devres.h>
19 #include <dm/pinctrl.h>
20 #include <linux/bitops.h>
21 #include <linux/bug.h>
22 #include <linux/io.h>
23 #include <linux/sizes.h>
24
25 #include "sh_pfc.h"
26
27 enum sh_pfc_model {
28 SH_PFC_R8A7790 = 0,
29 SH_PFC_R8A7791,
30 SH_PFC_R8A7792,
31 SH_PFC_R8A7793,
32 SH_PFC_R8A7794,
33 SH_PFC_R8A7795,
34 SH_PFC_R8A7796,
35 SH_PFC_R8A774A1,
36 SH_PFC_R8A774B1,
37 SH_PFC_R8A774C0,
38 SH_PFC_R8A774E1,
39 SH_PFC_R8A77965,
40 SH_PFC_R8A77970,
41 SH_PFC_R8A77980,
42 SH_PFC_R8A77990,
43 SH_PFC_R8A77995,
44 };
45
46 struct sh_pfc_pin_config {
47 u32 type;
48 const char *name;
49 };
50
51 struct sh_pfc_pinctrl {
52 struct sh_pfc *pfc;
53
54 struct sh_pfc_pin_config *configs;
55 };
56
57 struct sh_pfc_pin_range {
58 u16 start;
59 u16 end;
60 };
61
62 struct sh_pfc_pinctrl_priv {
63 struct sh_pfc pfc;
64 struct sh_pfc_pinctrl pmx;
65 };
66
sh_pfc_get_pin_index(struct sh_pfc * pfc,unsigned int pin)67 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
68 {
69 unsigned int offset;
70 unsigned int i;
71
72 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
73 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
74
75 if (pin <= range->end)
76 return pin >= range->start
77 ? offset + pin - range->start : -1;
78
79 offset += range->end - range->start + 1;
80 }
81
82 return -EINVAL;
83 }
84
sh_pfc_enum_in_range(u16 enum_id,const struct pinmux_range * r)85 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
86 {
87 if (enum_id < r->begin)
88 return 0;
89
90 if (enum_id > r->end)
91 return 0;
92
93 return 1;
94 }
95
sh_pfc_read_raw_reg(void __iomem * mapped_reg,unsigned int reg_width)96 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
97 {
98 switch (reg_width) {
99 case 8:
100 return readb(mapped_reg);
101 case 16:
102 return readw(mapped_reg);
103 case 32:
104 return readl(mapped_reg);
105 }
106
107 BUG();
108 return 0;
109 }
110
sh_pfc_write_raw_reg(void __iomem * mapped_reg,unsigned int reg_width,u32 data)111 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
112 u32 data)
113 {
114 switch (reg_width) {
115 case 8:
116 writeb(data, mapped_reg);
117 return;
118 case 16:
119 writew(data, mapped_reg);
120 return;
121 case 32:
122 writel(data, mapped_reg);
123 return;
124 }
125
126 BUG();
127 }
128
sh_pfc_read(struct sh_pfc * pfc,u32 reg)129 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
130 {
131 return sh_pfc_read_raw_reg((void __iomem *)(uintptr_t)reg, 32);
132 }
133
sh_pfc_unlock_reg(struct sh_pfc * pfc,u32 reg,u32 data)134 static void sh_pfc_unlock_reg(struct sh_pfc *pfc, u32 reg, u32 data)
135 {
136 u32 unlock;
137
138 if (!pfc->info->unlock_reg)
139 return;
140
141 if (pfc->info->unlock_reg >= 0x80000000UL)
142 unlock = pfc->info->unlock_reg;
143 else
144 /* unlock_reg is a mask */
145 unlock = reg & ~pfc->info->unlock_reg;
146
147 sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)unlock, 32, ~data);
148 }
149
sh_pfc_write(struct sh_pfc * pfc,u32 reg,u32 data)150 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
151 {
152 sh_pfc_unlock_reg(pfc, reg, data);
153 sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)reg, 32, data);
154 }
155
sh_pfc_config_reg_helper(struct sh_pfc * pfc,const struct pinmux_cfg_reg * crp,unsigned int in_pos,void __iomem ** mapped_regp,u32 * maskp,unsigned int * posp)156 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
157 const struct pinmux_cfg_reg *crp,
158 unsigned int in_pos,
159 void __iomem **mapped_regp, u32 *maskp,
160 unsigned int *posp)
161 {
162 unsigned int k;
163
164 *mapped_regp = (void __iomem *)(uintptr_t)crp->reg;
165
166 if (crp->field_width) {
167 *maskp = (1 << crp->field_width) - 1;
168 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
169 } else {
170 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
171 *posp = crp->reg_width;
172 for (k = 0; k <= in_pos; k++)
173 *posp -= crp->var_field_width[k];
174 }
175 }
176
sh_pfc_write_config_reg(struct sh_pfc * pfc,const struct pinmux_cfg_reg * crp,unsigned int field,u32 value)177 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
178 const struct pinmux_cfg_reg *crp,
179 unsigned int field, u32 value)
180 {
181 void __iomem *mapped_reg;
182 unsigned int pos;
183 u32 mask, data;
184
185 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
186
187 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
188 "r_width = %u, f_width = %u\n",
189 crp->reg, value, field, crp->reg_width, crp->field_width);
190
191 mask = ~(mask << pos);
192 value = value << pos;
193
194 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
195 data &= mask;
196 data |= value;
197
198 sh_pfc_unlock_reg(pfc, crp->reg, data);
199 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
200 }
201
sh_pfc_get_config_reg(struct sh_pfc * pfc,u16 enum_id,const struct pinmux_cfg_reg ** crp,unsigned int * fieldp,u32 * valuep)202 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
203 const struct pinmux_cfg_reg **crp,
204 unsigned int *fieldp, u32 *valuep)
205 {
206 unsigned int k = 0;
207
208 while (1) {
209 const struct pinmux_cfg_reg *config_reg =
210 pfc->info->cfg_regs + k;
211 unsigned int r_width = config_reg->reg_width;
212 unsigned int f_width = config_reg->field_width;
213 unsigned int curr_width;
214 unsigned int bit_pos;
215 unsigned int pos = 0;
216 unsigned int m = 0;
217
218 if (!r_width)
219 break;
220
221 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
222 u32 ncomb;
223 u32 n;
224
225 if (f_width)
226 curr_width = f_width;
227 else
228 curr_width = config_reg->var_field_width[m];
229
230 ncomb = 1 << curr_width;
231 for (n = 0; n < ncomb; n++) {
232 if (config_reg->enum_ids[pos + n] == enum_id) {
233 *crp = config_reg;
234 *fieldp = m;
235 *valuep = n;
236 return 0;
237 }
238 }
239 pos += ncomb;
240 m++;
241 }
242 k++;
243 }
244
245 return -EINVAL;
246 }
247
sh_pfc_mark_to_enum(struct sh_pfc * pfc,u16 mark,int pos,u16 * enum_idp)248 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
249 u16 *enum_idp)
250 {
251 const u16 *data = pfc->info->pinmux_data;
252 unsigned int k;
253
254 if (pos) {
255 *enum_idp = data[pos + 1];
256 return pos + 1;
257 }
258
259 for (k = 0; k < pfc->info->pinmux_data_size; k++) {
260 if (data[k] == mark) {
261 *enum_idp = data[k + 1];
262 return k + 1;
263 }
264 }
265
266 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
267 mark);
268 return -EINVAL;
269 }
270
sh_pfc_config_mux(struct sh_pfc * pfc,unsigned mark,int pinmux_type)271 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
272 {
273 const struct pinmux_range *range;
274 int pos = 0;
275
276 switch (pinmux_type) {
277 case PINMUX_TYPE_GPIO:
278 case PINMUX_TYPE_FUNCTION:
279 range = NULL;
280 break;
281
282 case PINMUX_TYPE_OUTPUT:
283 range = &pfc->info->output;
284 break;
285
286 case PINMUX_TYPE_INPUT:
287 range = &pfc->info->input;
288 break;
289
290 default:
291 return -EINVAL;
292 }
293
294 /* Iterate over all the configuration fields we need to update. */
295 while (1) {
296 const struct pinmux_cfg_reg *cr;
297 unsigned int field;
298 u16 enum_id;
299 u32 value;
300 int in_range;
301 int ret;
302
303 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
304 if (pos < 0)
305 return pos;
306
307 if (!enum_id)
308 break;
309
310 /* Check if the configuration field selects a function. If it
311 * doesn't, skip the field if it's not applicable to the
312 * requested pinmux type.
313 */
314 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
315 if (!in_range) {
316 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
317 /* Functions are allowed to modify all
318 * fields.
319 */
320 in_range = 1;
321 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
322 /* Input/output types can only modify fields
323 * that correspond to their respective ranges.
324 */
325 in_range = sh_pfc_enum_in_range(enum_id, range);
326
327 /*
328 * special case pass through for fixed
329 * input-only or output-only pins without
330 * function enum register association.
331 */
332 if (in_range && enum_id == range->force)
333 continue;
334 }
335 /* GPIOs are only allowed to modify function fields. */
336 }
337
338 if (!in_range)
339 continue;
340
341 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
342 if (ret < 0)
343 return ret;
344
345 sh_pfc_write_config_reg(pfc, cr, field, value);
346 }
347
348 return 0;
349 }
350
351 const struct pinmux_bias_reg *
sh_pfc_pin_to_bias_reg(const struct sh_pfc * pfc,unsigned int pin,unsigned int * bit)352 sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
353 unsigned int *bit)
354 {
355 unsigned int i, j;
356
357 for (i = 0; pfc->info->bias_regs[i].puen; i++) {
358 for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
359 if (pfc->info->bias_regs[i].pins[j] == pin) {
360 *bit = j;
361 return &pfc->info->bias_regs[i];
362 }
363 }
364 }
365
366 WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
367
368 return NULL;
369 }
370
sh_pfc_init_ranges(struct sh_pfc * pfc)371 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
372 {
373 struct sh_pfc_pin_range *range;
374 unsigned int nr_ranges;
375 unsigned int i;
376
377 if (pfc->info->pins[0].pin == (u16)-1) {
378 /* Pin number -1 denotes that the SoC doesn't report pin numbers
379 * in its pin arrays yet. Consider the pin numbers range as
380 * continuous and allocate a single range.
381 */
382 pfc->nr_ranges = 1;
383 pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL);
384 if (pfc->ranges == NULL)
385 return -ENOMEM;
386
387 pfc->ranges->start = 0;
388 pfc->ranges->end = pfc->info->nr_pins - 1;
389 pfc->nr_gpio_pins = pfc->info->nr_pins;
390
391 return 0;
392 }
393
394 /* Count, allocate and fill the ranges. The PFC SoC data pins array must
395 * be sorted by pin numbers, and pins without a GPIO port must come
396 * last.
397 */
398 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
399 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
400 nr_ranges++;
401 }
402
403 pfc->nr_ranges = nr_ranges;
404 pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL);
405 if (pfc->ranges == NULL)
406 return -ENOMEM;
407
408 range = pfc->ranges;
409 range->start = pfc->info->pins[0].pin;
410
411 for (i = 1; i < pfc->info->nr_pins; ++i) {
412 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
413 continue;
414
415 range->end = pfc->info->pins[i-1].pin;
416 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
417 pfc->nr_gpio_pins = range->end + 1;
418
419 range++;
420 range->start = pfc->info->pins[i].pin;
421 }
422
423 range->end = pfc->info->pins[i-1].pin;
424 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
425 pfc->nr_gpio_pins = range->end + 1;
426
427 return 0;
428 }
429
sh_pfc_pinctrl_get_pins_count(struct udevice * dev)430 static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev)
431 {
432 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
433
434 return priv->pfc.info->nr_pins;
435 }
436
sh_pfc_pinctrl_get_pin_name(struct udevice * dev,unsigned selector)437 static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev,
438 unsigned selector)
439 {
440 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
441
442 return priv->pfc.info->pins[selector].name;
443 }
444
sh_pfc_pinctrl_get_groups_count(struct udevice * dev)445 static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev)
446 {
447 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
448
449 return priv->pfc.info->nr_groups;
450 }
451
sh_pfc_pinctrl_get_group_name(struct udevice * dev,unsigned selector)452 static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev,
453 unsigned selector)
454 {
455 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
456
457 return priv->pfc.info->groups[selector].name;
458 }
459
sh_pfc_pinctrl_get_pin_muxing(struct udevice * dev,unsigned int selector,char * buf,int size)460 static int sh_pfc_pinctrl_get_pin_muxing(struct udevice *dev,
461 unsigned int selector,
462 char *buf, int size)
463 {
464 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
465 struct sh_pfc_pinctrl *pmx = &priv->pmx;
466 struct sh_pfc *pfc = &priv->pfc;
467 struct sh_pfc_pin_config *cfg;
468 const struct sh_pfc_pin *pin;
469 int idx;
470
471 pin = &priv->pfc.info->pins[selector];
472 if (!pin) {
473 snprintf(buf, size, "Unknown");
474 return -EINVAL;
475 }
476
477 idx = sh_pfc_get_pin_index(pfc, pin->pin);
478 cfg = &pmx->configs[idx];
479 snprintf(buf, size, "%s", cfg->name);
480
481 return 0;
482 }
483
sh_pfc_pinctrl_get_functions_count(struct udevice * dev)484 static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
485 {
486 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
487
488 return priv->pfc.info->nr_functions;
489 }
490
sh_pfc_pinctrl_get_function_name(struct udevice * dev,unsigned selector)491 static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev,
492 unsigned selector)
493 {
494 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
495
496 return priv->pfc.info->functions[selector].name;
497 }
498
sh_pfc_gpio_request_enable(struct udevice * dev,unsigned pin_selector)499 static int sh_pfc_gpio_request_enable(struct udevice *dev,
500 unsigned pin_selector)
501 {
502 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
503 struct sh_pfc_pinctrl *pmx = &priv->pmx;
504 struct sh_pfc *pfc = &priv->pfc;
505 struct sh_pfc_pin_config *cfg;
506 const struct sh_pfc_pin *pin = NULL;
507 int i, ret, idx;
508
509 for (i = 0; i < pfc->info->nr_pins; i++) {
510 if (priv->pfc.info->pins[i].pin != pin_selector)
511 continue;
512
513 pin = &priv->pfc.info->pins[i];
514 break;
515 }
516
517 if (!pin)
518 return -EINVAL;
519
520 idx = sh_pfc_get_pin_index(pfc, pin->pin);
521 cfg = &pmx->configs[idx];
522
523 if (cfg->type != PINMUX_TYPE_NONE) {
524 if (!strcmp(cfg->name, pin->name))
525 return 0;
526
527 dev_err(pfc->dev, "Pin already used as %s\n",
528 cfg->name);
529 return -EBUSY;
530 }
531
532 ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
533 if (ret)
534 return ret;
535
536 cfg->type = PINMUX_TYPE_GPIO;
537 cfg->name = "gpio";
538
539 return 0;
540 }
541
sh_pfc_gpio_disable_free(struct udevice * dev,unsigned pin_selector)542 static int sh_pfc_gpio_disable_free(struct udevice *dev,
543 unsigned pin_selector)
544 {
545 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
546 struct sh_pfc_pinctrl *pmx = &priv->pmx;
547 struct sh_pfc *pfc = &priv->pfc;
548 struct sh_pfc_pin_config *cfg;
549 const struct sh_pfc_pin *pin = NULL;
550 int i, idx;
551
552 for (i = 0; i < pfc->info->nr_pins; i++) {
553 if (priv->pfc.info->pins[i].pin != pin_selector)
554 continue;
555
556 pin = &priv->pfc.info->pins[i];
557 break;
558 }
559
560 if (!pin)
561 return -EINVAL;
562
563 idx = sh_pfc_get_pin_index(pfc, pin->pin);
564 cfg = &pmx->configs[idx];
565
566 cfg->type = PINMUX_TYPE_NONE;
567 cfg->name = "none";
568
569 return 0;
570 }
571
sh_pfc_pinctrl_pin_set(struct udevice * dev,unsigned pin_selector,unsigned func_selector)572 static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector,
573 unsigned func_selector)
574 {
575 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
576 struct sh_pfc_pinctrl *pmx = &priv->pmx;
577 struct sh_pfc *pfc = &priv->pfc;
578 const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector];
579 int idx = sh_pfc_get_pin_index(pfc, pin->pin);
580 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
581 int ret;
582
583 if (cfg->type != PINMUX_TYPE_NONE) {
584 if (!strcmp(cfg->name, pin->name))
585 return 0;
586
587 dev_err(pfc->dev, "Pin already used as %s\n",
588 cfg->name);
589 return -EBUSY;
590 }
591
592 ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
593 if (ret)
594 return ret;
595
596 cfg->type = PINMUX_TYPE_FUNCTION;
597 cfg->name = "function";
598
599 return 0;
600 }
601
sh_pfc_pinctrl_group_set(struct udevice * dev,unsigned group_selector,unsigned func_selector)602 static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,
603 unsigned func_selector)
604 {
605 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
606 struct sh_pfc_pinctrl *pmx = &priv->pmx;
607 struct sh_pfc *pfc = &priv->pfc;
608 const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector];
609 bool grp_pins_configured = true;
610 struct sh_pfc_pin_config *cfg;
611 unsigned int i;
612 int ret = 0;
613 int idx;
614
615 for (i = 0; i < grp->nr_pins; ++i) {
616 idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
617 cfg = &pmx->configs[idx];
618
619 if (cfg->type != PINMUX_TYPE_NONE) {
620 if (!strcmp(cfg->name, grp->name))
621 continue;
622
623 dev_err(pfc->dev, "Pin already used as %s\n",
624 cfg->name);
625 ret = -EBUSY;
626 goto done;
627 } else {
628 grp_pins_configured = false;
629 }
630 }
631
632 if (grp_pins_configured)
633 return 0;
634
635 for (i = 0; i < grp->nr_pins; ++i) {
636 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
637 if (ret < 0)
638 break;
639
640 idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
641 cfg = &pmx->configs[idx];
642 cfg->type = PINMUX_TYPE_FUNCTION;
643 cfg->name = priv->pfc.info->groups[group_selector].name;
644 }
645
646 done:
647 return ret;
648 }
649 #if CONFIG_IS_ENABLED(PINCONF)
650 static const struct pinconf_param sh_pfc_pinconf_params[] = {
651 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
652 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
653 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
654 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
655 { "power-source", PIN_CONFIG_POWER_SOURCE, 3300 },
656 };
657
658 static void __iomem *
sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc * pfc,unsigned int pin,unsigned int * offset,unsigned int * size)659 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin,
660 unsigned int *offset, unsigned int *size)
661 {
662 const struct pinmux_drive_reg_field *field;
663 const struct pinmux_drive_reg *reg;
664 unsigned int i;
665
666 for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
667 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
668 field = ®->fields[i];
669
670 if (field->size && field->pin == pin) {
671 *offset = field->offset;
672 *size = field->size;
673
674 return (void __iomem *)(uintptr_t)reg->reg;
675 }
676 }
677 }
678
679 return NULL;
680 }
681
sh_pfc_pinconf_set_drive_strength(struct sh_pfc * pfc,unsigned int pin,u16 strength)682 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
683 unsigned int pin, u16 strength)
684 {
685 unsigned int offset;
686 unsigned int size;
687 unsigned int step;
688 void __iomem *reg;
689 u32 val;
690
691 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
692 if (!reg)
693 return -EINVAL;
694
695 step = size == 2 ? 6 : 3;
696
697 if (strength < step || strength > 24)
698 return -EINVAL;
699
700 /* Convert the value from mA based on a full drive strength value of
701 * 24mA. We can make the full value configurable later if needed.
702 */
703 strength = strength / step - 1;
704
705 val = sh_pfc_read_raw_reg(reg, 32);
706 val &= ~GENMASK(offset + 4 - 1, offset);
707 val |= strength << offset;
708
709 sh_pfc_unlock_reg(pfc, (uintptr_t)reg, val);
710 sh_pfc_write_raw_reg(reg, 32, val);
711
712 return 0;
713 }
714
715 /* Check whether the requested parameter is supported for a pin. */
sh_pfc_pinconf_validate(struct sh_pfc * pfc,unsigned int _pin,unsigned int param)716 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
717 unsigned int param)
718 {
719 int idx = sh_pfc_get_pin_index(pfc, _pin);
720 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
721
722 switch (param) {
723 case PIN_CONFIG_BIAS_DISABLE:
724 return pin->configs &
725 (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
726
727 case PIN_CONFIG_BIAS_PULL_UP:
728 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
729
730 case PIN_CONFIG_BIAS_PULL_DOWN:
731 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
732
733 case PIN_CONFIG_DRIVE_STRENGTH:
734 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
735
736 case PIN_CONFIG_POWER_SOURCE:
737 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
738
739 default:
740 return false;
741 }
742 }
743
sh_pfc_pinconf_set(struct sh_pfc_pinctrl * pmx,unsigned _pin,unsigned int param,unsigned int arg)744 static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
745 unsigned int param, unsigned int arg)
746 {
747 struct sh_pfc *pfc = pmx->pfc;
748 void __iomem *pocctrl;
749 u32 addr, val;
750 int bit, ret;
751
752 if (!sh_pfc_pinconf_validate(pfc, _pin, param))
753 return -ENOTSUPP;
754
755 switch (param) {
756 case PIN_CONFIG_BIAS_PULL_UP:
757 case PIN_CONFIG_BIAS_PULL_DOWN:
758 case PIN_CONFIG_BIAS_DISABLE:
759 if (!pfc->info->ops || !pfc->info->ops->set_bias)
760 return -ENOTSUPP;
761
762 pfc->info->ops->set_bias(pfc, _pin, param);
763
764 break;
765
766 case PIN_CONFIG_DRIVE_STRENGTH:
767 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
768 if (ret < 0)
769 return ret;
770
771 break;
772
773 case PIN_CONFIG_POWER_SOURCE:
774 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
775 return -ENOTSUPP;
776
777 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr);
778 if (bit < 0) {
779 printf("invalid pin %#x", _pin);
780 return bit;
781 }
782
783 if (arg != 1800 && arg != 3300)
784 return -EINVAL;
785
786 pocctrl = (void __iomem *)(uintptr_t)addr;
787
788 val = sh_pfc_read_raw_reg(pocctrl, 32);
789 if (arg == 3300)
790 val |= BIT(bit);
791 else
792 val &= ~BIT(bit);
793
794 sh_pfc_unlock_reg(pfc, addr, val);
795 sh_pfc_write_raw_reg(pocctrl, 32, val);
796
797 break;
798
799 default:
800 return -ENOTSUPP;
801 }
802
803 return 0;
804 }
805
sh_pfc_pinconf_pin_set(struct udevice * dev,unsigned int pin_selector,unsigned int param,unsigned int arg)806 static int sh_pfc_pinconf_pin_set(struct udevice *dev,
807 unsigned int pin_selector,
808 unsigned int param, unsigned int arg)
809 {
810 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
811 struct sh_pfc_pinctrl *pmx = &priv->pmx;
812 struct sh_pfc *pfc = &priv->pfc;
813 const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector];
814
815 sh_pfc_pinconf_set(pmx, pin->pin, param, arg);
816
817 return 0;
818 }
819
sh_pfc_pinconf_group_set(struct udevice * dev,unsigned int group_selector,unsigned int param,unsigned int arg)820 static int sh_pfc_pinconf_group_set(struct udevice *dev,
821 unsigned int group_selector,
822 unsigned int param, unsigned int arg)
823 {
824 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
825 struct sh_pfc_pinctrl *pmx = &priv->pmx;
826 struct sh_pfc *pfc = &priv->pfc;
827 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector];
828 unsigned int i;
829
830 for (i = 0; i < grp->nr_pins; i++)
831 sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg);
832
833 return 0;
834 }
835 #endif
836
837 static struct pinctrl_ops sh_pfc_pinctrl_ops = {
838 .get_pins_count = sh_pfc_pinctrl_get_pins_count,
839 .get_pin_name = sh_pfc_pinctrl_get_pin_name,
840 .get_groups_count = sh_pfc_pinctrl_get_groups_count,
841 .get_group_name = sh_pfc_pinctrl_get_group_name,
842 .get_pin_muxing = sh_pfc_pinctrl_get_pin_muxing,
843 .get_functions_count = sh_pfc_pinctrl_get_functions_count,
844 .get_function_name = sh_pfc_pinctrl_get_function_name,
845
846 #if CONFIG_IS_ENABLED(PINCONF)
847 .pinconf_num_params = ARRAY_SIZE(sh_pfc_pinconf_params),
848 .pinconf_params = sh_pfc_pinconf_params,
849 .pinconf_set = sh_pfc_pinconf_pin_set,
850 .pinconf_group_set = sh_pfc_pinconf_group_set,
851 #endif
852 .pinmux_set = sh_pfc_pinctrl_pin_set,
853 .pinmux_group_set = sh_pfc_pinctrl_group_set,
854 .set_state = pinctrl_generic_set_state,
855
856 .gpio_request_enable = sh_pfc_gpio_request_enable,
857 .gpio_disable_free = sh_pfc_gpio_disable_free,
858 };
859
sh_pfc_map_pins(struct sh_pfc * pfc,struct sh_pfc_pinctrl * pmx)860 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
861 {
862 unsigned int i;
863
864 /* Allocate and initialize the pins and configs arrays. */
865 pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins,
866 GFP_KERNEL);
867 if (unlikely(!pmx->configs))
868 return -ENOMEM;
869
870 for (i = 0; i < pfc->info->nr_pins; ++i) {
871 struct sh_pfc_pin_config *cfg = &pmx->configs[i];
872 cfg->type = PINMUX_TYPE_NONE;
873 cfg->name = "none";
874 }
875
876 return 0;
877 }
878
879
sh_pfc_pinctrl_probe(struct udevice * dev)880 static int sh_pfc_pinctrl_probe(struct udevice *dev)
881 {
882 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
883 enum sh_pfc_model model = dev_get_driver_data(dev);
884 fdt_addr_t base;
885
886 base = dev_read_addr(dev);
887 if (base == FDT_ADDR_T_NONE)
888 return -EINVAL;
889
890 priv->pfc.regs = devm_ioremap(dev, base, SZ_2K);
891 if (!priv->pfc.regs)
892 return -ENOMEM;
893
894 #ifdef CONFIG_PINCTRL_PFC_R8A7790
895 if (model == SH_PFC_R8A7790)
896 priv->pfc.info = &r8a7790_pinmux_info;
897 #endif
898 #ifdef CONFIG_PINCTRL_PFC_R8A7791
899 if (model == SH_PFC_R8A7791)
900 priv->pfc.info = &r8a7791_pinmux_info;
901 #endif
902 #ifdef CONFIG_PINCTRL_PFC_R8A7792
903 if (model == SH_PFC_R8A7792)
904 priv->pfc.info = &r8a7792_pinmux_info;
905 #endif
906 #ifdef CONFIG_PINCTRL_PFC_R8A7793
907 if (model == SH_PFC_R8A7793)
908 priv->pfc.info = &r8a7793_pinmux_info;
909 #endif
910 #ifdef CONFIG_PINCTRL_PFC_R8A7794
911 if (model == SH_PFC_R8A7794)
912 priv->pfc.info = &r8a7794_pinmux_info;
913 #endif
914 #ifdef CONFIG_PINCTRL_PFC_R8A7795
915 if (model == SH_PFC_R8A7795)
916 priv->pfc.info = &r8a7795_pinmux_info;
917 #endif
918 #ifdef CONFIG_PINCTRL_PFC_R8A7796
919 if (model == SH_PFC_R8A7796)
920 priv->pfc.info = &r8a7796_pinmux_info;
921 #endif
922 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
923 if (model == SH_PFC_R8A774A1)
924 priv->pfc.info = &r8a774a1_pinmux_info;
925 #endif
926 #ifdef CONFIG_PINCTRL_PFC_R8A774B1
927 if (model == SH_PFC_R8A774B1)
928 priv->pfc.info = &r8a774b1_pinmux_info;
929 #endif
930 #ifdef CONFIG_PINCTRL_PFC_R8A774C0
931 if (model == SH_PFC_R8A774C0)
932 priv->pfc.info = &r8a774c0_pinmux_info;
933 #endif
934 #ifdef CONFIG_PINCTRL_PFC_R8A774E1
935 if (model == SH_PFC_R8A774E1)
936 priv->pfc.info = &r8a774e1_pinmux_info;
937 #endif
938 #ifdef CONFIG_PINCTRL_PFC_R8A77965
939 if (model == SH_PFC_R8A77965)
940 priv->pfc.info = &r8a77965_pinmux_info;
941 #endif
942 #ifdef CONFIG_PINCTRL_PFC_R8A77970
943 if (model == SH_PFC_R8A77970)
944 priv->pfc.info = &r8a77970_pinmux_info;
945 #endif
946 #ifdef CONFIG_PINCTRL_PFC_R8A77980
947 if (model == SH_PFC_R8A77980)
948 priv->pfc.info = &r8a77980_pinmux_info;
949 #endif
950 #ifdef CONFIG_PINCTRL_PFC_R8A77990
951 if (model == SH_PFC_R8A77990)
952 priv->pfc.info = &r8a77990_pinmux_info;
953 #endif
954 #ifdef CONFIG_PINCTRL_PFC_R8A77995
955 if (model == SH_PFC_R8A77995)
956 priv->pfc.info = &r8a77995_pinmux_info;
957 #endif
958
959 priv->pmx.pfc = &priv->pfc;
960 sh_pfc_init_ranges(&priv->pfc);
961 sh_pfc_map_pins(&priv->pfc, &priv->pmx);
962
963 return 0;
964 }
965
966 static const struct udevice_id sh_pfc_pinctrl_ids[] = {
967 #ifdef CONFIG_PINCTRL_PFC_R8A7790
968 {
969 .compatible = "renesas,pfc-r8a7790",
970 .data = SH_PFC_R8A7790,
971 },
972 #endif
973 #ifdef CONFIG_PINCTRL_PFC_R8A7791
974 {
975 .compatible = "renesas,pfc-r8a7791",
976 .data = SH_PFC_R8A7791,
977 },
978 #endif
979 #ifdef CONFIG_PINCTRL_PFC_R8A7792
980 {
981 .compatible = "renesas,pfc-r8a7792",
982 .data = SH_PFC_R8A7792,
983 },
984 #endif
985 #ifdef CONFIG_PINCTRL_PFC_R8A7793
986 {
987 .compatible = "renesas,pfc-r8a7793",
988 .data = SH_PFC_R8A7793,
989 },
990 #endif
991 #ifdef CONFIG_PINCTRL_PFC_R8A7794
992 {
993 .compatible = "renesas,pfc-r8a7794",
994 .data = SH_PFC_R8A7794,
995 },
996 #endif
997 #ifdef CONFIG_PINCTRL_PFC_R8A7795
998 {
999 .compatible = "renesas,pfc-r8a7795",
1000 .data = SH_PFC_R8A7795,
1001 },
1002 #endif
1003 #ifdef CONFIG_PINCTRL_PFC_R8A7796
1004 {
1005 .compatible = "renesas,pfc-r8a7796",
1006 .data = SH_PFC_R8A7796,
1007 },
1008 #endif
1009 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
1010 {
1011 .compatible = "renesas,pfc-r8a774a1",
1012 .data = SH_PFC_R8A774A1,
1013 },
1014 #endif
1015 #ifdef CONFIG_PINCTRL_PFC_R8A774B1
1016 {
1017 .compatible = "renesas,pfc-r8a774b1",
1018 .data = SH_PFC_R8A774B1,
1019 },
1020 #endif
1021 #ifdef CONFIG_PINCTRL_PFC_R8A774C0
1022 {
1023 .compatible = "renesas,pfc-r8a774c0",
1024 .data = SH_PFC_R8A774C0,
1025 },
1026 #endif
1027 #ifdef CONFIG_PINCTRL_PFC_R8A774E1
1028 {
1029 .compatible = "renesas,pfc-r8a774e1",
1030 .data = SH_PFC_R8A774E1,
1031 },
1032 #endif
1033 #ifdef CONFIG_PINCTRL_PFC_R8A77965
1034 {
1035 .compatible = "renesas,pfc-r8a77965",
1036 .data = SH_PFC_R8A77965,
1037 },
1038 #endif
1039 #ifdef CONFIG_PINCTRL_PFC_R8A77970
1040 {
1041 .compatible = "renesas,pfc-r8a77970",
1042 .data = SH_PFC_R8A77970,
1043 },
1044 #endif
1045 #ifdef CONFIG_PINCTRL_PFC_R8A77980
1046 {
1047 .compatible = "renesas,pfc-r8a77980",
1048 .data = SH_PFC_R8A77980,
1049 },
1050 #endif
1051 #ifdef CONFIG_PINCTRL_PFC_R8A77990
1052 {
1053 .compatible = "renesas,pfc-r8a77990",
1054 .data = SH_PFC_R8A77990,
1055 },
1056 #endif
1057 #ifdef CONFIG_PINCTRL_PFC_R8A77995
1058 {
1059 .compatible = "renesas,pfc-r8a77995",
1060 .data = SH_PFC_R8A77995,
1061 },
1062 #endif
1063 { },
1064 };
1065
1066 U_BOOT_DRIVER(pinctrl_sh_pfc) = {
1067 .name = "sh_pfc_pinctrl",
1068 .id = UCLASS_PINCTRL,
1069 .of_match = sh_pfc_pinctrl_ids,
1070 .priv_auto = sizeof(struct sh_pfc_pinctrl_priv),
1071 .ops = &sh_pfc_pinctrl_ops,
1072 .probe = sh_pfc_pinctrl_probe,
1073 };
1074