1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
4 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
5 */
6
7 #include <common.h>
8 #include <init.h>
9 #include <irq_func.h>
10 #include <asm/global_data.h>
11 #include <linux/delay.h>
12
13 #include <asm/timer.h>
14 #include <asm/immap.h>
15 #include <asm/io.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 static ulong timestamp;
20
21 #if defined(CONFIG_SLTTMR)
22 #ifndef CONFIG_SYS_UDELAY_BASE
23 # error "uDelay base not defined!"
24 #endif
25
26 #if !defined(CONFIG_SYS_TMR_BASE) || !defined(CONFIG_SYS_INTR_BASE) || !defined(CONFIG_SYS_TMRINTR_NO) || !defined(CONFIG_SYS_TMRINTR_MASK)
27 # error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
28 #endif
29 extern void dtimer_intr_setup(void);
30
__udelay(unsigned long usec)31 void __udelay(unsigned long usec)
32 {
33 slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE);
34 u32 now, freq;
35
36 /* 1 us period */
37 freq = CONFIG_SYS_TIMER_PRESCALER;
38
39 /* Disable */
40 out_be32(&timerp->cr, 0);
41 out_be32(&timerp->tcnt, usec * freq);
42 out_be32(&timerp->cr, SLT_CR_TEN);
43
44 now = in_be32(&timerp->cnt);
45 while (now != 0)
46 now = in_be32(&timerp->cnt);
47
48 setbits_be32(&timerp->sr, SLT_SR_ST);
49 out_be32(&timerp->cr, 0);
50 }
51
dtimer_interrupt(void * not_used)52 void dtimer_interrupt(void *not_used)
53 {
54 slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
55
56 /* check for timer interrupt asserted */
57 if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) {
58 setbits_be32(&timerp->sr, SLT_SR_ST);
59 timestamp++;
60 return;
61 }
62 }
63
timer_init(void)64 int timer_init(void)
65 {
66 slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
67
68 timestamp = 0;
69
70 /* disable timer */
71 out_be32(&timerp->cr, 0);
72 out_be32(&timerp->tcnt, 0);
73 /* clear status */
74 out_be32(&timerp->sr, SLT_SR_BE | SLT_SR_ST);
75
76 /* initialize and enable timer interrupt */
77 irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
78
79 /* Interrupt every ms */
80 out_be32(&timerp->tcnt, 1000 * CONFIG_SYS_TIMER_PRESCALER);
81
82 dtimer_intr_setup();
83
84 /* set a period of 1us, set timer mode to restart and
85 enable timer and interrupt */
86 out_be32(&timerp->cr, SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN);
87 return 0;
88 }
89
get_timer(ulong base)90 ulong get_timer(ulong base)
91 {
92 return (timestamp - base);
93 }
94
95 #endif /* CONFIG_SLTTMR */
96