1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Renesas RCar Gen3 CPG MSSR driver
4 *
5 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
6 *
7 * Based on the following driver from Linux kernel:
8 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
9 *
10 * Copyright (C) 2016 Glider bvba
11 */
12 #include <common.h>
13 #include <clk-uclass.h>
14 #include <dm.h>
15 #include <errno.h>
16 #include <log.h>
17 #include <wait_bit.h>
18 #include <asm/io.h>
19 #include <linux/bitops.h>
20
21 #include <dt-bindings/clock/renesas-cpg-mssr.h>
22
23 #include "renesas-cpg-mssr.h"
24
renesas_clk_is_mod(struct clk * clk)25 bool renesas_clk_is_mod(struct clk *clk)
26 {
27 return (clk->id >> 16) == CPG_MOD;
28 }
29
renesas_clk_get_mod(struct clk * clk,struct cpg_mssr_info * info,const struct mssr_mod_clk ** mssr)30 int renesas_clk_get_mod(struct clk *clk, struct cpg_mssr_info *info,
31 const struct mssr_mod_clk **mssr)
32 {
33 const unsigned long clkid = clk->id & 0xffff;
34 int i;
35
36 for (i = 0; i < info->mod_clk_size; i++) {
37 if (info->mod_clk[i].id !=
38 (info->mod_clk_base + MOD_CLK_PACK(clkid)))
39 continue;
40
41 *mssr = &info->mod_clk[i];
42 return 0;
43 }
44
45 return -ENODEV;
46 }
47
renesas_clk_get_core(struct clk * clk,struct cpg_mssr_info * info,const struct cpg_core_clk ** core)48 int renesas_clk_get_core(struct clk *clk, struct cpg_mssr_info *info,
49 const struct cpg_core_clk **core)
50 {
51 const unsigned long clkid = clk->id & 0xffff;
52 int i;
53
54 for (i = 0; i < info->core_clk_size; i++) {
55 if (info->core_clk[i].id != clkid)
56 continue;
57
58 *core = &info->core_clk[i];
59 return 0;
60 }
61
62 return -ENODEV;
63 }
64
renesas_clk_get_parent(struct clk * clk,struct cpg_mssr_info * info,struct clk * parent)65 int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
66 struct clk *parent)
67 {
68 const struct cpg_core_clk *core;
69 const struct mssr_mod_clk *mssr;
70 int ret;
71
72 if (renesas_clk_is_mod(clk)) {
73 ret = renesas_clk_get_mod(clk, info, &mssr);
74 if (ret)
75 return ret;
76
77 parent->id = mssr->parent;
78 } else {
79 ret = renesas_clk_get_core(clk, info, &core);
80 if (ret)
81 return ret;
82
83 if (core->type == CLK_TYPE_IN)
84 parent->id = ~0; /* Top-level clock */
85 else
86 parent->id = core->parent;
87 }
88
89 parent->dev = clk->dev;
90
91 return 0;
92 }
93
renesas_clk_endisable(struct clk * clk,void __iomem * base,struct cpg_mssr_info * info,bool enable)94 int renesas_clk_endisable(struct clk *clk, void __iomem *base,
95 struct cpg_mssr_info *info, bool enable)
96 {
97 const unsigned long clkid = clk->id & 0xffff;
98 const unsigned int reg = clkid / 100;
99 const unsigned int bit = clkid % 100;
100 const u32 bitmask = BIT(bit);
101
102 if (!renesas_clk_is_mod(clk))
103 return -EINVAL;
104
105 debug("%s[%i] MSTP %lu=%02u/%02u %s\n", __func__, __LINE__,
106 clkid, reg, bit, enable ? "ON" : "OFF");
107
108 if (enable) {
109 clrbits_le32(base + info->control_regs[reg], bitmask);
110 return wait_for_bit_le32(base + info->status_regs[reg],
111 bitmask, 0, 100, 0);
112 } else {
113 setbits_le32(base + info->control_regs[reg], bitmask);
114 return 0;
115 }
116 }
117
renesas_clk_remove(void __iomem * base,struct cpg_mssr_info * info)118 int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info)
119 {
120 unsigned int i;
121
122 /* Stop TMU0 */
123 clrbits_le32(TMU_BASE + TSTR0, TSTR0_STR0);
124
125 /* Stop module clock */
126 for (i = 0; i < info->mstp_table_size; i++) {
127 clrsetbits_le32(base + info->control_regs[i],
128 info->mstp_table[i].sdis,
129 info->mstp_table[i].sen);
130 clrsetbits_le32(base + RMSTPCR(i),
131 info->mstp_table[i].rdis,
132 info->mstp_table[i].ren);
133 }
134
135 return 0;
136 }
137