1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Actions Semi S900 Register Definitions 4 * 5 * Copyright (C) 2015 Actions Semi Co., Ltd. 6 * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 7 * 8 */ 9 10 #ifndef _OWL_REGS_S900_H_ 11 #define _OWL_REGS_S900_H_ 12 13 /* CMU registers */ 14 #define CMU_COREPLL (0x0000) 15 #define CMU_DEVPLL (0x0004) 16 #define CMU_DDRPLL (0x0008) 17 #define CMU_NANDPLL (0x000C) 18 #define CMU_DISPLAYPLL (0x0010) 19 #define CMU_AUDIOPLL (0x0014) 20 #define CMU_TVOUTPLL (0x0018) 21 #define CMU_BUSCLK (0x001C) 22 #define CMU_SENSORCLK (0x0020) 23 #define CMU_LCDCLK (0x0024) 24 #define CMU_DSICLK (0x0028) 25 #define CMU_CSICLK (0x002C) 26 #define CMU_DECLK (0x0030) 27 #define CMU_BISPCLK (0x0034) 28 #define CMU_IMXCLK (0x0038) 29 #define CMU_HDECLK (0x003C) 30 #define CMU_VDECLK (0x0040) 31 #define CMU_VCECLK (0x0044) 32 #define CMU_NANDCCLK (0x004C) 33 #define CMU_SD0CLK (0x0050) 34 #define CMU_SD1CLK (0x0054) 35 #define CMU_SD2CLK (0x0058) 36 #define CMU_UART0CLK (0x005C) 37 #define CMU_UART1CLK (0x0060) 38 #define CMU_UART2CLK (0x0064) 39 #define CMU_PWM0CLK (0x0070) 40 #define CMU_PWM1CLK (0x0074) 41 #define CMU_PWM2CLK (0x0078) 42 #define CMU_PWM3CLK (0x007C) 43 #define CMU_USBPLL (0x0080) 44 #define CMU_ASSISTPLL (0x0084) 45 #define CMU_EDPCLK (0x0088) 46 #define CMU_GPU3DCLK (0x0090) 47 #define CMU_CORECTL (0x009C) 48 #define CMU_DEVCLKEN0 (0x00A0) 49 #define CMU_DEVCLKEN1 (0x00A4) 50 #define CMU_DEVRST0 (0x00A8) 51 #define CMU_DEVRST1 (0x00AC) 52 #define CMU_UART3CLK (0x00B0) 53 #define CMU_UART4CLK (0x00B4) 54 #define CMU_UART5CLK (0x00B8) 55 #define CMU_UART6CLK (0x00BC) 56 #define CMU_TLSCLK (0x00C0) 57 #define CMU_SD3CLK (0x00C4) 58 #define CMU_PWM4CLK (0x00C8) 59 #define CMU_PWM5CLK (0x00CC) 60 #define CMU_ANALOGDEBUG (0x00D4) 61 #define CMU_TVOUTPLLDEBUG0 (0x00EC) 62 #define CMU_TVOUTPLLDEBUG1 (0x00FC) 63 64 #define CMU_DEVCLKEN1_ETH BIT(22) 65 #define CLK_ETHERNET CLK_ETH_MAC 66 #define CMU_ETHERNETPLL CMU_ASSISTPLL 67 68 #endif 69