1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2007 Freescale Semiconductor, Inc.
4 *
5 * (C) Copyright 2000
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 */
8
9 #include <common.h>
10 #include <clock_legacy.h>
11 #include <asm/global_data.h>
12 #include <linux/libfdt.h>
13 #include <fdt_support.h>
14 #include <asm/processor.h>
15
16 extern void ft_qe_setup(void *blob);
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 #if defined(CONFIG_BOOTCOUNT_LIMIT) && \
21 (defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X))
22 #include <linux/immap_qe.h>
23
fdt_fixup_muram(void * blob)24 void fdt_fixup_muram (void *blob)
25 {
26 ulong data[2];
27
28 data[0] = 0;
29 data[1] = QE_MURAM_SIZE - 2 * sizeof(unsigned long);
30 do_fixup_by_compat(blob, "fsl,qe-muram-data", "reg",
31 data, sizeof (data), 0);
32 }
33 #endif
34
ft_cpu_setup(void * blob,struct bd_info * bd)35 void ft_cpu_setup(void *blob, struct bd_info *bd)
36 {
37 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
38 int spridr = immr->sysconf.spridr;
39
40 /*
41 * delete crypto node if not on an E-processor
42 * initial revisions of the MPC834xE/6xE have the original SEC 2.0.
43 * EA revisions got the SEC uprevved to 2.4 but since the default device
44 * tree contains SEC 2.0 properties we uprev them here.
45 */
46 if (!IS_E_PROCESSOR(spridr))
47 fdt_fixup_crypto_node(blob, 0);
48 else if (IS_E_PROCESSOR(spridr) &&
49 (SPR_FAMILY(spridr) == SPR_834X_FAMILY ||
50 SPR_FAMILY(spridr) == SPR_836X_FAMILY) &&
51 REVID_MAJOR(spridr) >= 2)
52 fdt_fixup_crypto_node(blob, 0x0204);
53
54 #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
55 defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\
56 defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5)
57 #ifdef CONFIG_ARCH_MPC8313
58 /*
59 * mpc8313e erratum IPIC1 swapped TSEC interrupt ID numbers on rev. 1
60 * h/w (see AN3545). The base device tree in use has rev. 1 ID numbers,
61 * so if on Rev. 2 (and higher) h/w, we fix them up here
62 */
63 if (REVID_MAJOR(immr->sysconf.spridr) >= 2) {
64 int nodeoffset, path;
65 const char *prop;
66
67 nodeoffset = fdt_path_offset(blob, "/aliases");
68 if (nodeoffset >= 0) {
69 #if defined(CONFIG_HAS_ETH0)
70 prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
71 if (prop) {
72 u32 tmp[] = { 32, 0x8, 33, 0x8, 34, 0x8 };
73
74 path = fdt_path_offset(blob, prop);
75 prop = fdt_getprop(blob, path, "interrupts",
76 NULL);
77 if (prop)
78 fdt_setprop(blob, path, "interrupts",
79 &tmp, sizeof(tmp));
80 }
81 #endif
82 #if defined(CONFIG_HAS_ETH1)
83 prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
84 if (prop) {
85 u32 tmp[] = { 35, 0x8, 36, 0x8, 37, 0x8 };
86
87 path = fdt_path_offset(blob, prop);
88 prop = fdt_getprop(blob, path, "interrupts",
89 NULL);
90 if (prop)
91 fdt_setprop(blob, path, "interrupts",
92 &tmp, sizeof(tmp));
93 }
94 #endif
95 }
96 }
97 #endif
98 #endif
99
100 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
101 "timebase-frequency", (bd->bi_busfreq / 4), 1);
102 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
103 "bus-frequency", bd->bi_busfreq, 1);
104 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
105 "clock-frequency", gd->arch.core_clk, 1);
106 do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
107 "bus-frequency", bd->bi_busfreq, 1);
108 do_fixup_by_compat_u32(blob, "fsl,soc",
109 "bus-frequency", bd->bi_busfreq, 1);
110 do_fixup_by_compat_u32(blob, "fsl,soc",
111 "clock-frequency", bd->bi_busfreq, 1);
112 do_fixup_by_compat_u32(blob, "fsl,immr",
113 "bus-frequency", bd->bi_busfreq, 1);
114 do_fixup_by_compat_u32(blob, "fsl,immr",
115 "clock-frequency", bd->bi_busfreq, 1);
116 #ifdef CONFIG_QE
117 ft_qe_setup(blob);
118 #endif
119
120 #ifdef CONFIG_SYS_NS16550
121 do_fixup_by_compat_u32(blob, "ns16550",
122 "clock-frequency", get_serial_clock(), 1);
123 #endif
124
125 fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
126
127 #if defined(CONFIG_BOOTCOUNT_LIMIT) && \
128 (defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X))
129 fdt_fixup_muram (blob);
130 #endif
131 }
132