1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Hitachi Power Grids TUGE1 Device Tree Source
4 *
5 * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
6 *
7 */
8
9/dts-v1/;
10
11#include "km8321.dtsi"
12
13/ {
14	model = "TUGE1";
15	compatible = "hitachi,kmpbec8321";
16	#address-cells = <1>;
17	#size-cells = <1>;
18
19	aliases {
20		ethernet0 = &enet_piggy2;
21		serial0 = &serial0;
22	};
23};
24
25&par_io {
26	/* UCC5 as HDLC controller for ICN */
27	pio_ucc5: ucc_pin@04 {
28		pio-map = <
29			/* port  pin  dir  open_drain  assignment  has_irq */
30			2   0  1  0  2  0   /* TxD0 */
31			2   8  2  0  2  0   /* RxD0 */
32			2  29  2  0  2  0   /* CTS */
33			3  30  2  0  1  0   /* ICN CLK */
34			>;
35	};
36
37	/* UCC4 Piggy Ethernet */
38	pio_ucc4: ucc_pin@03 {
39		pio-map = <
40			/* port pin dir open_drain assignment has_irq */
41			3   4  3  0  2  0	/* MDIO */
42			3   5  1  0  2  0	/* MDC  */
43
44			1 18  1  0  1  0	/* TxD0 */
45			1 19  1  0  1  0	/* TxD1 */
46			1 22  2  0  1  0	/* RxD0 */
47			1 23  2  0  1  0	/* RxD1 */
48			1 26  2  0  1  0	/* RX_ER */
49			1 28  2  0  1  0	/* RX_DV */
50			1 30  1  0  1  0	/* TX_EN */
51			1 31  2  0  1  0	/* CRS */
52			3  10  2  0  3  0 /* UCC4_RMII_CLK (CLK17) */
53		>;
54	};
55
56	pio_spi: spi_pin@01 {
57		pio-map = <
58			/*
59			 *port pin dir open_drain assignment has_irq
60			 * SPI_MOSI (PD0, bi, f3)
61			 */
62			3  0  3  0  1  0
63			/* SPI_MISO (PD1, bi, f3) */
64			3  1  3  0  1  0
65			/* SPI_CLK  (PD2, bi, f3) */
66			3  2  3  0  1  0
67		>;
68	};
69};
70
71&localbus {
72	ranges = <0 0 0xf0000000 0x04000000     /* LB 0 Flash (boot) */
73		  1 0 0xe8000000 0x01000000     /* LB 1 PRIO1 and Piggy */
74		  2 0 0xa0000000 0x10000000>;   /* LB 2 PAXI */
75
76	flash@0,0 {
77		compatible = "cfi-flash";
78		reg = <0 0x00000000 0x04000000>;
79		bank-width = <2>;
80		#address-cells = <1>;
81		#size-cells = <1>;
82
83		partition@0 { /* 768KB */
84			label = "u-boot";
85			reg = <0 0xC0000>;
86		};
87		partition@c0000 { /* 128KB */
88			label = "env";
89			reg = <0xc0000 0x20000>;
90		};
91		partition@e0000 { /* 128KB */
92			label = "envred";
93			reg = <0xe0000 0x20000>;
94		};
95		partition@100000 { /* 64512KB */
96			label = "ubi0";
97			reg = <0x100000 0x3F00000>;
98		};
99	};
100};
101